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| www..com FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM25-10135-5E 2MC-8L F 8-BIT MICROCONTROLLER MB89530/530H/530A Series HARDWARE MANUAL 2MC-8L F 8-BIT MICROCONTROLLER MB89530/530H/530A Series HARDWARE MANUAL FUJITSU LIMITED PREFACE I Objectives and Intended Readers Thank you for purchasing Fujitsu semiconductor products. The MB89530/530H/530A series of microcontrollers was developed as a general-purpose product in the F2MC (R)*-8L series that comprises the proprietary 8-bit one-chip microcontroller that supports application specific ICs (ASICs). This product is designed for a broad range of uses, from consumer products to industrial equipment, such as portable devices. This manual describes the functions and operations of the MB89530/530H/530A series of microcontrollers for engineers who develop products using this series. Be sure to read this manual thoroughly. For details on the instructions, see the F2MC Programming Manual. I Trademark F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of Fujitsu Limited. I Organization of this manual This manual consists of the following 23 chapters and appendix: CHAPTER 1 "OVERVIEW" This chapter explains the features and basic specifications of the MB89530/530H/530A series of microcontrollers. CHAPTER 2 "HANDLING DEVICE" This chapter describes the precautions to be taken when using the MB89530/530H/530A series of microcontrollers. CHAPTER 3 "CPU" This chapter describes the functions and operations of the CPU. CHAPTER 4 "I/O PORTS" This chapter describes the functions and operations of the I/O port. CHAPTER 5 "TIMEBASE TIMER" This chapter describes the functions and operations of the timebase timer. CHAPTER 6 "WATCHDOG TIMER" This chapter describes the functions and operations of the watchdog timer. CHAPTER 7 "WATCH PRESCALER" This chapter describes the functions and operations of the watch prescaler. CHAPTER 8 "2-CHANNEL 8-BIT PWM TIMERS" This chapter describes the functions and operations of the 2-channel 8-bit PWM timer. CHAPTER 9 "PULSE-WIDTH COUNT TIMER (PWC)" This chapter describes the functions and operations of the pulse width count timer (PWC). i CHAPTER 10 "6-BIT PPG TIMER" This chapter describes the functions and operations of 6-bit PPG timer. CHAPTER 11 "12-BIT PPG TIMER" This chapter describes the functions and operations of the 12-bit PPG timer. CHAPTER 12 "16-BIT TIMER/COUNTER" This chapter describes the functions and operations of the 16-bit timer/counter. CHAPTER 13 "EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)" This chapter describes the functions and operations of external interrupt circuit 1 (edge). CHAPTER 14 "EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)" This chapter describes the functions and operations of external interrupt circuit 2 (level). CHAPTER 15 "A/D CONVERTER" This chapter describes the functions and operations of the A/D converter. CHAPTER 16 "UART/SIO" This chapter describes the functions and operations of the UART/SIO. CHAPTER 17 "HIGH-SPEED UART" This chapter describes the functions and operations of the high-speed UART. CHAPTER 18 "8-BIT SERIAL I/O" This chapter describes the functions and operations of the 8-bit serial I/O. CHAPTER 19 "I2C INTERFACE" This chapter describes the functions and operations of the I2C bus Interface. CHAPTER 20 "WILD REGISTER FUNCTION" This chapter describes the functions and operations of the wild register function. CHAPTER 21 "CLOCK OUTPUT" This chapter describes the functions and operations of the clock output function. CHAPTER 22 "FLASH MEMORY" This chapter describes the functions and operations of the flash memory. CHAPTER 23 "MB89F538/F538L SERIAL PROGRAMMING" This chapter describes an example of serial writing connection. APPENDIX This appendix lists the I/O map and instructions. ii * * * * * The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. (c)2002 FUJITSU LIMITED Printed in Japan iii HOW TO USE THIS MANUAL I Page Configuration of This Manual Each section of this manual has a summary below the title. This is to enable the reader to acquire an understanding of the outline of the product. The titles of the sections are also described in the subsections. This is to let the reader know what section of the manual he or she is consulting. I Example of Notations for the Register and Bit Names Example of the notations for the register and bit names By writing "1" in the sleep bit (STBC:SLP) of the standby control register, Register name Bit abbreviation Register abbreviation Bit name Disable (TBTC:TBIE = 0) the interrupt request output of the timebase timer. Setting data Bit abbreviation Register abbreviation If the interrupt enable (CCR:I = 1) is set, the interrupt is accepted. Current status Bit abbreviation Register abbreviation Example of the notation for the convertible pin P34/PT02 pin A convertible pin is available which can be used by switching its functions by program settings. The convertible pin is represented by separating the name of each function by "/". iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 OVERVIEW ................................................................................................... 1 Features of the MB89530/530H/530A Series ........................................................................................ 2 Available Models of the MB89530/530H/530A Series ........................................................................... 5 Differences among Models and the Precautions to Be Taken When Selecting Models ........................ 8 Block Diagram of the MB89530/530H/530A Series ............................................................................. 10 Pin Layout ............................................................................................................................................ 11 External Dimension Diagram ............................................................................................................... 14 Explanations of the Pin Functions ....................................................................................................... 21 I/O Circuit Format ................................................................................................................................ 26 CHAPTER 2 2.1 HANDLING DEVICE ................................................................................... 29 Notes on Handling Devices ................................................................................................................. 30 CHAPTER 3 CPU ............................................................................................................. 33 3.1 Memory Space ..................................................................................................................................... 34 3.1.1 Special Areas ................................................................................................................................. 36 3.1.2 Storing 16-bit Data in Memory ........................................................................................................ 38 3.2 Dedicated Registers ............................................................................................................................ 39 3.2.1 Condition Code Register (CCR) ..................................................................................................... 41 3.2.2 Register Bank Pointer (RP) ............................................................................................................ 44 3.3 General-purpose Registers .................................................................................................................. 45 3.4 Interrupts ............................................................................................................................................. 47 3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) ............................................................ 49 3.4.2 Interrupt Processing ....................................................................................................................... 51 3.4.3 Multiple Interrupts ........................................................................................................................... 53 3.4.4 Interrupt Processing Time .............................................................................................................. 54 3.4.5 Stack Operation during Interrupt Processing .................................................................................. 55 3.4.6 Stack Area for Interrupt Processing ................................................................................................ 56 3.5 Resets ................................................................................................................................................. 57 3.5.1 External Reset Pin .......................................................................................................................... 59 3.5.2 Reset Operation ............................................................................................................................. 60 3.5.3 Pin States during Reset .................................................................................................................. 62 3.6 Clock .................................................................................................................................................... 63 3.6.1 Clock Generator ............................................................................................................................. 65 3.6.2 Clock Controller .............................................................................................................................. 67 3.6.3 System Clock Control Register (SYCC) ......................................................................................... 69 3.6.4 Clock Modes ................................................................................................................................... 72 3.6.5 Oscillation Stabilization Wait Time ................................................................................................. 75 3.7 Standby Mode (Low Power Consumption) .......................................................................................... 77 3.7.1 Operating State in Standby Mode .................................................................................................. 78 3.7.2 Sleep Mode .................................................................................................................................... 79 3.7.3 Stop Mode ...................................................................................................................................... 80 3.7.4 Watch Mode ................................................................................................................................... 82 3.7.5 Standby Control Register (STBC) .................................................................................................. 83 v 3.7.6 State Transition Diagram 1 (Power-On Reset and Dual Clock System) ........................................ 3.7.7 State Transition Diagram 2 (Single Clock System Option) ............................................................ 3.7.8 Notes on Using Standby Mode ...................................................................................................... 3.8 Memory Access Mode ........................................................................................................................ 85 88 90 92 CHAPTER 4 I/O PORTS .................................................................................................. 95 4.1 Overview of the I/O Ports .................................................................................................................... 96 4.2 Port 0 and Port 1 ................................................................................................................................. 99 4.2.1 Registers of Port 0 and Port 1 (PDR0, DDR0, PURR0, PDR1, DDR1, PURR1) ......................... 101 4.2.2 Operation of Port 0 and Port 1 ..................................................................................................... 104 4.3 Port 2 ................................................................................................................................................ 106 4.3.1 Registers of Port 2 (PDR2, DDR2, PURR2) ................................................................................ 110 4.3.2 Operation of Port 2 ...................................................................................................................... 112 4.4 Port 3 ................................................................................................................................................ 114 4.4.1 Registers of Port 3 (PDR3, DDR3, PURR3) ................................................................................ 117 4.4.2 Operation of Port 3 ...................................................................................................................... 119 4.5 Port 4 ................................................................................................................................................ 121 4.5.1 Registers of Port 4 (PDR4, DDR4, PURR4, DDCR) .................................................................... 125 4.5.2 Operation of Port 4 ...................................................................................................................... 129 4.6 Port 5 ................................................................................................................................................ 131 4.6.1 Register of Port 5 (PDR5) ............................................................................................................ 133 4.6.2 Operation of Port 5 ...................................................................................................................... 134 4.7 Port 6 ................................................................................................................................................ 135 4.7.1 Register of Port 6 (PDR6, PURR6, DDCR) ................................................................................. 138 4.7.2 Operation of Port 6 ...................................................................................................................... 141 4.8 Sample I/O Port Program .................................................................................................................. 142 CHAPTER 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 TIMEBASE TIMER .................................................................................... 143 144 146 148 150 151 153 154 Overview of the Timebase Timer ...................................................................................................... Configuration of the Timebase Timer ................................................................................................ Timebase Timer Control Register (TBTC) ........................................................................................ Timebase Timer Interrupt .................................................................................................................. Operation of the Timebase Timer ..................................................................................................... Notes on Using the Timebase Timer ................................................................................................ Program Example of the Timebase Timer ........................................................................................ CHAPTER 6 6.1 6.2 6.3 6.4 6.5 6.6 WATCHDOG TIMER ................................................................................. 155 156 157 159 161 163 164 Overview of the Watchdog Timer ...................................................................................................... Configuration of the Watchdog Timer ............................................................................................... Watchdog Timer Control Register (WDTC) ...................................................................................... Operation of the Watchdog Timer ..................................................................................................... Notes on Using the Watchdog Timer ................................................................................................ Program Example of the Watchdog Timer ........................................................................................ CHAPTER 7 7.1 7.2 7.3 WATCH PRESCALER .............................................................................. 167 Overview of the Watch Prescaler ...................................................................................................... 168 Configuration of the Watch Prescaler ............................................................................................... 170 Watch Prescaler Control Register (WPCR) ...................................................................................... 172 vi 7.4 7.5 7.6 7.7 Watch Prescaler Interrupt .................................................................................................................. 174 Operation of the Watch Prescaler ...................................................................................................... 175 Notes on Using the Watch Prescaler ................................................................................................. 177 Program Example of the Watch Prescaler ......................................................................................... 178 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS ............................................................ 179 8.1 Overview of the 2-Channel 8-Bit PWM Timer (Interval Timer Function) ............................................ 180 8.2 Overview of the 2-Channel 8-Bit PWM Timer (PWM Timer Function) ............................................... 183 8.3 Configuration of the 2-Channel 8-Bit PWM Timer ............................................................................. 186 8.4 Pins of the 2-Channel 8-Bit PWM Timer ............................................................................................ 188 8.5 Registers of the 2-Channel 8-Bit PWM Timer .................................................................................... 190 8.5.1 PWM Control Register 1 (CNTR1) ............................................................................................... 191 8.5.2 PWM Control Register 2 (CNTR2) ............................................................................................... 193 8.5.3 PWM Control Register 3 (CNTR3) ............................................................................................... 195 8.5.4 PWM Compare Register 1 (COMR1) ........................................................................................... 197 8.5.5 PWM Compare Register 2 (COMR2) ........................................................................................... 199 8.6 2-Channel 8-Bit PWM Timer Interrupts .............................................................................................. 201 8.7 Interval Timer Function Operation ..................................................................................................... 202 8.8 Explanation of the 2-Channel 8-Bit PWM Timer Operation in 8-Bit PWM Mode ............................... 204 8.9 2-Channel 8-Bit PWM Timer Operation in 7-Bit PWM Mode ............................................................. 206 8.10 Explanation of the 2-Channel 8-Bit PWM Timer Operation in CH12PWM Mode .............................. 208 8.11 Explanation of the Prescaler Operation of 2-Channel 8-Bit PWM Timer ........................................... 210 8.12 State of the 2-Channel 8-Bit PWM Timer Operation in Each Mode ................................................... 212 8.13 Notes on Using the 2-Channel 8-Bit PWM Timer Usage ................................................................... 215 8.14 Program Examples of the 2-Channel 8-Bit PWM Timer (Interval Timer Function) ............................ 216 8.15 Program Examples of the 2-Channel 8-Bit PWM Timer (PWM Timer Function) ............................... 220 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) .................................................... 223 9.1 Overview of the Pulse Width Count Timer ......................................................................................... 224 9.2 Configuration of the Pulse Width Count Timer .................................................................................. 226 9.3 Pins of the Pulse Width Count Timer ................................................................................................. 228 9.4 Registers of the Pulse Width Count Timer ......................................................................................... 231 9.4.1 PWC Pulse Width Control Register 1 (PCR1) .............................................................................. 232 9.4.2 PWC Pulse Width Control Register 2 (PCR2) .............................................................................. 235 9.4.3 PWC Reload Buffer Register (RLBR) ........................................................................................... 237 9.5 Pulse Width Count Timer Interrupts ................................................................................................... 239 9.6 Operation of the Interval Timer Function ........................................................................................... 241 9.7 Operation of the Pulse Width Measurement Function ....................................................................... 244 9.8 Status of the Pulse Width Count Timer in Each Mode ....................................................................... 247 9.9 Notes on Using the Pulse Width Count Timer ................................................................................... 248 9.10 Program Examples for the Interval Timer Function of the Pulse Width Count Timer ........................ 250 9.11 Program Example for the Pulse Width Measurement Function of the Pulse Width Count Timer ...... 253 CHAPTER 10 6-BIT PPG TIMER ..................................................................................... 255 10.1 10.2 10.3 10.4 Overview of the 6-Bit PPG Timer ....................................................................................................... 256 Configuration of the 6-Bit PPG Timer Circuit ..................................................................................... 259 Pins of the 6-Bit PPG Timer ............................................................................................................... 261 Registers of the 6-Bit PPG Timer ...................................................................................................... 262 vii 10.4.1 6-Bit PPG Control Register 1 (RCR1) .......................................................................................... 10.4.2 6-Bit PPG Control Register 2 (RCR2) .......................................................................................... 10.5 Operation of the 6-Bit PPG Timer ..................................................................................................... 10.6 Notes on Using the 6-Bit PPG Timer ................................................................................................ 10.7 Program Example of the 6-Bit PPG Timer Programs ....................................................................... 263 264 265 266 268 CHAPTER 11 12-BIT PPG TIMER ................................................................................... 269 11.1 Overview of the 12-Bit PPG Timer .................................................................................................... 11.2 Configuration of the 12-Bit PPG Timer Circuit .................................................................................. 11.3 Pins of the 12-Bit PPG Timer ............................................................................................................ 11.4 Registers of the 12-Bit PPG Timer .................................................................................................... 11.4.1 12-Bit PPG Control Register 1 (PPGC1/PPGC2) ........................................................................ 11.4.2 12-Bit PPG Reload Register 1 (PRL11/PRL21) ........................................................................... 11.4.3 12-Bit PPG Reload Register 2 (PRL12/PRL22) ........................................................................... 11.4.4 12-Bit PPG Reload Register 3 (PRL13/PRL23) ........................................................................... 11.5 Operation of the 12-Bit PPG Timer ................................................................................................... 11.6 Notes on Using the 12-Bit PPG Timer .............................................................................................. 11.7 Program Example of the 12-Bit PPG Timer ...................................................................................... 270 273 275 277 278 279 280 281 282 283 285 CHAPTER 12 16-BIT TIMER/COUNTER ......................................................................... 287 12.1 Overview of the 16-bit Timer/Counter ............................................................................................... 12.2 Configuration of the 16-bit Timer/Counter ......................................................................................... 12.3 Pin of the 16-bit Timer/Counter ........................................................................................................ 12.4 Registers of the 16-bit Timer/Counter ............................................................................................... 12.4.1 Timer Control Register (TMCR) ................................................................................................... 12.4.2 16-bit Timer Count Register (TCR) .............................................................................................. 12.5 16-bit Timer/Counter Interrupts ......................................................................................................... 12.6 Operation of the Interval Timer Function .......................................................................................... 12.7 Operation of the Counter Function .................................................................................................... 12.8 Status of the 16-bit Timer/Counter in Each Mode ............................................................................. 12.9 Notes on Using the 16-bit Timer/Counter ......................................................................................... 12.10 Programe Example of the 16-bit Timer/Counter ............................................................................... 288 289 291 293 294 296 297 298 300 302 303 304 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) ......................................... 309 13.1 Overview of External Interrupt Circuit 1 ............................................................................................ 13.2 Configuration of the External Interrupt Circuit 1 ................................................................................ 13.3 Pins of the External Interrupt Circuit 1 .............................................................................................. 13.4 Registers of the External Interrupt Circuit 1 ...................................................................................... 13.4.1 External Interrupt Control Register 1 (EIC1) ................................................................................ 13.4.2 External Interrupt Control Register 2 (EIC2) ................................................................................ 13.5 External Interrupt Circuit 1 Interrupts ................................................................................................ 13.6 Operation of the External Interrupt Circuit 1 ..................................................................................... 13.7 Program Example of the External Interrupt Circuit 1 ........................................................................ 310 311 313 315 316 318 320 321 323 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) ........................................ 325 14.1 Overview of the External Interrupt Circuit 2 (Level) .......................................................................... 326 14.2 Configuration of the External Interrupt Circuit 2 ................................................................................ 327 14.3 Pins of the External Interrupt Circuit 2 .............................................................................................. 329 viii 14.4 Registers of the External Interrupt Circuit 2 ....................................................................................... 332 14.4.1 External Interrupt 2 Control Register (EIE2) ................................................................................. 333 14.4.2 External Interrupt 2 Flag Register (EIF2) ...................................................................................... 335 14.5 External Interrupt Circuit 2 Interrupts ................................................................................................. 336 14.6 Operation of the External Interrupt Circuit 2 ...................................................................................... 337 14.7 Program Example of the External Interrupt Circuit 2 ......................................................................... 339 CHAPTER 15 A/D CONVERTER ..................................................................................... 341 15.1 Overview of the A/D Converter .......................................................................................................... 342 15.2 Configuration of the A/D Converter .................................................................................................... 343 15.3 Pins of the A/D Converter .................................................................................................................. 346 15.4 Registers of the A/D Converter .......................................................................................................... 348 15.4.1 A/D Control Register 1 (ADC1) ..................................................................................................... 349 15.4.2 A/D Control Register 2 (ADC2) ..................................................................................................... 351 15.4.3 A/D Data Registers (ADDH, ADDL) .............................................................................................. 353 15.5 A/D Converter Interrupt ...................................................................................................................... 354 15.6 Operation of the A/D Converter ......................................................................................................... 355 15.7 Notes on Using the A/D Converter .................................................................................................... 357 15.8 Program Example of the A/D Converter ............................................................................................ 359 CHAPTER 16 UART/SIO .................................................................................................. 361 16.1 Overview of the UART/SIO .............................................................................................................. 362 16.2 Configuration of the UART/SIO ........................................................................................................ 363 16.3 Pins of the UART/SIO ........................................................................................................................ 365 16.4 Registers of the UART/SIO ................................................................................................................ 367 16.4.1 Serial Mode Control Register 1 (SMC21) ..................................................................................... 368 16.4.2 Serial Mode Control Register 2 (SMC22) ..................................................................................... 370 16.4.3 Serial Status/Data Register (SSD2) ............................................................................................. 372 16.4.4 Serial Input Data Register (SIDR2) .............................................................................................. 374 16.4.5 Serial Output Data Register (SODR2) .......................................................................................... 375 16.4.6 Baud Rate Generator Reload Register (SRC2) ............................................................................ 376 16.5 UART/SIO Interrupt .......................................................................................................................... 377 16.6 Operation of the UART/SIO .............................................................................................................. 378 16.7 Operation of the Operation Mode 0 ................................................................................................... 379 16.8 Operation of the Operation Mode 1 ................................................................................................... 384 CHAPTER 17 HIGH-SPEED UART ................................................................................. 389 17.1 Overview of the High-Speed UART ................................................................................................... 390 17.2 Configuration of the High-Speed UART ............................................................................................. 394 17.3 Pins of the High-Speed UART ........................................................................................................... 397 17.4 Registers of the High-Speed UART ................................................................................................... 399 17.4.1 Serial Mode Control Register 1 (SMC11) ..................................................................................... 400 17.4.2 Serial Mode Control Register 2 (SMC12) ..................................................................................... 402 17.4.3 Serial Rate Control Register (SRC1) ............................................................................................ 404 17.4.4 Serial Status/Data Register (SSD1) ............................................................................................. 406 17.4.5 Serial Input Data Register (SIDR1) .............................................................................................. 408 17.4.6 Serial Output Data Register (SODR1) .......................................................................................... 409 17.5 High-Speed UART Interrupts ............................................................................................................. 410 ix 17.6 17.7 17.8 17.9 Operation of the High-Speed UART ................................................................................................. Operation of Operation Modes 0, 1, 2, and 4 .................................................................................... Operation of Operation Mode 3 ........................................................................................................ Program Example of the UART ........................................................................................................ 411 412 415 417 CHAPTER 18 8-BIT SERIAL I/O ..................................................................................... 419 18.1 Overview of the 8-Bit Serial I/O ......................................................................................................... 18.2 Configuration of the 8-Bit Serial I/O .................................................................................................. 18.3 Pins of the 8-Bit Serial I/O ................................................................................................................. 18.4 Registers of the 8-Bit Serial I/O ........................................................................................................ 18.4.1 Serial Mode Register (SMR) ........................................................................................................ 18.4.2 Serial Data Register (SDR) .......................................................................................................... 18.5 8-Bit Serial I/O Interrupts .................................................................................................................. 18.6 Operation of the Serial Output .......................................................................................................... 18.7 Operation of the Serial Input ............................................................................................................. 18.8 States in Each Mode of 8-Bit Serial I/O Operation ............................................................................ 18.9 Notes on Using the 8-Bit Serial I/O ................................................................................................... 18.10 8-Bit Serial I/O Connection Example ................................................................................................ 18.11 Program Examples of the 8-Bit Serial I/O ......................................................................................... 420 421 423 427 428 430 431 432 434 436 439 440 442 CHAPTER 19 I2C INTERFACE ........................................................................................ 445 19.1 Overview of the I2C Interface ............................................................................................................ 19.2 Configuration of the I2C Interface ..................................................................................................... 19.3 Configuration of the I2C Bus Interface .............................................................................................. 19.4 Registers of the I2C Bus Interface .................................................................................................... 19.4.1 I2C Address Control Register (IACR) ........................................................................................... 19.4.2 I2C Bus Status Register (IBSR) ................................................................................................... 19.4.3 I2C Bus Control Register (IBCR) .................................................................................................. 19.4.4 I2C Clock Control Register (ICCR) ............................................................................................... 19.4.5 I2C Address Register (IADR) ....................................................................................................... 19.4.6 I2C Data Register (IDAR) ............................................................................................................. 19.5 I2C Interface Interrupts ..................................................................................................................... 19.6 Operation of the I2C Interface ........................................................................................................... 19.7 Notes on Using the I2C Bus Interface ............................................................................................... 19.8 I2C Bus Interface Flowcharts ............................................................................................................ 19.9 Program Example of the I2C Bus Interface ....................................................................................... 446 447 451 453 454 456 458 461 463 464 465 466 469 471 473 CHAPTER 20 WILD REGISTER FUNCTION .................................................................. 475 20.1 Overview of the Wild Register Function ............................................................................................ 20.2 Configuration of the Wild Register Function ..................................................................................... 20.3 Registers of the Wild Register Function ............................................................................................ 20.3.1 Data Setting Registers (WRDR1 to WRDR6) .............................................................................. 20.3.2 Upper Address Setting Registers (WRARH1 to WRARH6) ......................................................... 20.3.3 Lower Address Setting Registers (WRARL1 to WRARL6) .......................................................... 20.3.4 Wild Register Enable Register (WREN) ....................................................................................... 20.3.5 Wild Register Data Test Register (WROR) .................................................................................. 20.4 Operation of the Wild Register Function ........................................................................................... 20.5 General Hardware Connections ........................................................................................................ 476 477 478 479 481 483 485 487 488 490 x CHAPTER 21 CLOCK OUTPUT ...................................................................................... 491 21.1 Overview of Clock Output .................................................................................................................. 492 21.2 Clock Output Components ................................................................................................................. 493 21.3 Clock Output Pins .............................................................................................................................. 494 21.4 Registers for Clock Output ................................................................................................................. 495 21.4.1 Clock Output Control Register (CKR) ........................................................................................... 496 21.5 Description of Clock Output Operation .............................................................................................. 497 21.6 Notes on Use of Clock Output ........................................................................................................... 498 21.7 Sample Clock Output Program .......................................................................................................... 499 CHAPTER 22 FLASH MEMORY ...................................................................................... 501 22.1 Outline of Flash Memory ................................................................................................................... 502 22.2 Sector Configuration of the Flash Memory ........................................................................................ 503 22.3 Flash Memory Control Status Register (FMCS) ................................................................................ 504 22.4 Starting the Flash Memory Automatic Algorithm ............................................................................... 506 22.5 Confirming the Automatic Algorithm Execution State ........................................................................ 507 22.5.1 Data Polling Flag (DQ7) ............................................................................................................... 509 22.5.2 Toggle Bit Flag (DQ6) ................................................................................................................... 510 22.5.3 Timing Limit Exceeded Flag (DQ5) .............................................................................................. 511 22.5.4 Sector Erase Timer Flag (DQ3) .................................................................................................... 512 22.5.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................... 513 22.6 Detailed Explanation of Writing to and Erasing Flash Memory .......................................................... 514 22.6.1 Setting The Read/Reset State ...................................................................................................... 515 22.6.2 Writing Data .................................................................................................................................. 516 22.6.3 Erasing All Data (Erasing Chips) .................................................................................................. 518 22.6.4 Erasing Data (Erasing Sectors) .................................................................................................... 519 22.6.5 Suspending Sector Erase ............................................................................................................. 521 22.6.6 Restarting Sector Erase ............................................................................................................... 522 22.7 Notes on using Flash Memory ........................................................................................................... 523 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING .......................................... 525 23.1 Basic Configuration of MB89F538/F538L Serial Programming Connection ...................................... 526 23.2 Connection Example of Serial Programming (when User Power Supply is Used) ........................... 529 23.3 Connection Example of Serial Programming (when Power Supply is Supplied from Flash MCU Programmer) ...................................................................................................................................... 531 23.4 Minimum Connection Example with Flash MCU Programmer (when User Power Supply is Used) .. 533 23.5 Minimum Connection Example with Flash Microcomputer Programmer (when Power Supply is Supplied from Flash MCU Programmer) .......................................................................................................... 535 APPENDIX .......................................................................................................................... 537 APPENDIX A I/O Maps ............................................................................................................................... 538 APPENDIX B Overview of Instructions ........................................................................................................ 542 B.1 Overview of F2MC-8L Instructions .................................................................................................. 543 B.2 Addressing ...................................................................................................................................... 545 B.3 Special Instructions ......................................................................................................................... 549 B.4 Bit Manipulation Instructions (SETB, CLRB) ................................................................................... 552 B.5 F2MC-8L Instructions ...................................................................................................................... 553 B.6 Instruction Map ................................................................................................................................ 559 xi APPENDIX C Mask Options ....................................................................................................................... APPENDIX D Write Specifications for the One-Time PROM and EPROM Microcomputer ........................ APPENDIX E EPROM with Piggyback/Evaluation Chip ............................................................................. APPENDIX F Pin Statuses of the MB89530/530H/530A Series ................................................................ APPENDIX G Troubleshooting ................................................................................................................... 560 561 563 564 566 INDEX ...................................................................................................................................569 xii CHAPTER 1 OVERVIEW This chapter describes the features and basic specifications of the MB89530/530H/ 530A series of microcontrollers. 1.1 "Features of the MB89530/530H/530A Series" 1.2 "Available Models of the MB89530/530H/530A Series" 1.3 "Differences among Models and the Precautions to Be Taken When Selecting Models" 1.4 "Block Diagram of the MB89530/530H/530A Series" 1.5 "Pin Layout" 1.6 "External Dimension Diagram" 1.7 "Explanations of the Pin Functions" 1.8 "I/O Circuit Format" 1 CHAPTER 1 OVERVIEW 1.1 Features of the MB89530/530H/530A Series The MB89530/530H/530A series is a one-chip microcontroller that uses the F2MC(R)-8L core to support the low voltage and high-speed operation. The internal peripheral functions include the timers, serial interfaces, A/D converter, external interrupts, and so on. This series is a general-purpose one-chip microcontroller that is suitable for a broad range of uses, from consumer products to industrial equipment as well as for portable devices. I Features of the MB89530/530H/530A series Full package development * * * Two types of QFP packages (1-mm pitch, 0.65-mm pitch) LQFP package (0.5-mm pitch) SH-DIP package High-speed operation with low voltage * Minimum instruction execution time 0.32 s (for oscillation 12.5 MHz) F2MC(R)-8L CPU core Optimal instruction system for the controller * * * * Multiplication and division instructions 16-bit arithmetic operations Branch instructions with bit test Bit manipulation instructions Five-system timer * * * * * 8-bit PWM timer: 2-channel timer (can be used as the interval timer or PWM timer) Pulse-width count timer (supports the usages such as continuous measurement and remote control reception) 16-bit timer counter 21-bit timebase timer Watch prescaler (17 bits) UART * Clock synchronization and asynchronization can be switched. 2 1.1 Features of the MB89530/530H/530A Series Two serial interfaces (serial I/O) * Transfer direction can be selected (specification of MSB first or LSB first), enabling communication with a variety of devices. 10-bit A/D converter (8 channels) * The start of the A/D converter is supported with external clock input and timebase timer output. (The A/D converter cannot be started with external clock input for MB89F538/ F538L.) Two programmable pulse generators (PPGs) * * 6-bit PPG that enables a pulse width and cycle to be selected with a program 12-bit PPG that enables a pulse width and cycle to be selected with a program (2 channels) I2C interface circuit External interrupt 1 (single-clock system product: 4 channels, dual-clock system product: 3 channels) * Four or three inputs are independent, enabling releases from standby mode. (With the edge detection function) External interrupt 2 (product other than MB89F538/F538L: 8 channels, MB89F538/F538L: 7 channels) * Eight or seven inputs are independent, enabling releases from standby mode. (With the level edge detection function) Standby mode (low-power consumption mode) * * * * Stop mode (current consumption hardly takes place because oscillation stops) Sleep mode (current consumption becomes about 1/3 of the usual amount because the CPU stops) Subclock mode Watch mode Watchdog timer reset I/O ports * Maximum number of ports Single-clock system product Other than MB89F538/F538L: 53 ports MB89F538/F538L: 52 ports Dual-clock system product Other than MB89F538/F538L: 51 ports MB89F538/F538L: 50 ports 3 CHAPTER 1 OVERVIEW * General-purpose I/O port (CMOS) Other than MB89F538/F538L: 38 ports MB89F538/F538L: 37 ports * * * General-purpose I/O port (N-channel open drain): 2 ports General-purpose output port (N-channel open drain): 8 ports General-purpose input port (CMOS) Single-clock system product: 5 ports Dual-clock system product: 3 ports 4 1.2 Available Models of the MB89530/530H/530A Series 1.2 Available Models of the MB89530/530H/530A Series Four models of the MB89530/530H/530A series are supported. Table 1.2-1 "Available models of the MB89530/530H/530A series" lists the available models and Table 1.2-2 "CPU and peripheral functions of the MB89530/530H/530A series" lists the CPU and peripheral functions. I Available models of the MB89530/530H/530A series Table 1.2-1 Available models of the MB89530/530H/530A series Model Item MB89535A MB89537/537C MB89537H/537HC MB89537A/537AC MB89538/538C MB89538H/538HC MB89538A/538AC MB89F538/F538L MB89P538 MB89PV530 Classification ROM capacity RAM capacity Mass production (mask ROM product) 16 KB x 8 bits (Internal ROM) 32 KB x 8 bits (Internal ROM) 48 KB x 8 bits (Internal ROM) Flash Memory 48 KB x 8 bits (Internal flash memory) PROM 48 KB x 8 bits (Internal PROM) EVA 48 KB x 8 bits (External ROM) (*2) 512 x 8 bits 1 KB x 8 bits 2 KB x 8 bits MB89F538: 3.5V to 5.5V(*1) MB89F538L: 2.4V to 3.6V(*1)(*3) 2.7V to 3.6V(*1)(*4) Operating voltage 2.2V to 3.6V(*1) (MB89537/538/537C/538C) 3.5V to 5.5V(*1) (MB89537H/538H/537HC/538HC) 2.2V to 5.5V(*1) (MB89535A/537A/538A/537AC/538AC) 2.7V to 5.5V *1 Depends on the operating frequency. *2 MBM27C512 is used as the external ROM. *3 Flash memory read assurance voltage. *4 Flash memory read/write assurance voltage. Note: MB89537/538/537H/538H/535A/537A/538A contain no I2C function. To use the I2C function, use MB89PV530/MB89P538/MB89F538/MB89F538L/MB89537C/538C/537HC/ 538HC/537AC/538AC. 5 CHAPTER 1 OVERVIEW Table 1.2-2 CPU and peripheral functions of the MB89530/530H/530A series Item Specifications Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Minimum interrupt processing time Input port * * Single-clock system product Dual-clock system product : 5 ports (Four ports also serve as external interrupts.) : 3 ports (Three ports also serve as external interrupts.) : 8 ports (Eight ports are also used as ADC input.) : 2 ports (Two ports also serve as S02/ SDA and SI2/SCL.) : 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 0.32 s/12.5 MHz : 2.88 s/12.5 MHz CPU function Output-dedicated port (N-channel) I/O port (N-channel open drain) Port I/O port (CMOS) * * Peripheral function Other than MB89F538/F538L MB89F538/F538L : 38 pins : 37 pins (Twenty-one ports do not serve as other functions.) Total * * Single-clock system product Dual-clock system product Other than MB89F538/F538L: 53 ports MB89F538/F538L: 52 ports Other than MB89F538/F538L: 51 ports MB89F538/F538L: 50 ports Timebase timer Watchdog timer 21 bits Interrupt cycle for main clock original oscillation 12.5 MHz (approx. 0.655 ms, 2.621 ms, 20.97 ms, and 335.5 ms) Reset cycle for main clock original oscillation 12.5 MHz (approx. 167.8 to 335.6 ms) Reset cycle for subclock original oscillation 32.768 KHz (approx. 500 to 1,000 ms) 8-bit interval timer operation (Rectangular output supported, operating clock cycle: 1tinst, 8tinst, 16tinst, and 64tinst) 8-bit resolution pulse width measurement (conversion cycle: 28tinst to 28 x 64tinst) 2 channels (also usable as the interval timer), usable as the channel 1 output and channel 2 count clock. Interval time for 17-bit subclock original oscillation 32.768 KHz (Approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, and 4.00 s) PWM timer Watch prescaler 6 1.2 Available Models of the MB89530/530H/530A Series Table 1.2-2 CPU and peripheral functions of the MB89530/530H/530A series (Continued) Item Specifications 8-bit one-shot timer operation (Underflow output supported, operating clock cycle: 1tinst, 4tinst, 32tinst, and external) 8-bit reload timer operation (rectangular output supported, operating clock cycle: 1tinst, 4tinst, 32tinst, and external) 8-bit pulse width measurement operation (the following measurements are possible: continuous measurement, H width measurement, L width measurement, measurement from to , measurement from to , and both H width measurement and measurement from to ) 16-bit timer operation (operating clock cycle: 1tinst, and external) 16-bit event counter operation (rising edge, falling edge, or both selectable) 16 bits x 1 channel 8-bit length LSB or MSB precedence selectable Transfer clock (2tinst, 8tinst, 32tinst, and external) CLK synchronization/CLK asynchronization data transferable (bits 8 and 9 with parity bits, bits 7 and 8 without parity bits) 14 baud rates can be selected with the internal baud rate generator. CLK synchronization/CLK asynchronization data transferable (bits 4, 6, 7, and 8 with parity bits, bits 5, 7, 8, and 9 without parity bits) 14 baud rates can be selected with the internal baud rate generator. Baud rates can also be set with external clock input and 2-channel 8-bit PWM timer output. Single-clock system product: independent 4 channels, dual-clock system product: independent 3 channels Rising edge, falling edge, or both can be selected. Usable for release from standby mode (edge detection can also be used in stop mode). Other than MB89F538/F538L: independent 8 channel L level detection, MB89F538/F538L: independent 7 channel L level detection Usable for release from standby mode. Rectangular waves whose cycle is programmable can be generated. 6 bits x 1 channel and 12 bits x 2 channels 1 channel, conforms to the system management bus revised edition 1.0 of the Intel Corporation and to the I2C specifications of Philips Electronics. 2-wire system communication (contained only in the following: MB89PV530/P538/ F538/F538L/537C/538C/537HC/538HC/537AC/538AC) 10-bit resolution x 8 channels A/D conversion function (conversion time: 60tinst) Repeated start is supported with external or internal clocks (MB89F538/ MB89F538L is excluded from repeated start with external clocks.) Reference voltage input available (AVR) Sleep mode, stop mode, subclock mode, and watch mode CMOS Pulse width count timer 16-bit timer/ counter Serial I/O UART/SIO Peripheral functions UART External interrupt 1 External interrupt 2 6-bit PPG, 12-bit PPG I2C bus interface A/D converter Standby mode (low-power mode) Process tinst: Instruction cycle (execution time). 1/4, 1/8, 1/16, or 1/64 of the main clock or 1/2 of the subclock can be selected (see Section 3.6 "Clock"). 7 CHAPTER 1 OVERVIEW 1.3 Differences among Models and the Precautions to Be Taken When Selecting Models This section describes the differences among five models of the MB89530/530H/530A series and the precautions to be taken when selecting models. I Differences among models and precautions to be taken when selecting models Table 1.3-1 Packages of the supported models Model Package MB89535A DIP-64P-M01 FPT-64P-M03 FPT-64P-M06 FPT-64P-M09 MDP-64C-P02 MQP-64C-P01 o o o o x x MB89537/537C MB89537H/537HC MB89537A/537AC o o o o x x MB89538/538C MB89538H/538HC MB89538A/538AC o o o o x x MB89P538 MB89F538 MB89F538L o x o o x x MB89PV530 x x x x o o [o]: Usable [x]: Unusable The conversion socket (manufactured by Sunhayato Corporation) can be used to convert a pin pitch. Where to make contact: Sunhayato Corporation Tel. 03-3986-0403 Memory space To use a piggyback model for evaluation, carefully confirm the differences between this model and the model to be actually used. Pay special attention to the following points. (See Section 3.1 "Memory Space.") * * The program ROM area begins from 4000H on MB89P538, MB89F538, MB89F538L, and MB89PV530. The stack area is set in the upper limit of the RAM Current consumption * * For MB89PV530, the current consumed by EPROM connected to the top socket is added. During low-speed operation, the current consumption of the model mounted on the one-time PROM or the EPROM is greater than that of the model mounted on the mask ROM. However, the current consumption in sleep or stop mode is equal for both cases. For details, see the electrical characteristics of the data sheet. 8 1.3 Differences among Models and the Precautions to Be Taken When Selecting Models Mask option The functions that can be specified with options and the method of specifying the options depend on the model. Before using the options, first refer to Appendix C "Mask Options" for details. Wild register function Table 1.3-2 "Spaces in which the wild register function can be used" lists the spaces in which the wild register function can be used. Table 1.3-2 Spaces in which the wild register function can be used Model name MB89PV530 MB89P538/F538/F538L MB89537/537C/537H/537HC/537A/537AC MB89538/538C/538H/538HC/538A/538AC MB89535A Address space 4000H to FFFFH 4000H to FFFFH 8000H to FFFFH 4000H to FFFFH C000H to FFFFH 9 CHAPTER 1 OVERVIEW 1.4 Block Diagram of the MB89530/530H/530A Series Figure 1.4-1 "Entire block diagram of the MB89530/530H/530A series" shows the block diagram of the MB89530/530H/530A series. I Entire block diagram of the MB89530/530H/530A series Figure 1.4-1 Entire block diagram of the MB89530/530H/530A series Subclock P63/INT13/X0A*1 P64/X1A*1 Low-power oscillation circuit (32.768kHz) Clock control P60/INT10 to P62/INT12 Port 6 4 Port 1 8 P10 to P17 Watch prescaler External interrupt 1 (Edge) CMOS I/O port 12-bit PPG02 X0 X1 Main clock Oscillation circuit Port 0 CMOS I/O port 8 P00 to P07 CMOS I/O port Port 2 12-bit PPG01 P20/PWCK P21/PPG01 P22/PPG02 P23 to P27 CMOS I/O port Clock control RST Reset circuit (Watchdog timer) 21-bit timebase timer Internal data bus SIO UART I2C 16-bit timer/counter 1 External interrupt 2 (level) P40/INT20/EC P41/INT21/SCK2 N-channel I/O P42/INT22/ SO2/SDA P43/INT23/ SI2/SCL P44/INT24/UCK2 P30/PPG03/MCO P31/SCK1(UCK) /LMCO P32/SO1(U01) Port 3 P33/SI1(UI1) P34/PT02 P35/PWC P36/WTO P37/PTO1 6-bit PPG03 8-bit PWM timer 2 Port 4 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST*2 8-bit PWM timer 1 UART/SIO PWC CMOS I/O port N-channel output Port 5 CMOS I/O port 1-KB RAM/2-KB RAM F2MC-8L CPU 10-bit A/D converter 8 8 P50/AN0 to P57/AN7 AVcc AVR AVss Wild register *1 For the single-clock system product, P63, INT13 and P64 pins are used. For the dual-clock system product, X0A and X1A pins are used. *2 The P47, INT27, and ADST pins become the MOD2 pin for MB89F538/F538L. 32-KB ROM/48-KB ROM Other pins MOD0,MOD1,MOD2*2,Vcc,Vss,C/NC 10 1.5 Pin Layout 1.5 Pin Layout Figure 1.5-1 "Pin layout for DIP-64P-M01 and MDP-64C-P02", Figure 1.5-2 "Pin layout for FPT-64P-M03 and FPT-64P-M09", and Figure 1.5-3 "Pin layout diagram for FPT-64PM06 and MQP-64C-P01" show the pin layouts of the MB89530/530H/530A series. I Pin layout for DIP-64P-M01 and MDP-64C-P02 Figure 1.5-1 Pin layout for DIP-64P-M01 and MDP-64C-P02 (Top view) P36/WTO P37/PTO1 P40/INT20/EC P41/INT21/SCK2 P42/INT22/SO2/SDA P43/INT23/SI2/SCL P44/INT24/UCK2 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST,MOD2*1 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT10 P61/INT11 P62/INT12 P63/INT13/XOA*2 P64/X1A*2 RST MOD0 MOD1 X0 X1 VSS 1 2 65 A15 92 VCC 3 66 A12 91 A14 4 67 A7 90 A13 5 68 A6 89 A8 6 69 A5 88 A9 7 70 A4 87 A11 8 71 A3 86 OE 9 72 A2 85 A10 10 73 A1 84 CE 11 74 A0 83 O8 12 75 O1 82 O7 13 76 O2 81 O6 14 77 O3 80 O5 15 78 VSS 79 O4 16 17 18 19 The dotted area is dedicated to MB89PV530. 20 21 22 23 24 25 26 27 28 29 30 31 32 (DIP-64P-M01) (MDP-64C-P02) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vcc P35/PWC P34/PTO2 P33/SI1(UI1) P32/SO1(UO1) P31/SCK1(UCK1)/LMCO P30/PPG03/MCO C/NC*3 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20/PWCK P21/PPG01 P22/PPG02 P23 P24 P25 P26 P27 *1 Pin 10 is the MOD2 pin for MB89F538/F538L and pin 10 is the P47, INT27, and ADST pins for a product other than MB89F538/538L. *2 Pins 25 and 26 are P63, INT13, and P64 pins for the single-clock system product. Pins 25 and 26 are X0A and X1A pins for the dual-clock system product. *3 The pin function of pin 57 depends on the model. For details, see Chapter 2, "Handling Device." 11 CHAPTER 1 OVERVIEW I Pin layout for FPT-64P-M03 and FPT-64P-M09 Figure 1.5-2 Pin layout for FPT-64P-M03 and FPT-64P-M09 P45/INT25/UO2 P44/INT24/UCK2 P43/INT23/SI2/SCL P42/INT22/SO2/SDA P41/INT21/SCK2 P40/INT20/EC P37/PT01 P36/WTO VCC P35/PWC P34/PT02 P33/SI1(UI1) P32/SO1(UO1) P31/SCK1(UCK1)/LMCO P30/PPG03/MCO C/NC*3 P46/INT26/UI2 P47/INT27/ADST/MOD2*1 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVcc AVR AVss P60/INT10 P61/INT11 P62/INT12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 (Top view) P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 *1 Pin 2 is the MOD2 pin for MB89F538/F538L. Pin 2 is the P47, INT27, and ADST pins for a product other than MB89F538/538L. *2 Pins 17 and 18 are P63, INT13, and P64 pins for the single-clock system product. Pins 17 and 18 are X0A and X1A pins for the dual-clock system product. *3 The pin function of pin 49 depends on the model. For details, see Chapter 2, "Handling Device." 12 P63/INT13/X0A*2 P64/X1A*2 RST MOD0 MOD1 X0 X1 Vss P27 P26 P25 P24 P23 P22/PPG02 P21/PPG01 P20/PWCK (FPT-64P-M03) (FPT-64P-M09) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1.5 Pin Layout I Pin layout for FPT-64P-M06 and MQP-64C-P01 Figure 1.5-3 Pin layout diagram for FPT-64P-M06 and MQP-64C-P01 P44/INT24/UCK2 P43/INT23/SI2/SCL P42/INT22/SO2/SDA P41/INT21/SCK2 P40/INT20/EC P37/PT01 P36/WTO VCC P35/PWC P34/PT02 P33/SI1(UI1) P32/SO1/(U01) P31/SCK1(UCK1)/LMCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST/MOD2*1 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVcc AVR AVss P60/INT10 P61/INT11 P62/INT12 P63/INT13/X0A*2 P64/X1A*2 *4 85 86 87 88 89 90 91 92 93 (Top view) 77 76 75 74 73 72 71 70 69 P30/PPG03/MCO C/NC*3 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20/PWCK *1 Pin 3 is the MOD2 pin for MB89F538/F538L. Pin 3 is the P47, INT27, and ADST pins for a product other than MB89F538/538L. *2 Pins 18 and 19 are P63, INT13, and P64 pins for the single-clock system product. Pins 18 and 19 are the X0A and X1A pins for the dual-clock system product. *3 The pin function of pin 50 depends on the model. For details, see Chapter 2, "Handling Device." *4 Pin layout (dedicated to MB89PV530) in the upper part of the package Pin number Pin symbol Pin number Pin symbol Pin number Pin symbol Pin number Pin symbol 65 81 89 N.C. N.C. 73 OE A2 66 82 90 A15 04 74 N.C. A1 67 83 91 A12 05 75 A11 A0 68 84 92 A7 06 76 A9 N.C. 69 85 93 A6 07 77 A8 01 70 86 94 A5 08 78 A13 02 71 87 95 A4 CE 79 A14 03 72 88 96 A3 A10 80 VCC VSS N.C.: This pin is unusable because it is used for internal connection. RST MOD0 MOD1 X0 X1 Vss P27 P26 P25 P24 P23 P22/PPG02 P21/PPG01 (FPT-64P-M06) (MQP-64C-P01) 20 21 22 23 24 25 26 27 28 29 30 31 32 94 95 96 65 66 67 68 84 83 82 81 80 79 78 13 CHAPTER 1 OVERVIEW 1.6 External Dimension Diagram Six packages are provided for the MB89530/530H/530A series. Figure 1.6-1 "External dimensions for DIP-64P-M01" to Figure 1.6-6 "External dimensions for MQP-64C-P01" show their external dimensions. 14 1.6 External Dimension Diagram I External dimensions for DIP-64P-M01 Figure 1.6-1 External dimensions for DIP-64P-M01 Plastic SH-DIP 64 pins Lead pitch Package width x package length Packaging method Mounting height 1.778mm 17 x 58 mm Plastic mold 5.65 mm MAX (DIP-64P-M01) Plastic SH-DIP 64 pins (DIP-64P-M01) 58.00 -0.55 2.283 -.022 +0.22 +.009 Note: The pin width and pin thickness include the plating thickness. INDEX-1 17.000.25 (.669.010) INDEX-2 4.95 -0.20 .195 -.008 +0.70 +.028 0.70 -0.19 .028 -.007 +0.50 +.020 3.30 -0.30 .130 +0.20 +.008 -.012 +0.40 -0.20 +.016 -.008 0.270.10 (.011.004) 1.378 .0543 1.778(.0700) 0.470.10 (.019.004) 0.25(.010) M 19.05(.750) 0~15 1.00 -0 +0.50 +.020 .039 -.0 C 2001 FUJITSU LIMITED D64001S-c-4-5 Unit: mm (inches) 15 CHAPTER 1 OVERVIEW I External dimensions for FPT-64P-M03 Figure 1.6-2 External dimensions for FPT-64P-M03 Plastic LQFP 64 pins Lead pitch Package width x package length Lead shape Packaging method Mounting height Weight 0.50 mm 10.0 x 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32g (FPT-64P-M03) Plastic LQFP 64 pins (FPT-64P-M03) Note: The pin width and pin thickness include the plating thickness. 12.000.20(.472.008)SQ 10.000.10(.394.004)SQ 48 33 0.1450.055 (.006.002) 49 32 Details of "A" part 0.08(.003) 1.50 -0.10 .059 -.004 +0.20 +.008 (Mounting height) INDEX 64 17 0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) 0.25(.010) LEAD No. 1 16 0.50(.020) 0.200.05 (.008.002) 0.08(.003) M C 2000 FUJITSU LIMITED F64009S-c-4-7 Unit: mm (inches) 16 1.6 External Dimension Diagram I External dimensions for FPT-64P-M06 Figure 1.6-3 External dimensions for FPT-64P-M06 Plastic QFP 64 pins Lead pitch Package width x package length Lead shape Packaging method Mounting height 1.00 mm 14 x 20 mm Gullwing Plastic mold 3.35 mm MAX (FPT-64P-M06) Plastic QFP 64 pins (FPT-64P-M06) 24.700.40(.972.016) 20.000.20(.787.008) 51 33 Note: The pin width and pin thickness include the plating thickness. 0.170.06 (.007.002) 52 32 18.700.40 (.736.016) 14.000.20 (.551.008) INDEX Details of "A" part 3.00 -0.20 .118 -.008 20 +0.35 +.014 (Mounting height) 64 0~8 1 19 1.00(.039) 0.420.08 (.017.003) 0.20(.008) M 0.25 -0.20 1.200.20 (.047.008) +0.15 +.006 .010 -.008 (Stand off) "A" 0.10(.004) C 2001 FUJITSU LIMITED F64013S-c-4-4 Unit: mm (inches) 17 CHAPTER 1 OVERVIEW I External dimensions for FPT-64P-M09 Figure 1.6-4 External dimensions for FPT-64P-M09 Plastic LQFP 64 pins Lead pitch Package width x package length Lead shape Packaging method Mounting height 0.65 mm 12 x 12 mm Gullwing Plastic mold 1.70 mm MAX (FPT-64P-M09) Plastic LQFP 64 pins (FPT-64P-M09) Note: The pin width and pin thickness include the plating thickness. 14.000.20(.551.008)SQ 12.000.10(.472.004)SQ 48 33 0.1450.055 (.0057.0022) 49 32 0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004 +0.20 +.008 (Mounting height) 0.25(.010) INDEX 0~8 64 17 1 16 "A" 0.65(.026) 0.320.05 (.013.002) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) 0.13(.005) M C 2001 FUJITSU LIMITED F64018S-c-2-4 Unit: mm (inches) 18 1.6 External Dimension Diagram I External dimensions for MDP-64C-P02 Figure 1.6-5 External dimensions for MDP-64C-P02 Ceramic MDIP 64 pins Lead pitch Row spacing Mother board material Connection socket material 70 mil 750 mil Ceramic Plastic (MDP-64C-P02) Ceramic MDIP 64 pins (MDP-64C-P02) 56.900.64 (2.240.025) 0~9 15.24(.600) TYP 18.750.30 (.738.012) 19.050.30 (.750.012) INDEX AREA 2.540.25 (.100.010) 33.02(1.300)REF 0.250.05 (.010.002) 10.16(.400)MAX 1.270.25 (.050.010) 1.7780.25 (.070.010) 0.46 -0.08 +.005 .018 -.003 55.12(2.170)REF +0.13 0.900.13 (.035.005) 3.430.38 (.135.015) C 1994 FUJITSU LIMITED M64002SC-1-4 Unit: mm (inches) 19 CHAPTER 1 OVERVIEW I External dimensions for MQP-64C-P01 Figure 1.6-6 External dimensions for MQP-64C-P01 Ceramic MQFP 64 pins Lead pitch Lead shape Motherboard material Material of the socket mounted 1.00 mm Straight Ceramic Plastic (MQP-64C-P01) Ceramic MQFP 64 pins (MQP-64C-P01) 18.70(.736)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 12.00(.472)TYP +0.40 +.016 -.008 INDEX AREA 1.20 -0.20 .047 1.000.25 (.039.010) 1.000.25 (.039.010) 1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.00(.709) TYP 1.270.13 (.050.005) 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.400.10 (.016.004) 0.400.10 (.016.004) 1.20 -0.20 .047 -.008 +0.40 +.016 0.50(.020)TYP 10.82(.426) 0.150.05 MAX (.006.002) C 1994 FUJITSU LIMITED M64004SC-1-3 Unit: mm (inches) 20 1.7 Explanations of the Pin Functions 1.7 Explanations of the Pin Functions Table 1.7-1 "Explanations of the pin functions" and Table 1.7-2 "Explanation of the external EPROM socket pin functions (MB89PV530 only)" list the I/O pins and their functions of the MB89530/530H/530A series. The alphabetic characters in the I/O circuit format column in Table 1.7-1 "Explanations of the pin functions" correspond to those in the classification column in Table 1.8-1 "I/O circuit format." I Explanations of the pin functions Table 1.7-1 Explanations of the pin functions Pin number SH-DIP(*1) MDIP(*2) 30 31 28 29 QFP(*3) MQFP(*4) 23 24 21 22 LQFP(*5) QFP(*6) 22 23 20 21 X0 A X1 MOD0 B MOD1 Pin name I/O circuit format Explanation of functions Connection pin for the crystal oscillation circuit or other oscillation circuits An external clock can be connected to X0. In this case, X1 must be opened. Input pin for setting the memory access Connected directly to VSS. Reset I/O pin. This pin is used as the CMOS input/output and hysteresis input with pull-up resistor. "L" is output from the pin in accordance with an internal reset request. The internal circuit is initialized with input of the "L" level. General-purpose I/O port General-purpose I/O port General-purpose I/O port Resource I/O pin (input: hysteresis) Hysteresis input. This pin is also used as the PWC input. General-purpose I/O port This pin is also used as the PPG01 output. General-purpose I/O port This pin is also used as the PPG02 output. General-purpose I/O port General-purpose I/O port General-purpose I/O port 27 20 19 RST C 56 to 49 48 to 41 49 to 42 41 to 34 48 to 41 40 to 33 P00 to P07 P10 to P17 D D 40 33 32 P20/PWCK E 39 38 37 36 35 32 31 30 29 28 31 30 29 29 27 P21/ PPG01 P22/ PPG02 P23 P24 P25 D D D D D 21 CHAPTER 1 OVERVIEW Table 1.7-1 Explanations of the pin functions (Continued) Pin number SH-DIP(*1) MDIP(*2) 34 33 58 QFP(*3) MQFP(*4) 27 26 51 LQFP(*5) QFP(*6) 26 25 50 P26 P27 P30/ PPG03/ MCO P31/SCK1 (UCK1)/ LMCO P32/ SO1(UO1) Pin name I/O circuit format D D D Explanation of functions General-purpose I/O port General-purpose I/O port General-purpose I/O port This pin is also used as the PPG03 output. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the UART/SIO clock I/ O. General-purpose I/O port This pin is also used as the UART/SIO serial data output. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the UART/SIO serial data input. General-purpose I/O port This pin is also used as the PWM timer 2 output. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the PWC input. General-purpose I/O port The resource is output. This pin is also used as the PWC output. General-purpose I/O port The resource is output. This pin is also used as the PWM timer 1 output. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input and 16-bit timer/counter input. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input and SIO clock I/O. N-channel open-drain output Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input, SIO serial data output, and I2C data line. 59 52 51 E 60 53 52 D 61 54 53 P33/ SI1(UI1) E 62 55 54 P34/PTO2 D 63 56 55 P35/PWC E 1 58 57 P36/WTO D 2 59 58 P37/PTO1 D 3 60 59 P40/ INT20/EC E 4 61 60 P41/ INT21/ SCK2 P42/ INT22/ SO2/SDA E 5 62 61 G 22 1.7 Explanations of the Pin Functions Table 1.7-1 Explanations of the pin functions (Continued) Pin number SH-DIP(*1) MDIP(*2) QFP(*3) MQFP(*4) LQFP(*5) QFP(*6) P43/ INT23/S12/ SCL P44/ INT24/ UCK2 Pin name I/O circuit format Explanation of functions 6 63 62 G N-channel open-drain output Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input, SIO serial data input, and I2C clock I/O. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input and UART clock I/O. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input and UART data output. General-purpose I/O port External interrupt I/O pin (input: hysteresis) This pin is also used as the external interrupt input and UART data input. MB89F538/ MB89F538L Input pin for setting memory access mode Connected directly to VSS. General-purpose I/O port Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input and A/D converter clock input pin. 7 64 63 E 8 1 64 P45/ INT25/UO2 E 9 2 1 P46/ INT26/UI2 E MOD2 B Other than above 10 3 2 P47/ INT27/ ADST E 11 to 18 4 to 11 3 to 10 P50/AN0 to P57/AN7 P60/INT10 to P62/INT12 H N-channel open-drain output port This pin is also used as the A/D converter analog input. General-purpose input port Resource I/O pin (input: hysteresis) This pin is also used as the external interrupt input. General-purpose input port Resource I/O pin (input: hysteresis) Also used as the external interrupt input. Connection pin for subclocks 22 to 24 15 to 17 14 to 16 I P63/INT13 25 18 17 I Single-clock system product X0A A Dual-clock system product 23 CHAPTER 1 OVERVIEW Table 1.7-1 Explanations of the pin functions (Continued) Pin number SH-DIP(*1) MDIP(*2) QFP(*3) MQFP(*4) LQFP(*5) QFP(*6) P64 26 19 18 X1A 64 32 19 20 21 57 25 12 13 14 56 24 11 12 13 VCC VSS AVCC AVR AVSS A Dual-clock system product Power supply pin Power supply pin (GND) A/D converter power supply pin A/D converter reference voltage input A/D converter power supply pin Used with the same voltage level with VSS. Capacitor connection pin for power supply stabilization Connect the ceramic capacitor of about 0.1 F to the exterior. If "Available" is selected for the step-down circuit stabilization time, VCC is fixed. If "Unavailable" is selected for the stepdown circuit stabilization time, VSS is fixed. Connection pin for subclocks Pin name I/O circuit format J Explanation of functions Single-clock system product General-purpose input port MB89537H/537HC MB89538H/538HC MB89F538 57 50 49 C - MB89P538 MB89PV530/535A/ F538L MB89537/537C/ 537A/537AC MB89538/538C/ 538A/538AC *1:DIP-64P-M01 *4:MQP-64C-P01 *2:MDP-64C-P02 *5:FPT-64P-M03 *3:FPT-64P-M06 *6:FPT-64P-M09 N.C. pin 24 1.7 Explanations of the Pin Functions Table 1.7-2 Explanation of the external EPROM socket pin functions (MB89PV530 only) Pin number MDIP(*1) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 MQFP(*2) 66 67 68 69 70 71 72 73 74 75 77 78 79 80 82 83 84 85 86 87 88 89 91 92 93 94 95 96 65 76 81 90 Pin name A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 01 02 03 VSS 04 05 06 07 08 CE A10 OE A11 A9 A8 A13 A14 VCC I/O circuit format Explanation of functions O Address output pin I O Data input pin Power supply pin (GND) I Data input pin O O O ROM chip enable pin. "H" is always output in standby mode. Address output pin ROM output enable pin. "L" is always output. Address output pin O O O O EPROM power supply pin Internal connection pin. Have it open at all times. - N.C. O *1: MDP-64C-P02 *2: MQP-64C-P01 25 CHAPTER 1 OVERVIEW 1.8 I/O Circuit Format Table 1.8-1 "I/O circuit format" shows the I/O circuit format. The alphabetic characters of the classification column in Table 1.7-1 "Explanations of the pin functions" correspond to those of the I/O circuit format column in Table 1.8-1 "I/O circuit format." I I/O circuit format Table 1.8-1 I/O circuit format Classification Circuit Remarks Oscillation feedback resistor * High-speed side = approx. 1 M * Low-speed side = approx. 10 M Pch Nch X1(X1A) Nch Pch A X0(X0A) * * B Hysteresis input Pull-down resistor Contained in MB89535A, MB89537/ 537C, MB89538/538C, MB8537H/ 537HC, MB89538H/538HC, MB89537A/537AC, and MB89538A/ 538AC. Pull-up resistor is approx. 50 k Hysteresis input * * R Pch C Nch 26 1.8 I/O Circuit Format Table 1.8-1 I/O circuit format (Continued) Classification Circuit * * R Pch Pch Remarks CMOS I/O Software pull-up resistor can be used. Approx. 50 k Pull-up control register D Nch * * R Pch Pch Pull-up control register CMOS I/O Software pull-up resistor can be used. Approx. 50 k E Nch Port input Resource input * * * G Nch Resource input Port input N-channel open-drain output Hysteresis input CMOS input * * Pch N-channel open-drain output Analog input (A/D converter) H Nch Analog input R * * * Pch I Pull-up control register Resource Port Hysteresis input CMOS input Software pull-up resistor can be used. Approx. 50 k 27 CHAPTER 1 OVERVIEW Table 1.8-1 I/O circuit format (Continued) Classification Circuit * * R Remarks CMOS input Software pull-up resistor can be used. Approx. 50 k J Pch Pull-up control register Port 28 CHAPTER 2 HANDLING DEVICE This chapter describes the precautions to be taken when using the MB89530/530H/ 530A series. 2.1 "Notes on Handling Devices" 29 CHAPTER 2 HANDLING DEVICE 2.1 Notes on Handling Devices This section describes the precautions to be taken when handling the power supply voltage and pins of the device. I Notes on Handling Devices Maximum Rated Voltage (Preventing Latchup) The maximum rated voltage must not be exceeded. Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins, or if voltage higher than ratings is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC, AVR, DVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. Power Supply Voltage Fluctuations The power supply voltage must be made as stable as possible. Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pullup or pull-down resistor. Treatment of Unused Input Pins Be sure to leave (internally connected) N.C. pins open. Treatment of Power Supply Pins on Microcontroller with A/D and D/A Converters Connect to be AVCC = VCC and AVSS = AVR = DVR = VSS even if the A/D and D/A converters are not in use. Precautions when Using an External Clock Even when an external clock is used, an oscillation stabilization time is required after a poweron reset and exit from subclock mode or stop mode. 30 2.1 Notes on Handling Devices Program Execution in RAM Debugging of a program that is executed in RAM cannot be done even if MB89PV530 is used. Wild Register Function Debugging cannot be made for the wild register with MB89PV530 and the tool. Check the operation with MB89P538, MB89F538, or MB89F538L on an actual machine. Detailed Processing of the C Pin of the MB89530/530H/530A Series The MB89530/530H/530A series consists of the products listed in Table 2.1-1 "Pin Processing for the Products With and Without a Step-Down Circuit." The operation characteristic depends on whether a product contains a step-down circuit. Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). Table 2.1-1 Pin Processing for the Products With and Without a Step-Down Circuit Product name MB89PV530 MB89P538 MB89F538 MB89537H/537HC MB89538H/538HC MB89537/537C MB89538/538C MB89F538L MB89537A/537AC MB89538A/538AC MB89535A Operating voltage 2.7V to 5.5V 2.7V to 5.5V Not contained. 3.5V to 5.5V 3.5V to 5.5V 3.5V to 5.5V 2.2V to 3.6V 2.2V to 3.6V 2.3V to 3.6V 2.2V to 5.5V 2.2V to 5.5V 2.2V to 5.5V Contained. Contained. Contained. Not contained. Not contained. Not contained. Not contained. Not contained. Not contained. C pin C pin C pin N.C pin N.C pin N.C pin N.C pin N.C pin N.C pin Step-down circuit Not contained. Contained. C pin Pin type N.C pin Pin processing Not required. VCC fixed VSS fixed 0.1 F capacitor connection 0.1 F capacitor connection 0.1 F capacitor connection Not required. Not required. Not required. Not required. Not required. Not required. These products use the same internal resources. However, the operation sequence after power-on reset depends on whether a product contains a step-down circuit. Figure 2.1-1 "Operation Sequences After Power-On Reset Between Product Types" shows the sequence of operations after power-up for each model. 31 CHAPTER 2 HANDLING DEVICE Figure 2.1-1 Operation Sequences After Power-On Reset Between Product Types Power supply (VCC) CPU operation of product containing stepdown circuit (only MB89537H/537HC, MB89538H/538HC, and MB89F538) CPU operation of product with no stepdown circuit (all products other than MB89537H/537HC, MB89538H/538HC, and MB89F538) Step-down circuit stabilization time + oscillation stabilization wait time (219/Fch) Oscillation stabilization wait time (218/Fch) Start of CPU operation of product with no step-down circuit (reset vector) Start of the CPU operation of product with no step-down circuit (reset vector) Note: Fch: Main oscillation frequency As shown in Figure 2.1-1 "Operation Sequences After Power-On Reset Between Product Types", the start of CPU operation of a product with a step-down circuit is slower than that of the product with no step-down circuit. This is because extra time is required for the step-down circuit to stabilize prior to normal operation of the step-down circuit. For MB89P538, a product either with or without a step-down circuit can be selected by C pin processing. Therefore, use it depending on the mask version to be used. 32 CHAPTER 3 CPU This chapter describes the functions and operations of the CPU. 3.1 "Memory Space" 3.2 "Dedicated Registers" 3.3 "General-purpose Registers" 3.4 "Interrupts" 3.5 "Resets" 3.6 "Clock" 3.7 "Standby Mode (Low Power Consumption)" 3.8 "Memory Access Mode" 33 CHAPTER 3 CPU 3.1 Memory Space The memory space of the MB89530/530H/530A series is 64 Kbytes and is made up of the I/O area, RAM area, and ROM area. Some areas in the memory space, such as the general-purpose registers and vector table, are used for specific applications. I Configuration of the Memory Space I/O area (address: 0000H - 007FH) * * This area is allocated to the control registers and data registers of the built-in peripheral devices. Since the I/O area is allocated to a part of the memory space, it can be accessed like normal memory. The area can be accessed faster using direct addressing. Extended I/O area (address: C80H - C91H) * The high-order byte address register, low-order byte address register, and data register of the wild register are allocated to this area. RAM area * * * * * Static RAM is contained as a built-in data area. The internal RAM size is dependent on the part number. 80H to FFH can be accessed faster using direct addressing. 100H to 1FFH can be used as a general-purpose register area. If a reset occurs during a write operation to RAM, data at the address to which data is being written cannot be guaranteed. ROM area * * * ROM is contained as an internal program area. The internal ROM size is dependent on the part number. FFC0H to FFFFH are used as, for example, a vector table. 34 3.1 Memory Space I Memory Map Figure 3.1-1 Memory Map MB89PV530 MB89P538 MB89538/538C MB89538H/538HC MB89538A/538AC 0000H I/O RAM Generalpurpose register MB89535A 0000H 0080H 0100H 0200H 0280H Vacancy 0C80H 0C91H Wild register MB89537/537C MB89537H/537HC MB89537A/537AC 0000H 0080H I/O RAM Generalpurpose register I/O RAM Generalpurpose register 0080H 0100H 0200H 0880H 0100H 0200H 0480H Vacancy 0C80H 0C91H Wild register Vacancy 0C80H 0C91H 4000H Wild register Vacancy 8000H C000H Vacancy Vacancy ROM ROM FFC0H FFFFH Vector table(*2) External ROM(*1) FFC0H FFFFH Vector table(*2) FFC0H FFFFH Vector table(*2) *1 The external ROM area is used only for MB89PV530. *2 Vector table (reset, interrupt, and vector call 35 CHAPTER 3 CPU 3.1.1 Special Areas In addition to the I/O area, the general-purpose register area and vector table area are available as areas for specific applications. I General-purpose Register Area (Address: 0100H - 01FFH) * * * This area is used for 8-bit arithmetic operations and transfer. Supplementary registers are provided. Since this area is allocated to a part of the RAM area, it can also be used as normal RAM. When this area is used as a general-purpose register, it can be accessed faster using shorter instructions by general-purpose register addressing. For details, see Section 3.2.2 "Register Bank Pointer (RP)" and Section 3.3 "General-purpose Registers". I Vector Table Area (Address: FFC0H - FFFFH) * * This area is used as vector tables of the vector call instructions, interrupts, and reset. This area is allocated to the highest ranges of the ROM area, and the start address of the corresponding processing routine is set to the address of each vector table. Table 3.1-1 "Vector Table" lists the addresses of the vector tables referenced corresponding to the vector call instructions, interrupts, and reset. For details, see Section 3.4 "Interrupts", Section 3.5 "Reset", and "CALLV #vct" of Appendix B.3 "Special Instructions". Table 3.1-1 Vector Table Vector call instruction CALLV #0 CALLV #1 CALLV #2 CALLV #3 CALLV #4 CALLV #5 CALLV #6 CALLV #7 Vector table address High FFC0H FFC2H FFC4H FFC6H FFC8H FFCAH FFCCH FFCEH Low FFC1H FFC3H FFC5H FFC7H FFC9H FFCBH FFCDH FFCFH 36 3.1 Memory Space Table 3.1-1 Vector Table (Continued) Vector table address Interrupt name High IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Mode data Reset vector FFDCH FFDEH FFE0H FFE2H FFE4H FFE6H FFE8H FFEAH FFECH FFEEH FFF0H FFF2H FFF4H FFF6H FFF8H FFFAH -- (*1) FFFEH Low FFDDH FFDFH FFE1H FFE3H FFE5H FFE7H FFE9H FFEBH FFEDH FFEFH FFF1H FFF3H FFF5H FFF7H FFF9H FFFBH FFFDH FFFFH *1: FFFCH is not available (Set FFH) 37 CHAPTER 3 CPU 3.1.2 Storing 16-bit Data in Memory Higher data of 16-bit data and stacks are stored in the areas of smaller address values on memory. I Storage of 16-bit Data on RAM When writing 16-bit data into memory, the higher byte of the data is stored at the lower address. The lower byte of the data is stored at the next address. When reading memory, the same procedure is executed.Figure 3.1-2 "Storing 16-bit Data in Memory" shows the storing 16-bit data in memory. Figure 3.1-2 Storing 16-Bit Data in Memory Before execution Memory 0080H After execution Memory MOVW 0081H, A 0080H A 1234 H A 1234 0081H H 12 34 H H 0081H 0082H 0083H 0082H 0083H I Storage of a 16-bit Operand Also when 16 bits are specified in an operand of an instruction, the higher byte is stored at the nearby operation code (instruction) and the lower byte is stored at the next address. This is the same if the operand points to a memory address or is 16-bit immediate data. Figure 3.1-3 "16-bit Data in Instructions" shows the storing 16-bit data in instructions. Figure 3.1-3 16-Bit Data in Instructions [Example] MOV A, 5678H MOVW A, #1234H ;Extended address ;16-bit immediate data After assembling X X X X X X X X X X X X 0 2 5 8 H H H H XX XX 60 56 78 E4 12 34 XX ;Extended address ;16-bit immediate data I Storage of 16-bit Data on the Stack Data of the 16-bit length register saved on the stack due, for example, to an interrupt, is also stored in the same manner, with the higher byte at the smaller address. 38 3.2 Dedicated Registers 3.2 Dedicated Registers The dedicated registers in the CPU consist of the program counter (PC), two arithmetic operation registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16 bits. I Dedicated Register Configuration The dedicated registers in the CPU consist of seven 16-bit registers. Some of these registers are also able to be used as 8-bit registers, using the lower 8 bits only. Figure 3.2-1 "Dedicated Register Configuration" shows the structure of the dedicated registers. Figure 3.2-1 Dedicated Register Configuration Initial value FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = "0", IL0, IL1 = "11" Other bits are indeterminate 16 bits PC A T IX EP SP RP PS CCR : Program counter A register for indicating the current instruction storage positions : Accumulator A temporary register for storing arithmetic operations or transfer instructions : Temporary accumulator A register which performs arithmetic operations with the accumulator : Index register A register for indicating an index address : Extra pointer A pointer for indicating a memory address : Stack pointer A register for indicating the current stack location : Program status A register for storing a register bank pointer and condition code I Dedicated Register Functions Program counter (PC) The program counter is a 16-bit counter that indicates the memory address of the instruction currently being executed by the CPU. Instruction execution, interrupts, resets, and similar update the contents of the program counter. The initial value during a reset is the read address of the mode data (FFFDH). Accumulator (A) The accumulator is a 16-bit arithmetic operation register. The accumulator is used to perform arithmetic operations and data transfers with data in memory or in other registers such as the temporary accumulator (T). The content of the accumulator can be treated as either word (16bit) or byte (8-bit) data. Only the lower 8 bits (AL) of the accumulator are used for byte arithmetic operations or transfers. In this case, the upper 8 bits (AH) remain unchanged. The content of the accumulator after a reset is indeterminate. 39 CHAPTER 3 CPU Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (A). The content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations. For byte-length arithmetic operations, only the lower 8 bits of the temporary accumulator (TL) are used and the upper 8 bits (TH) are not used. Executing a transfer instruction to transfer data to the accumulator (A) automatically transfer the previous content of the accumulator to the temporary accumulator. In this case also, a byte transfer leaves the upper 8 bits of the temporary accumulator (TH) unchanged. The content of the temporary accumulator after a reset is indeterminate. Index register (IX) The index register is a 16-bit register used to hold the index address. The index register is used in conjunction with a single byte offset value (-128 to +127). Adding the sign-extended offset value to the index address generates the memory address for data access. The content of the index register after a reset is indeterminate. Extra pointer (EP) The extra pointer is a 16-bit register used to hold a memory address for data access. The content of the extra pointer after a reset is indeterminate. Stack pointer (SP) The stack pointer is a 16-bit register used to hold the address referenced during operations such as interrupts, subroutine calls, and the stack save and restore instructions. The value of the stack pointer during program execution is the address of the most recently saved data on the stack. The content of the stack pointer after a reset is indeterminate. Program status (PS) The program status is a 16-bit control register. The upper 8 bits contain the register bank pointer (RP) which points to the address of the current general-purpose register bank. The lower 8 bits contain the condition code register (CCR) which contains flags indicating the current CPU status. The two 8-bit registers which form the program status cannot be accessed independently (the program status can only be accessed by the MOVW A,PS and MOVW PS,A instructions). Refer to the "F2MC-8L Programming Manual" for details on using the dedicated registers 40 3.2 Dedicated Registers 3.2.1 Condition Code Register (CCR) The condition code register (CCR) located in the lower 8 bits of the program status (PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations and the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not the CPU accepts interrupt requests. I Structure of Condition Code Register (CCR) Figure 3.2-2 Structure of Condition Code Register RP CCR CCR initial value X011XXXXB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PS R4 R3 R2 R1 R0 -- -- -- H I IL1 IL0 N Z V C X: Indeterminate Half-carry flag Interrupt enable flag Interrupt level bits Negative flag Zero flag Overflow flag Carry flag Note: The condition code register is part of the program status (PS) and cannot be accessed independently. Reference: In practice, the flag bits are rarely fetched and used directly. Instead, the bits are used indirectly by instructions such as branch instructions (such as BNZ) or the decimal adjustment instructions (DAA, DAS). The content of the flags after a reset is indeterminate. I Arithmetic Operation Result Bits Half-carry flag (H) Set when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an arithmetic operation. Cleared otherwise. As this flag is for the decimal adjustment instructions, do not use this flag in cases other than addition or subtraction. Negative flag (N) Set if the most significant bit (MSB) is set to 1 as a result of an arithmetic operation. Cleared when the bit is set to 0. Zero flag (Z) Set when an arithmetic operation results in 0. Cleared otherwise. 41 CHAPTER 3 CPU Overflow flag (V) Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. Carry flag (C) Set when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in case of a shift instruction. Figure 3.2-3 "Change of Carry Flag by Shift Instruction" shows the change of the carry flag by a shift instruction. Figure 3.2-3 Change of Carry Flag by Shift Instruction * Left shift (ROLC) Bit 7 C Bit 0 * Right shift (RORC) Bit 7 Bit 0 C I Interrupt Acceptance Control Bit Interrupt enable flag (I) Interrupt is enabled when this flag is set to "1" and the CPU accepts interrupt. Interrupt is prohibited when this flag is set to "0" and the CPU does not accept interrupt. The initial value after a reset is "0". Normal practice is to set the flag to "1" by the SETI instruction and clear to "0" by the CLRI instruction. Interrupt level bits (IL1, IL0) These bits indicate the level of the interrupt currently being accepted by the CPU. The value is compared with the interrupt level setting registers (ILR1 to ILR4) which have a setting for each peripheral function interrupt request (IRQ0 to IRQF). Given that the interrupt enable flag is enabled (I = "1"), the CPU only performs interrupt processing for interrupt requests with an interrupt level value that is less than the value of these bits. Table 3.2-1 "Interrupt Level" lists the interrupt level priorities. The initial value after a reset is "11B". Table 3.2-1 Interrupt Level IL1 0 0 1 1 IL0 0 1 1 0 1 2 3 Interrupt level High-low High Low (no interrupt) 42 3.2 Dedicated Registers Reference: The interrupt level bits (IL1, IL0) are normally "11" when the CPU is not processing an interrupt (during main program execution). See Section 3.4 "Interrupts" for details on interrupts. 43 CHAPTER 3 CPU 3.2.2 Register Bank Pointer (RP) The register bank pointer (RP) located in the upper 8 bits of the program status (PS) indicates the address of the general-purpose register bank currently in use. The RP is converted to form the actual address in general-purpose register addressing. I Structure of Register Bank Pointer (RP) Figure 3.2-4 "Structure of Register Bank Pointer" shows the structure of the register bank pointer. Figure 3.2-4 Structure of Register Bank Pointer RP CCR RP initial value XXXXXXXXB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PS R4 R3 R2 R1 R0 -- -- -- H I IL1 IL0 N Z V C X: Indeterminate The register bank pointer indicates the address of the register bank currently in use. Figure 3.25 "Rule for Conversion of Actual Addresses of General-purpose Register Area" shows the relationship between the pointer contents and the actual address is based on the conversion rule. Figure 3.2-5 Rule for Conversion of Actual Addresses of General-purpose Register Area Upper bits of RP "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 Lower operation codes R0 b2 b1 b0 Generated addresses A15 A14 A13 A12 A10 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The register bank pointer points to the memory block (register bank) in the RAM area that is used for general-purpose registers. A total of 32 register banks are available. A register bank is specified by setting a value between 0 and 31 in the upper 5 bits of the register bank pointer. Each register bank contains 8-bit general-purpose registers. Registers are specified by the lower 3 bits of the operation codes. Using the register bank pointer, the addresses 0100H to 01FFH can be used as the generalpurpose register area. However, the available area is limited on some products if internal RAM only is used. The initial value after a reset is indeterminate. Note: Before using a general-purpose register, set the register bank pointer (RP). The register bank pointer is part of the program status (PS) and cannot be accessed independently. 44 3.3 General-purpose Registers 3.3 General-purpose Registers The general-purpose registers are a memory block made up of banks, with 8 x 8-bit registers per bank. The register bank pointer (RP) is used to specify the register bank. The function permits the use of up to 32 banks. Register banks are valid for interrupt processing, vector call processing, and subroutine calls. I Structure of General-purpose Registers * * * The general-purpose registers are 8 bits and located in the register banks of the generalpurpose register area (in RAM). One bank contains eight registers (R0 to R7) and up to a total of 32 banks. The register bank currently in use is specified by the register bank pointer (RP). The lower three bits of the operation code specify general-purpose register 0 (R0) to general-purpose register 7 (R7). Figure 3.3-1 "Register Bank Structure" shows the register bank structure. Figure 3.3-1 Register Bank Structure Lower 3 bits of the operation code 100H* R0 R1 R2 R3 R4 R5 R6 R7 108H* R0 : R7 : : : 1F8H* R0 : 1FFH R7 000 001 010 011 100 101 110 111 000 : 111 : : : 000 : 111 Bank 0 (RP="00000---B") 32 banks (RAM area) The number of banks is limited on available RAM size. Bank 1 (RP="00001---B") Bank 2 to Bank 30 Bank 31 (RP="11111---B") *: The top address of a register bank = 0100H + 8 x (upper 5 bits of RP) see Section 3.1.1 "Special Areas" for the general-purpose register area available for each product. 45 CHAPTER 3 CPU I Features of General-purpose Registers General-purpose registers have the following features: * * RAM can be accessed at high-speed using short instructions (general-purpose register addressing). Registers are grouped in blocks in the form of register banks. This simplifies the process of saving register contents and dividing registers by function. Dedicated register banks can be permanently assigned for each interrupt processing or vector call (CALLV #0 to #7) processing routine by general-purpose register. For example, register bank 4 interrupt 2. For example, a particular interrupt processing routine only uses a particular register bank which cannot be written to unintentionally by other routines. The interrupt processing routine only needs to specify its dedicated register bank at the start of the routine to effectively save the general-purpose registers in use prior to the interrupt. Therefore, saving the general-purpose registers to the stack or other memory location is not necessary. This allows high-speed interrupt handling while maintaining simplicity. Also, as an alternative to saving general-purpose registers in subroutine calls, register banks can be used to create reentrant programs (programs that do not use fixed addresses and can be entered more than once) usually made by the index register (IX). Note: If an interrupt processing routine changes the register bank pointer (RP), ensure that the program does not also change the interrupt level bits in the condition code register (CCR: IL1, 0) when specifying the register bank. 46 3.4 Interrupts 3.4 Interrupts The MB89530/530H/530A series has 15 interrupt request input corresponding to peripheral functions. An interrupt level can be set independently. If an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller. The CPU performs interrupt operation according to how the interrupt is accepted. The CPU wakes up from standby modes, and returns to the interrupt or normal operation. I Interrupt Requests from Peripheral Functions Table 3.4-1 "Interrupt Request and Interrupt Vector" lists the interrupt requests corresponding to the peripheral functions. On acceptance of an interrupt, execution branches to the interrupt processing routine. The contents of interrupt the vector table address corresponding to the interrupt request specifies the branch destination address for the interrupt processing routine. An interrupt processing level can be for each interrupt request in the interrupt level setting registers (ILR1, ILR2, ILR3, ILR4). Three levels are available. If an interrupt request with the same or lower level occurs during execution of an interrupt processing routine, the letter interrupt is not normally processed until the current interrupt processing routine completes. If interrupt request set the same level occur simultaneously, the highest priority is IRQ0. 47 CHAPTER 3 CPU Table 3.4-1 Interrupt Requests and Interrupt Vectors Vector table address Interrupt request Higher IRQ0 (external interrupt (edge) INT10 to INT11) IRQ1 (external interrupt (edge) INT12 to INT13) IRQ2 I2C IRQ3 (setting not available) IRQ4 (external interrupt (level) INT20 to INT27) IRQ5 (PWM timer 1) IRQ6 (PWM timer 2) IRQ7 (PWC) IRQ8 (16-bit timer/counter interrupt) IRQ9 (8-bit serial I/O) IRQA (UART/SIO) IRQB (UART reception) IRQC (UART transmission) IRQD (A/D converter) IRQE (timebase timer) IRQF (watch prescaler) FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH Bit name of the interrupt level setting register L01, L00 L11, L10 L21, L20 L31, L30 L41, L40 L51, L50 L61, L60 L71, L70 L81, L80 L91, L90 LA1, LA0 LB1, LB0 LC1, LC0 LD1, LD0 LE1, LE0 LF1, LF0 Priority if interrupt requests with the same level occur simultaneously High Low 48 3.4 Interrupts 3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) The interrupt level setting registers (ILR1, ILR2, ILR3, ILR4) together contain 16 blocks of 2-bit data, with each data corresponding to an interrupt request from a peripheral function. The interrupt level for each interrupt is set in that interruptis corresponding 2-bit data (interrupt level setting bits). I Structure of Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) Figure 3.4-1 Structure of the Interrupt Level Setting Register Register ILR1 Address 0 0 7 BH bit7 L31 W L71 W 0 0 7 DH LB1 W ILR4 0 0 7 EH LF1 W W: write only bit6 L30 W L70 W LB0 W LF0 W bit5 L21 W L61 W LA1 W LE1 W bit4 L20 W L60 W LA0 W LE0 W bit3 L11 W L51 W L91 W LD1 W bit2 L10 W L50 W L90 W LD0 W bit1 L01 W L41 W L81 W LC1 W bit0 L00 W L40 W L80 W LC0 W 11111111B 11111111B 11111111B Initial value 11111111B ILR2 0 0 7 CH ILR3 Two bits of the interrupt level setting registers are allocated to each interrupt request. The value of the interrupt level setting bits in these registers sets the interrupt priority (interrupt levels 1 to 3). The interrupt level setting bits are compared with the interrupt level bits in the condition code register (CCR: IL1, IL0). The CPU does not accept interrupt requests set to interrupt level 3. Table 3.4-2 "Interrupt Level Setting Bits and Interrupt Level" shows the relationship between the interrupt level setting bits and the interrupt levels. Table 3.4-2 Interrupt Level Setting Bits and the Interrupt Level L01 to LF1 0 0 1 1 L00 to LF0 0 1 1 0 1 2 3 Low (no interrupt) Request Interrupt level High-low High X: 0 to F Associated interrupt numbers 49 CHAPTER 3 CPU Reference: The interrupt level bits in the condition code register (CCR: IL1, IL0) are normally "11B" during main program execution. Note: As the IRL1, ILR2, ILR3, and ILR4 registers are write-only, the bit manipulation instructions (SETB, CLRB) cannot be used. 50 3.4 Interrupts 3.4.2 Interrupt Processing The interrupt controller transmits the interrupt level to the CPU when an interrupt request is generated by a peripheral function. If the CPU is able to receive the interrupt, the CPU temporarily halts the currently executing program and executes the interrupt processing routine. I Interrupt Processing The procedure for interrupt operation is performed in the following order: interrupt source generated at peripheral function, set the interrupt request flag bit (request FF), discriminate the interrupt request enable bit (enable FF), the interrupt level (ILR1, ILR2, ILR3, ILR4 and CCR: IL1, IL0), simultaneously generated interrupt requests with the same level, then check the interrupt enable flag (CCR: I). Figure 3.4-2 "Interrupt Processing" shows the interrupt processing. Figure 3.4-2 Interrupt Processing Internal data bus Condition code register (CCR) Register file IR IPLA Check F2MC-8L*CPU START (7) PS I IL Comparator (5) Wake-up from stop mode Wake-up from sleep mode Exit watch mode (6) (1) Initialize peripheral Enable FF Is an interrupt request present at the peripheral? NO YES Request FF (3) * * * AND Level comparator RAM (4) Peripherals Is interrupt request output enabled for the peripheral? NO (4) Interrupt controller (3) YES Check the interrupt priority level and transfer the level to the CPU (5) Compare the level with the IL bits in PS Is the level higher than IL? Main program execution YES (2) I-flag = 1? NO NO Interrupt processing routine YES Clear interrupt request (7) Save PC and PS to the stack (6) Restore PC and PS Execute interrupt processing PC interrupt vector Update IL in PS RETI 51 CHAPTER 3 CPU (1) After a reset, all interrupt requests are disabled. Initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ILR1, ILR2, ILR3, ILR4), and start peripheral function. The interrupt level can be set to 1, 2 or 3. Level 1 is the highest priority, followed by level 2. Setting level 3 disables the interrupt for that peripheral function. Execute the main program (for multiple interrupts, execute the interrupt processing routine). The interrupt request flag bit (request FF) for a peripheral function is set to "1" when the peripheral function generates an interrupt source. If the interrupt request enable bit for the peripheral function is set to "enable" (enable FF = "1"), the peripheral function outputs the interrupt request to the interrupt controller. The interrupt controller continuously monitors for interrupt requests from the peripheral functions and passes the interrupt level of the current interrupt request with the highest interrupt level to the CPU. The interrupt controller also evaluates the priority order if requests with the same level are present simultaneously. If the interrupt level received by the CPU has a higher priority (a lower level value) than the level set in the interrupt level bits in the condition code register (CCR: IL1, IL0), the CPU checks the interrupt enable flag (CCR: I) and receives the interrupt if interrupts are enabled (CCR: I = "1"). The CPU saves the contents of the program counter (PC) and program status (PS) on the stack, reads the top address of the interrupt processing routine from the interrupt vector table for the interrupt, updates the interrupt level bits in the condition code register (CCR: IL1, IL0) with the received interrupt level, and starts execution of the interrupt processing routine. Finally, on execution of the RETI instruction, the CPU restores the program counter (PC) and program status (PS) values saved on the stack and resumes execution from the instruction following the last instruction executed before the interrupt. (2) (3) (4) (5) (6) (7) Note: As the interrupt request flag bit of a peripheral function is not cleared automatically when an interrupt request is received, the bit must be cleared by the program (normally, by writing "0" to the interrupt request flag bit) at interrupt processing routine. An interrupt wakes up the CPU from standby mode (low-power consumption). see Section 3.7 "Standby Modes (Low-Power Consumption)" for details. Reference: If the interrupt request flag bit is cleared at the top of the interrupt processing routine, the peripheral function that has generated the interrupt becomes able to generate another interrupt during execution of the interrupt processing routine (resetting the interrupt request flag bit). However, the interrupts are not normally accepted until the current processing routine completes. 52 3.4 Interrupts 3.4.3 Multiple Interrupts Multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register (ILR1 to ILR4) for two or more interrupt requests from peripheral functions. I Multiple Interrupts If the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the CPU halts the current interrupt process and switches to accept the interrupt with the higher priority. Interrupt levels can be set in the range 1 to 3. However, the CPU does not accept interrupt requests set to interrupt level 3. Example of multiple interrupts As an example of multiple interrupt processing, assume that an external interrupt has a higher priority than the timer interrupt. The timer interrupt is set to level 2 and the external interrupt is set to level 1. Figure 3.4-3 "Example of Multiple Interrupts" shows the processing when the external interrupt occurs during execution of timer interrupt processing. Figure 3.4-3 Example of Multiple Interrupts Main program Timer interrupt processing Interrupt level 2 (CCR:IL1, IL0 = "10") External interrupt processing Interrupt level 1 (CCR:IL1, IL0 = "01") Initialize peripheral (1) Timer interrupt occurs (2) Halt Restart Restart main program (8) (6) Timer interrupt processing (7) Timer interrupt returns (5) External interrupt returns (3) External interrupt occurs (4) External interrupt processing * During execution of timer interrupt processing, the interrupt level bits in the condition code register (CCR:IL1, IL0) are automatically set to the same value as the interrupt level setting register (ILR1, ILR2, ILR3, ILR4) corresponding to the timer interrupt (level 2 in this example). If the interrupt request set to higher interrupt level (level 1 in this example) occurs at this time, the interrupt processing has priority. To temporarily disable multiple interrupts during the timer interrupt, the interrupt enable flag in the condition code register is set to "interrupts disabled" (CCR: I = "0") or the interrupt level bits (IL1, IL0) set to "00". On execution of the interrupt return instruction (RETI) at the completion of interrupt processing, the CPU restores the program counter (PC) and program status (PS) values saved on the stack and resumes execution of the interrupted program. Restoring the program status (PS) returns the condition code register (CCR) to the value prior to the interrupt. 53 * * CHAPTER 3 CPU 3.4.4 Interrupt Processing Time The total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing). The maximum time for this process is 30 instruction cycles. I Interrupt Processing Time When an interrupt request occurs, the time until the interrupt is accepted and the interrupt processing routine is executed includes the interrupt request sampling time and the interrupt handling time. Interrupt request sampling time Whether or not an interrupt request has occurred is determined by sampling and testing for interrupt requests during the final cycle of each instruction. Therefore, the CPU is unable to identify interrupt requests during execution of an instruction. The longest delay occurs when an interrupt request is generated immediately after starting execution of a DIVU instruction, which has the longest instruction cycles (21 instruction cycles). Interrupt handling time Nine instruction cycles are required to perform the following preparation for interrupt processing after the CPU accepts an interrupt request: * * * Save the program counter (PC) and program status (PS). Set the top address of the interrupt processing routine (the interrupt vector) in the PC. Update the interrupt level bits (PS:CCR: IL1, IL0) in the program status (PS). Figure 3.4-4 "Interrupt Processing Time" shows the interrupt processing time. Figure 3.4-4 Interrupt Processing Time Execution of a standard instruction CPU operation Interrupt request sampling time Interrupt handling Interrupt processing routine Interrupt waiting time Interrupt handling time (9 instruction cycles) Interrupt request occurs : Final cycle of instruction. Interrupt requests are sampled at this timing. The total interrupt processing time of 21 + 9 = 30 instruction cycles is required if an interrupt request occurs immediately after starting execution of a DIVU instruction, which has the longest instruction cycles (21 instruction cycles). If, on the other hand, the program does not use the DIVU or MULU instructions, the maximum interrupt processing time is 6 + 9 = 15 instruction cycles. The time of one instruction cycle changes with the clock mode and the main clock frequency as selected by the "speed-shift" (gear) function. see Section 3.6 "Clock" for details. 54 3.4 Interrupts 3.4.5 Stack Operation during Interrupt Processing This section describes the saving of the register contents to the stack and restore operation during interrupt processing. I Stack Operation at Start of Interrupt Processing The CPU automatically saves the current contents of the program counter (PC) and program status (PS) to the stack when an interrupt is accepted. Figure 3.4-5 "Stack Operation at Start of Interrupt Processing" shows the stack operation at the start of interrupt processing. Figure 3.4-5 Stack Operation at Start of Interrupt Processing Immediately before interrupt Immediately after interrupt Address Memory Address Memory PS PC 0870H E000H SP 0280H 027CH 027DH 027EH 027FH 0280H 0281H xxH xxH xxH xxH xxH xxH SP PS PC 027CH 027CH 027DH 027EH 027FH 0280H 0281H 08H 70H E0H 00H 0870H E000H xxH xxH PS PC I Stack Operation at Interrupt Return On execution of the interrupt return instruction (RETI) at the completion of interrupt processing, the CPU performs the opposite processing to interrupt initiation, restoring first the program status (PS) and then the program counter (PC) from the stack. This returns the PS and PC to their states immediately prior to the start of the interrupt. Note: The CPU does not automatically save the accumulator (A) or temporary accumulator (T) contents to the stack. Use the PUSHW and POPW instructions to save and restore A and T contents to and from the stack. 55 CHAPTER 3 CPU 3.4.6 Stack Area for Interrupt Processing Interrupt processing execution uses the stack area in RAM. The contents of the stack pointer (SP) specifies the top address of the stack area. I Stack Area for Interrupt Processing The subroutine call instruction (CALL) and vector call instruction (CALLV) use the stack area to save and restore the program counter (PC). The stack area is also used by the PUSHW and POPW instructions to temporarily save and restore registers. * * The stack area is located in RAM along with the data area. Initializing the stack pointer (SP) to the top address of RAM and allocating data areas upwards from the bottom RAM address is recommended. Figure 3.4-6 "Stack Area for Interrupt Processing" shows the example of stack area setting. Figure 3.4-6 Stack Area for Interrupt Processing 0000H I/O 0080H Data area 0100H Generalpurpose registers RAM 0200H Stack area 0280H Recommended set value for SP (When the top address of RAM is 0280H.) Access prohibited ROM FFFFH Reference: The stack area is used in the downward direction starting from a high address by functions such as interrupts, subroutine calls, and the PUSHW instruction. Instructions such as return instructions (RETI, RET) and the POPW instruction release stack area in the upward direction. Take care when the stack address is decreased by multiple interrupts or subroutine calls that the stack does not overlap the general-purpose register area or areas containing other data. 56 3.5 Resets 3.5 Resets The resets has the following four types of reset source: * External reset * Software reset * Watchdog reset * Power-on reset At reset, main clock oscillation stabilization wait time may or may not occur by the operating mode and option settings. I Reset Source Table 3.5-1 Reset Source Reset source External reset Software reset Watchdog reset Power-on reset Reset conditions Set the external reset pin to the "L" level. Write "0" to the software reset bit in the standby control register (STBC: RST). Watchdog timer overflow Power is turned on (only on products with a power-on reset). External reset Inputting an "L" level to the external reset pin (RST) generates an external reset. Returning the reset pin to the "H" level wakes up the CPU from the external reset. The external reset pin can also function as a reset output pin. Software reset Writing "0" to the software reset bit in the standby control register (STBC: RST) generates a four-instruction cycle reset. Watchdog reset The watchdog reset generates a four-instruction cycle reset if data is not written to the watchdog timer control register (WDTC) within a fixed time after the watchdog timer starts. Power-on reset A reset is generated by power-on to initialize the internal circuit. 57 CHAPTER 3 CPU I Main Clock Oscillation Stabilization Wait Time and the Reset Source Whether there will be an oscillation stabilization wait time depends on the operating mode when reset occurs, and the power-on reset option selected. Following reset, operation always starts out in the normal main clock operating mode, regardless of the kind of reset it was, or the operating mode (the clock mode and standby mode) prior to reset. Therefore, if reset occurs while the main clock oscillator is stopped or in a stabilization wait time, the system will be in a "main clock oscillation stabilization reset" state, and a clock stabilization period will be provided. If the device is set for no power-on reset, however, no main clock oscillation stabilization wait time is provided for power-on or external reset. In software or watchdog reset, if the reset occurs while the device is in main clock mode, no stabilization time is provided. If it occurs in the subclock mode, however, a stabilization time is provided since the main clock oscillation is stopped.Table 3.5-2 "Reset Source and Oscillation Stabilization Wait Time" shows the relationships between the reset sources and the main clock oscillation stabilization wait time, and reset mode (mode fetch) operations. Table 3.5-2 Reset Source and Oscillation Stabilization Wait Time Ret source External reset (*1) Software and watchdog reset Power-on reset Operating state At power on, during stop mode, or subclock mode Main clock mode Subclock mode Reset operation and main clock oscillation stabilization wait time After the main clock oscillation stabilization delya time, if the external reset is waked up, reset is operated.(*2) After 4-instruction-cycle reset occurs, reset is operated.(*3) Reset is operated after the main clock oscillation stabilization wait time.(*2) Device enters main clock oscillation stabilization wait time at power on. Reset is operated after wait time ends.(*2) *1: No oscillation stabilization wait time is required for external reset while main clock mode is operating. Reset is operated after external reset is waked up. *2: If the reset output option is selected, "L" is output at RST pin during the main clock oscillation stabilization wait time. *3: If the reset output option is selected, "L" level is output at RST pin during 4-instruction-cycle. 58 3.5 Resets 3.5.1 External Reset Pin Inputting an "L" level to the external reset pin generates a reset. If products are set to with the reset output (optional), the pin outputs an "L" level depending on internal reset sources. I Block Diagram of External Reset Pin The external reset pin (RST) is a hysteresis input type and N-ch open-drain output type with a pull-up resistor. Figure 3.5-1 Block Diagram of External Reset Pin Pull-up resistor Approx. 50 k/5.0V RST Pin N-ch P-ch Internal reset source Internal reset signal Input buffer I External Reset Pin Functions Inputting an "L" level to the external reset pin (RST) generates an internal reset signal. On products with the reset output, the pin outputs an "L" level depending on internal reset sources or during the oscillation stabilization wait time due to an external reset. Software reset, watchdog reset, and power-on reset are classed as internal reset sources. Note: * The external reset input accepts asynchronous with the internal clock. Therefore, initialization of the internal circuit requires a clock. Especially when an external clock is used, a clock is needed to be input at the reset. If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). * 59 CHAPTER 3 CPU 3.5.2 Reset Operation When the CPU wakes up from a reset, the CPU selects the read address of the mode data and reset vector according to the mode pin settings, then performs a mode fetch. The mode fetch is performed after the oscillation stabilization wait time has passed when power is turned on to a product with power-on reset, or on wake-up from subclock or stop mode by a reset. If reset occurs during a write to RAM, the contents of the RAM address cannot be assured. I Overview of Reset Operation Figure 3.5-2 Reset Operation Flow Diagram Software reset Watchdog reset External reset input Power-on reset During reset operation In subclock mode? Power-on, subclock or stop mode? NO YES Main clock oscillation stabilization wait reset state Main clock oscillation stabilization wait reset state NO YES Main clock oscillation stabilization wait reset state Wakes up from external reset? NO YES Fetch mode data Mode fetch (reset operation) Fetch reset vector Normal operation (RUN state) Fetch the instruction code from the address indicated by the reset vector and begin execution. 60 3.5 Resets I Mode Pins The MB89530/530H/530A series devices are single-chip mode devices. The mode pins (MOD1, MOD2) must be tied to VSS. The mode pin settings determine whether the mode data and reset vector are read from internal ROM. Do not change the mode pin settings, even after the reset has completed. I Mode Fetch When the CPU wakes up from a reset, the CPU reads the mode data and reset vector from internal ROM. Mode data (address: FFFDH) Always set the mode to "00H" (single-chip mode). Reset vector (address: FFFEH (upper), FFFFH (lower)) Contains the address where execution is to start after completion of the reset. The CPU starts executing instructions from the address contained in the reset vector. I Oscillation Stabilization Wait Reset State On products with power-on reset, the reset operation for a power-on reset or external reset in subclock or stop (main/sub) mode starts after the main clock oscillation stabilization wait time selected by the stabilization wait time option. If the CPU has not woken up from the external reset input when the wait time completes, the reset operation does not start until the CPU wakes up from external reset. As the oscillation stabilization wait time is also required when an external clock is used, a reset requires that the external clock is input. The main clock oscillation stabilization wait time is timed by the timebase timer. I Effect of Reset on RAM Contents If a reset condition occurs, the operation of the instruction currently being executed is suspended and the device enters the reset status. The contents written in RAM are unchanged before and after a reset. However, if a reset occurs during the writing of 16-bit data, only the high-order byte of the data is written and the low-order byte may not be written. If a reset occurs immediately before or after writing, the contents of the address to which writing is being performed will be unpredictable. After a reset, therefore, all of the RAM to be used must be initialized. 61 CHAPTER 3 CPU 3.5.3 Pin States during Reset Reset initialized the pin states. I Pin States during Reset When a reset source occurs, with a few exceptions, all I/O pins (peripheral pins) go to the highimpedance state and the mode data is read from internal ROM. I Pin States after Reading Mode Data With a few exceptions, the I/O pins remain in the high-impedance state immediately after reading the mode data (The pin for which "pull-up resistor available" is selected in the pull-up option setting register is set to the "H" level.). Note: For devices connected to pins that change to high-impedance state when a reset source occurs take care that malfunction does not occur due to the change in the pin states. For the pin states under conditions other than the reset state, see Appendix F "Pin Statuses of the MB89530/530H/530A Series". 62 3.6 Clock 3.6 Clock Dual clock oscillation circuits are contained in the clock generator. By connecting each external resonator, the high-speed main clock and low-speed subclock are generated independently (oscillator source). A clock generated externally can also be input. The speed and supply of the dual clock is controlled by the clock controller according to the clock mode and standby mode. I Clock Supply Map The clock oscillation and the supply to CPU and peripheral circuits (peripheral functions) are controlled by the clock controller. Thus, the operating clock of CPU and peripheral circuits are affected by switching between the main clock and the subclock (clock mode), speed switching of the main clock (gear function), and the standby mode (sleep/stop/watch). The divide-by output of the free-run counter of the clock for peripheral circuits is supplied to each peripheral function. The divide-by output of the timebase timer operating at divide-by-two oscillation of the main clock oscillation and peripheral functions to which divide-by output of the watch prescaler operating at the subclock is supplied are available and are not affected by the gear function. The following Figure 3.6-1 "Clock Supply Map" shows a clock supply map. 63 CHAPTER 3 CPU Figure 3.6-1 Clock Supply Map X0 pin Peripheral functions Main clock FCH oscillation circuit Timebase timer X1 pin *1, 3 Baud rate generator Watchdog timer *1 *2 UART UCK pin Clock controller Clock mode Stop mode Oscillation control 3 8-bit PWM timer - 1 8-bit PWM timer - 2 *2 Divide-by-4 Divide-by-8 Divide-by-16 Divide-by-64 Gear function 3 *2 3 16-bit timer counter EC 3 Supply to CPU 8-bit serial I/O pin Sleep/stop/clock oscillation stabilization wait Clock mode Stop clock Supply to peripheral circuits *2 SCK1 pin 3 Baud rate generator 6-bit PPG UART/SIO I2C *1 *2 SCK pin Divide-by-two 2 *2 SCL pin X0A pin Free-run counter *2 Subclock oscillation circuit Continuous start *4 ADST A/D converter pin X1A pin FCL 3 Watch prescaler *1, 3 *2 PWC PWCK pin 3 12-bit PPG *2 FCH: Main clock oscillation FCL: Subclock oscillation *1: *2: *3: *4: *1 Oscillation stabilization wait control Not affected by the clock mode and gear function. The operating speed is affected by the clock mode and gear function. Operations stop if the clock (main or sub), which is the source of oscillation, stops. The timebase timer output can be selected during continuous start of A/D conversion. In other modes, the clock speed is influenced by the clock mode and gear function. 64 3.6 Clock 3.6.1 Clock Generator The permission and stop of oscillation of the main clock and subclock are controlled by the clock mode and stop mode. I Clock Generator Crystal resonator or ceramic resonator Make connections as shown in Figure 3.6-2 "Connection Example of the Crystal and Ceramic Resonator". Figure 3.6-2 Connection Example of the Crystal and Ceramic Resonator Dual clock system Main clock oscillation circuit Subclock oscillation circuit Single clock system Main clock oscillation circuit Subclock oscillation circuit MB89530/530H/530A series X0 X1 P63/INT13/X0A P64/X1A R X0 MB89530/530H/530A series X1 P63/INT13/X0A P64/X1A Usable as a generalpurpose port. 32.768kHz C C C C C C 65 CHAPTER 3 CPU External clock Connect the external clock to the X0 pin as shown in Figure 3.6-3 "Connection Example of the External Clock" and open the X1 pin. If the subclock should be supplied externally, connect the external clock to the X0A pin and open the X1A pin. Figure 3.6-3 Connection Example of the External Clock Dual clock system Main clock oscillation circuit Subclock oscillation circuit Single clock system Main clock oscillation circuit Subclock oscillation circuit MB89530/530H/530A series X0 X1 P63/INT13/X0A P64/X1A Open Open X0 MB89530/530H/530A series X1 P63/INT13/X0A P64/X1A Open Usable as a generalpurpose port. Note: The MB89530/530H/530A series can operate with the single clock system. When using only the main clock, a return from subclock mode cannot be performed. The following table lists the options of the single and dual clock system products: Table 3.6-1 Part Number Options Option MB89P538-101 MB89P538-201 Minimum tinst 4 4 Clock system Single clock system Dual clock system 66 3.6 Clock 3.6.2 Clock Controller The clock controller is made up of the following seven blocks: * Main clock oscillation circuit * Subclock oscillation circuit * System clock selector * Clock control circuit * Oscillation stabilization wait time selector * System clock control register (SYCC) * Standby control register (STBC) I Block Diagram of the Clock Controller Figure 3.6-4 "Block Diagram of the Clock Controller" shows a block diagram of the clock controller. Figure 3.6-4 Block Diagram of the Clock Controller Standby control register (STBC) STP SLP SPL RST TMD Pin state Subclock control Operation allowed Subclock oscillation circuit Divide-by-two Divide-by-two Stop Sleep Clock Clock for watch prescaler Clock for timebase timer Main clock control Operation allowed System clock selector Prescaler Divide-by-4 Divide-by-8 Divide-by-16 Divide-by-64 Supply to CPU Selector Selector Main clock oscillation circuit Clock control circuit 1 tinst Supply to peripheral circuits 1 tinst From timebase timer From watch prescaler FCH FCH FCH Oscillation stabilization wait time selector Clock supply stop to CPU 2 Clock designation SCM WT2 WT1 WT0 SCS CS1 CS0 System clock control register (SYCC) FCH: Main clock oscillation FCL: Subclock oscillation t inst: Instruction cycle 67 CHAPTER 3 CPU Main clock oscillation circuit Oscillation circuit of the main clock. subclock mode. Subclock oscillation circuit Oscillation circuit of the subclock. This circuit always oscillates in a mode other than sub-stop mode. System clock selector One type is selected from the four clocks and the subclocks obtained by dividing the oscillation of the main clock to supply it to the clock control circuit. Clock control circuit The operating clock supply to CPU and each peripheral circuit is controlled according to normal operation (RUN) and standby modes (sleep, stop, watch). The clock controller stops the supply of clocks to CPU until the clock supply stop signal of the oscillation stabilization wait time selector is released. Oscillation stabilization wait time selector One wait time is selected from the four kinds of oscillation stabilization wait time for the main clock created by the timebase timer and the oscillation stabilization wait time for the subclock created by the watch prescaler for the clock mode, standby mode, and reset and is output as the clock supply stop signal to CPU. System clock control register (SYCC) The selection of the clock mode and main clock speed is performed, and the selection and state confirmation of the oscillation stabilization wait time of the main clock is performed. Standby control register (STBC) The transition from normal operation (RUN) to standby mode, pin state settings in stop mode or watch mode, and software reset are performed. This circuit stops oscillation in main stop mode and 68 3.6 Clock 3.6.3 System Clock Control Register (SYCC) The system clock control register (SYCC) is used to switch the main clock and the subclock, to select the speed of the main clock, and to select the oscillation stabilization wait time. I Structure of the System Clock Control Register (SYCC) Figure 3.6-5 Structure of the System Clock Control Register (SYCC) Address 0 0 0 7H bit7 SCM R bit6 bit5 WT2 R/W bit4 bit3 bit2 SCS R/W bit1 CS1 R/W bit0 CS0 R/W Initial value X-1MM100B WT1 WT0 R/W R/W CS1 CS0 0 0 1 1 SCS 0 1 0 1 0 1 Main clock speed select bit Instruction cycle (for FCH = 12.5 MHz) 64/FCH (5.12 s) 16/FCH (1.28 s) 8/FCH (0.64 s) 4/FCH (0.32 s) System clock select bit Select the subclock mode (32 kHz) Select the main clock mode Oscillation stabilization wait time select bit Main clock oscillation stabilization wait time by timebase timer output (for FCH = 12.5 MHz) Setting prohibited About 212 / FCH (about 1.31 ms) About 216 / FCH (about 10.5 ms) About 218 / FCH (about 20.97 ms) Setting prohibited "1" is always written into this bit. WT1 WT0 0 0 1 1 WT2 1 0 1 0 1 R/W R X M : Read/write enabled : Read only : Unused : Undefined : Defined by option settings : Initial value System clock monitor bit SCM 0 Subclock (The main clock is stopped or waiting for oscillation stabilization) Main clock 1 FCH: Main clock oscillation 69 CHAPTER 3 CPU Table 3.6-2 Explanation of the Functions of Each Bit of the System Clock Control Register (SYCC) Bit name * * SCM: System clock monitor bit Function Bit to check the current clock mode (operating clock) If the bit is "0", the system is operating in subclock mode (The main clock is stopped or waiting for oscillation stabilization to make a transition to the main clock mode). * If the bit is "1", the system is operating in main clock mode. Reference: This bit is read-only. Write operation to this bit has no significance and does not affect operations. * * * * The read value is undefined. Writing has no effect on operation. "1" is always written into this bit. Bit 7 Bit 6 Bit 5 Unused bits WT2 Bit 4 Bit 3 WT1, WT0: Oscillation stabilization wait time select bits Bits to select the oscillation stabilization wait time of the main clock * The oscillation stabilization wait time selected by these bits is taken when making a transition from the subclock mode to the main clock mode, or returning to normal operation from the main stop mode by an external interrupt. * The initial values of these bits are selected by option settings. Thus, if an oscillation stabilization wait time is taken for a reset, the oscillation stabilization wait time selected by option settings is taken. Note: Do not rewrite these bits simultaneously when switching from the subclock to the main clock (SCS=1 --> 0). Before rewriting the bits, check that the oscillation stabilization is not waited upon using the SCM bit. * * Bit to specify the clock mode A transition from the main clock mode to the subclock mode is caused by writing "0" into this bit. * If "1" is written into this bit, the transition from the subclock mode to the main clock mode occurs after taking the oscillation stabilization wait time set by the WT1 and WT0 bits. Note: If the single clock system option is selected, this bit has no significance. Set always "1". * * Bit to select the clock speed in main clock mode. Four different speeds of the operating clock can be selected for CPU and each peripheral function (gear function). However, the operating clock of the timebase timer and watch prescaler is not affected by these bits. Bit 2 SCS: System clock select bit Bit 1 Bit 0 CS1, CS0: Main clock speed select bits 70 3.6 Clock I Instruction Cycle (tinst) The instruction cycle (minimum execution time) can be selected from the 1/4, 1/8, 1/16, or 1/64 of the main clock and the divide-by-two of the subclock (32.768 kHz) using the system clock select bit (SYCC:SCS) and main clock speed select bits (SYCC:CS1, CS0) of the SYCC register. The instruction cycle at the maximum speed (SYCC: SCS=1, CS1, CS0=11B) in main clock mode is 4/FCH = about 0.32 s if the main clock oscillation (FCH) is 12.5 MHz. The instruction cycle in subclock mode (SCS=0) is 2/FCL = about 61.0 s if the subclock oscillation (FCL) is 32.768 kHz. 71 CHAPTER 3 CPU 3.6.4 Clock Modes The main clock mode and subclock mode are available as the clock mode. In main clock mode, the main clock is the main operating clock. The speed of the main clock can be switched by selecting from four kinds of clocks created by dividing its oscillation (gear function). In subclock mode, the oscillation of the man clock is stopped and the subclock alone becomes the operating clock. I Operating State of the Clock Mode Table 3.6-3 Operating State of the Clock Mode Clock mode Main clock speed SYCC register (SYCC: CS1, CS0) Standby mode Clock generation Main Sub CPU Operation clock in each section timebase timer Each peripheral watch prescaler Release source of standby mode (other than resets) Various interrupt requests External interrupt Various interrupt requests External interrupt Various interrupt requests External interrupt Various interrupt requests External interrupt Various interrupt requests External interrupt External interrupt, watch interrupt RUN Oscillation (1.1) High speed FCH/4 FCH/2 Oscillation Stop Stop FCH/8 Oscillation FCH/2 Oscillation Stop Stop FCH/16 Oscillation FCH/2 Oscillation Stop Stop FCH/64 Oscillation FCH/2 Oscillation Stop Stop FCL Oscillation Stop Stop Stop Stop Oscillation Stop Stop Stop Stop FCH/64 FCL Stop Stop FCH/16 FCL Stop Stop FCH/8 FCL Stop Stop FCH/4 FCL Sleep Stop RUN (1.0) Main clock mode (0.1) Sleep Stop RUN Sleep Stop RUN (0.0) Low speed Sleep Stop RUN Sleep (*1) Stop FCL FCL Subclock mode - Stop Watch mode Stop Stop FCL (*1) Stop FCH: Main clock oscillation FCL: Subclock oscillation *1: Since the timebase timer is operated by the main clock, it stops operation in subclock mode. In each clock mode, a transition can be made to the standby mode corresponding to each mode. For the standby mode, see Section 3.7 "Standby Mode (Low Power Consumption)". 72 3.6 Clock I Gear Function (Function for Switching the Speed of the Main Clock) Four different main clock speeds can be selected by writing "00B" to "11B" into the main clock speed select bits (SYCC: CS1, CS0) of the system clock control register. CPU and each peripheral circuit operate at the switched main clock speed. However, the timebase timer and watch prescaler are not affected by the gear function. By reducing the main clock speed, power consumption can be reduced. I Operation in Main Clock Mode In normal operation in main clock mode (main RUN mode), both the main clock and subclock oscillate. The watch prescaler is operated by the subclock, whereas CPU, the timebase timer, and other peripheral circuits are operated by the main clock. The speed of the main clock can be switched to a value other than that of the timebase timer during operation in main clock mode (gear function). A transition to the main sleep mode or main stop mode is enabled by specifying the standby mode. Operation always starts in main RUN mode regardless of the type of reset that occurs (release by the reset in each operation mode). Transition from the main clock mode to the subclock mode A transition from the main clock mode to the subclock mode is caused by writing "0" into the system clock select bit (SYCC: SCS) of the system clock control register. The current operating clock can be checked by reading the system clock monitor bit (SYCC: SCM) of the system clock control register. Note: To make a transition to the subclock mode, for example, just after power-on, it is necessary to wait at least the subclock oscillation stabilization wait time created by the watch prescaler using software before making a transition. 73 CHAPTER 3 CPU I Operation in Subclock Mode In normal operation in subclock mode (sub RUN mode), the oscillation of the main clock is stopped and only the subclock is used for operation. By operating in a low speed clock, power consumption can be reduced. All functions other than the timebase timer operate as in the main clock mode. A transition to the sub-sleep mode, sub-stop mode, or watch mode is enabled by specifying the standby mode during operation in subclock mode. Return from the subclock mode to the main clock mode A return from the subclock mode to the main clock mode is caused by writing "1" into the system clock select bit (SYCC: SCS) of the system clock control register. However, operation in main clock mode starts only after the oscillation stabilization wait time of the main clock passes. The oscillation stabilization wait time can be selected from three different wait times using the oscillation stabilization wait time select bits (SYCC: WT1, WT0) of the system clock control register. Note: Do not rewrite the oscillation stabilization wait time select bits (SYCC: WT1, WT0) simultaneously by switching from the subclock to the main clock. Also, do not rewrite the bits when the oscillation stabilization of the main clock is waited upon. In such cases, rewrite the bits after checking that the operating clock has been switched to the main clock (SYCC: SCM=1) by the system clock monitor bit. After a power-on, if a power-on reset is generated, the oscillation stabilization wait time is allowed to elapse. For return to the main clock mode from the subclock mode using a reset, the oscillation stabilization wait time is allowed to elapse. 74 3.6 Clock 3.6.5 Oscillation Stabilization Wait Time If the main clock is operated in main RUN mode from a state in which the main clock is stopped, for example, when the power is turned on, or in main stop mode or subclock mode, it is necessary to take the oscillation stabilization wait time of the main clock. Likewise, the oscillation stabilization wait time of the subclock is needed in sub-stop mode because the oscillation of the subclock is stopped. I Oscillation Stabilization Wait Time Ceramic and crystal resonators generally take several ms to several dozens of ms to oscillate steadily in natural frequency after starting oscillation. Thus, CPU operation must be prohibited just after starting oscillation. The clock should be supplied to CPU only when the oscillation is sufficiently stable after the passage of the oscillation stabilization wait time. Since the time needed to stabilize oscillation is dependent on the type (such as the crystal and ceramic) of resonator connected to the oscillator (clock generator), an oscillation stabilization wait time appropriate to the resonator to be used must be selected. Figure 3.6-6 "Oscillator Operation after Oscillation Starts" shows an oscillator operation just after the oscillation starts. Figure 3.6-6 Oscillator Operation after Oscillation Starts Resonator oscillation time Oscillation stabilization wait time ( Normal operation, return from the stop mode, or reset operation ) X1 Oscillation start Oscillation stable I Oscillation Stabilization Wait Time of the Main Clock To start operation in main clock mode from a state in which the main clock is stopped, the oscillation stabilization wait time of the main clock must be taken. The oscillation stabilization wait time of the main clock is a time interval counted from when the counter of the timebase timer is cleared until the overflow of the specified bit occurs. Oscillation stabilization wait time during operation One of the four kinds of oscillation stabilization wait time when returning to the main RUN mode from the main stop mode by an external reset or when making a transition from the subclock mode to the main clock mode can be selected using the oscillation stabilization wait time select bits (SYCC: WT1, WT0) of the system clock control register. 75 CHAPTER 3 CPU Oscillation stabilization wait time during reset The oscillation stabilization wait time during reset (SYCC: initial value of WT1 and WT0) can be selected by option settings. The oscillation stabilization wait time is allowed to elapse when the stop mode is canceled by two or more resets in subclock mode, a power-on reset, or external reset. Table 3.6-4 "Operation Start Conditions and Oscillation Stabilization Wait Time of the Main Clock Mode" lists the relations between the operation start conditions and oscillation stabilization wait time of the main clock mode. Table 3.6-4 Operation Start Conditions and Oscillation Stabilization Wait Time of the Main Clock Mode During subclock mode Start conditions for main clock operation Oscillation stabilization wait time selection During power-on External reset Software reset and watchdog timer Release from main stop mode External reset External interrupt Transition from the subclock mode to the main clock mode (SYCC: SCS (*1) =1) Option settings SYCC:WT1, WT0 (*2) *1: System clock select bit of the system clock control register *2: Oscillation stabilization wait time select bit of the system clock control register I Oscillation Stabilization Wait Time of the Subclock A certain oscillation stabilization wait time (215/FCL, FCL: subclock oscillation) of the subclock must be taken when returning to the sub RUN mode (subclock oscillation is started) from the sub-stop mode (state in which oscillation of the subclock is stopped) by an external reset. The oscillation stabilization wait time of the subclock is a time interval from the start of operation in a state in which the watch prescaler is cleared until an overflow occurs. Since the oscillation stabilization wait time of the subclock is needed during power-on, wait at least the subclock oscillation stabilization wait time using software to make a transition to the subclock mode after power-on. 76 3.7 Standby Mode (Low Power Consumption) 3.7 Standby Mode (Low Power Consumption) The sleep mode, stop mode, and watch mode are available as the standby mode. A transition to the standby mode is caused by settings of the standby control register (STBC) both in main clock mode and subclock mode. In main clock mode, transitions to the sleep mode and stop mode are possible. In subclock mode, transitions to the sleep mode, stop mode, and watch mode are possible. Power consumption can be reduced by stopping operations of CPU and peripheral functions using the standby mode. This section describes the relations between the standby mode and clock mode, and the operating states of each section in standby mode. I Standby Mode In clock mode, power consumption is reduced by reducing the operating clock of CPU and peripheral circuits such as switching of the main clock and subclock or switching of the main clock speed (gear function). In standby mode, however, power consumption is reduced by the clock supply stop (sleep mode) to CPU by the clock controller, clock supply stop (watch mode) to CPU and peripheral circuits, or stop of the oscillation itself (stop mode). Main sleep mode The main sleep mode is a mode which stops operations of CPU and the watchdog timer. Peripheral functions excluding the watch prescaler operate on the main clock (Part of the functions can operate on the subclock). Sub-sleep mode The sub-sleep mode is a mode which stops the main clock oscillation, CPU operations, and watchdog timer and timebase timer operations. Peripheral functions operate on the subclock. Main stop mode The main stop mode is a mode which stops operations of CPU and peripheral functions. The main clock stops oscillation, but the subclock continues oscillation. In this mode, all functions are stopped excluding external interrupts, count operations of the watch prescaler, and some of the functions that run with the subclock. Sub-stop mode The sub-stop mode is a mode which stops all functions other than external interrupts. The main clock and the subclock both stop oscillation. Watch mode The watch mode is a mode a transition to which is possible only from the subclock mode. All functions other than the watch prescaler (watch interrupt), external interrupts, and part of the functions operating on the subclock stop. 77 CHAPTER 3 CPU 3.7.1 Operating State in Standby Mode This section describes the operating states of CPU and peripheral functions in standby mode. I Operating State in Standby Mode Table 3.7-1 The Operating States of CPU and Peripheral Functions in Standby Mode Function RUN Main clock Subclock Instruction CPU ROM Operating RAM I/O port Watch prescaler Timebase timer 16-bit timer/counter 8-bit serial I/O UART I2C bus interface Peripheral UART/SIO functions 8-bit PWM timer A/D converter External interrupt 1, 2 12-bit PPG Watchdog timer PWC timer 6-bit PPG Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Retained Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Stopped Operating Operating Retained Operating(*1) Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Operating Operating Operating Stopped Operating Operating Operating Operating Operating Operating Operating Operating Retained Operating Stopped Operating Operating Operating Operating Operating Operating Operating Operating Retained Retained Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Operating Stopped Stopped Stopped Stopped Retained Operating Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Operating Operating(*2) Stopped Stopped Stopped Retained Retained Operating Retained Retained Retained Operating Operating Operating Main clock mode Sleep Operating Operating Stopped Stop Stopped Operating Stopped RUN Stopped Operating Operating Subclock mode Sleep Stopped Operating Stopped Stop Stopped Stopped Stopped Watch Stopped Operating Stopped Operating(*2) Operating(*2) Operating(*2) Stopped Stopped Operating(*2) Operating Stopped Operating Operating(*2) Operating(*2) Operating(*2) *1: The watch prescaler carries out the count operation, but no watch interrupt occurs. *2: This function can operate when the watch prescaler output is selected as the operating clock. Pin state in standby mode Most I/O pins can, independent of the clock mode, retain the state just before transition to the stop or watch mode or can be put into high impedance using the pin state designate bit (STBC: SPL) of the standby control register. For details on pin states in standby mode, see Appendix F "Pin Statuses of the MB89530/530H/ 530A Series " 78 3.7 Standby Mode (Low Power Consumption) 3.7.2 Sleep Mode This section describes the operations in sleep mode. I Operations in Sleep Mode Transition to the sleep mode The sleep mode is a mode which stops the operating clock of CPU. CPU stops by retaining the contents of the registers and RAM just before transition to the sleep mode, but peripheral functions other than the watchdog timer continue their operations. However, since the main clock oscillation stops in subclock mode, the timebase timer which uses the divide-by-two of the main clock oscillation as its count clock does not operate. A transition to the sleep mode is caused by writing "1" into the sleep bit (STBC: SLP) of the standby control register. If an interrupt has occurred when "1" is written into the SLP bit, the write operation is ignored and execution of instructions continues without transition to the sleep mode (no transition to sleep mode after the interrupt). Sleep mode release The sleep mode is released by a reset or an interrupt from the peripheral functions. If a reset occurs in sub-sleep mode, the reset operation is performed after taking the oscillation stabilization wait time of the main clock. Pin states are initialized by the reset operation. If an interrupt request whose interrupt level is higher than "11" comes from a peripheral function or external interrupt circuit, the sleep mode is released regardless of the interrupt enable flag (CCR: I) or interrupt level bit (CCR: IL1, 0) of CPU. After the release, normal interrupt operations are performed. If an interrupt can be accepted, interrupt processing is performed. If no interrupt can be accepted, processing starts with the instruction following the instruction executed just before the transition to sleep mode. 79 CHAPTER 3 CPU 3.7.3 Stop Mode This section describes the operations in stop mode. I Operations in Stop Mode Transition to the stop mode The stop mode is a mode which stops the oscillation. Contents of the registers and RAM just before transition to the stop mode are retained and most functions are stopped. In main clock mode, the main clock stops the oscillation, but the subclock continues the oscillation. Thus, though the count operation of the watch prescaler and part of the functions operating on the subclock continue their operations, other peripheral functions and CPU, excluding the external interrupt circuits, stop operations. In subclock mode, both the main clock and subclock stop oscillation, and all functions other than the external interrupt circuits stop their functions. Thus, data can be retained with minimum power consumption. A transition to the stop mode is caused by writing "1" into the stop bit (STBC: STP) of the standby control register. At this time, if the pin state designate bit (STBC: SPL) is "0", the states of external pins are retained. If the bit is "1", external pins are put into high impedance. If an interrupt request has occurred when "1" is written into the STP bit, the write operation is ignored and execution of instructions continues without making a transition to the stop mode (No transition to the stop mode occurs even after interrupt processing is completed). To make a transition to the stop mode in the main clock mode, prohibit (TBTC: TBIE=0) the interrupt request output of the timebase timer if necessary. Likewise, to make a transition to the stop mode in subclock mode, prohibit (WPCR: WIE=0) the watch interrupt request output of the watch prescaler. Stop mode release The stop mode can be released by a reset or external interrupt. If a reset occurs in stop mode, the reset operation is performed after taking the oscillation stabilization wait time of the main clock. Pin states are initialized by the reset. If an interrupt request whose interrupt level is higher than "11" comes from an external interrupt circuit in stop mode, the stop mode is released regardless of the interrupt enable flag (CCR: I) and interrupt level bits (CCR: IL1, 0) of CPU. Since peripheral functions are stopped in stop mode, no interrupt requests other than external interrupts occur. Though the watch prescaler operates in main stop mode, no watch interrupts occur. If the stop mode is released, a normal interrupt operation is performed following the passage of the oscillation stabilization wait time. If the interrupt is accepted, interrupt processing is performed. If the interrupt is not accepted, execution starts with the instruction following the instruction executed just before transition to the stop mode. If the stop mode is released by an external interrupt, part of the peripheral functions restarts halfway through their operations. Thus, for example, the first interval time of the interval timer function is undefined. Each peripheral function should be initialized after returning from the stop mode. 80 3.7 Standby Mode (Low Power Consumption) Note: The stop mode release by an interrupt can only be caused by an interrupt request of the external interrupt circuits. 81 CHAPTER 3 CPU 3.7.4 Watch Mode This section describes the operations in watch mode. I Operations in watch mode Transition to the watch mode The watch mode is a mode which stops the operating clock of CPU and main peripheral circuits. A transition to the watch mode is only possible from the subclock mode (The main clock oscillation is stopped). Contents of the registers and RAM just before transition to the watch mode are retained and most functions other than the watch prescaler (watch interrupt), external interrupt circuits, and part of the functions operating on the subclock are stopped. Thus, data can be retained with very low power consumption. A transition to the watch mode is caused by writing "1" into the watch bit (STBC: TMD) of the standby control register when the subclock mode is set by the system clock select bit of the system clock control register. If the pin state designate bit (STBC: SPL) of the standby control register during transition to the watch mode is "0", the external pin states are retained. If the bit is "1", external pins are put into high impedance. If an interrupt request has occurred when "1" is written into the TMD bit, the write operation is ignored and execution of instructions continues without making a transition to the watch mode (No transition to the watch mode occurs even after interrupt processing is completed). Watch mode release The watch mode can be released by a reset, watch interrupt, or external interrupt. If a reset occurs in watch mode, the reset operation is performed after taking the oscillation stabilization wait time of the main clock. Pin states are initialized by the reset. If an interrupt request whose interrupt level is higher than "11" comes from the watch prescaler or an external interrupt circuit in watch mode, the watch mode is released regardless of the interrupt enable flag (CCR: I) and interrupt level bits (CCR: IL1, 0) of CPU. Since most peripheral functions other than the watch prescaler are stopped in watch mode, no interrupt requests other than watch interrupts and external interrupts occur. After releasing the watch mode, a normal interrupt operation is performed. If the interrupt is accepted, interrupt processing is performed. If the interrupt is not accepted, execution starts with the instruction following the instruction executed just before transition to the watch mode. If the watch mode is released, part of the peripheral functions restarts halfway through their operations. Thus, for example, the first interval time of the interval timer function is undefined. Each peripheral function should be initialized after returning from the watch mode. 82 3.7 Standby Mode (Low Power Consumption) 3.7.5 Standby Control Register (STBC) The standby control register (STBC) is used to make a transition to the sleep mode/ stop mode/watch mode, set the pin states in watch mode, and reset software. I Standby Control Register (STBC) Figure 3.7-1 Standby Control Register (STBC) Address 0 0 0 8H bit7 STP R/W bit6 SLP R/W bit5 SPL R/W bit4 bit3 bit2 bit1 bit0 Initial value 00010---B RST TMD W R/W Watch bit TMD Valid only in subclock mode (SYCC: SCS=0) Read 0 1 "0" is always read Write No effects on operations Transition to the watch mode Software reset bit Read Write Generation of the reset signal of four instruction cycles No effects on operations RST 0 1 "1" is always read Pin state designate bit SPL 0 Retain external pin states just before if in stop mode 1 Put external pins into high impedance if in stop mode Sleep mode Read "0" is always read Write No effects on operations Transition to the sleep mode Stop bit Read "0" is always read Write No effects on operations Transition to the stop mode SLP 0 1 STP R/W : Read/write enabled W : Write only : Unused : Initial value 0 1 83 CHAPTER 3 CPU Table 3.7-2 Explanation of the Functions of Each Bit of the Standby Control Register (STBC) Bit name * * * * * * * * * * SPL: Pin state designate bit Function Bit to specify the transition to the stop mode A transition to the stop mode is caused by writing "1" into this bit. Operations are not affected if "0" is written into this bit. When this bit is read, "0" is always read. Bit to specify the transition to the sleep mode A transition to the sleep mode is caused by writing "1" into this bit. Operations are not affected if "0" is written into this bit. When this bit is read, "0" is always read. Bit to specify the external pin state in stop mode and watch mode If "0" is written into this bit, the external pin state (level) when making a transition to the stop or watch mode is retained. If "1" is written into this bit, the external pins are put into high impedance when making a transition to the stop or watch mode (The pin for which "pull-up resistor available" is selected in the pull-up setting register is set to the "H" level.). This bit is set to "0" by a reset. Bit 7 STP: Stop bit Bit 6 SLP: Sleep bit Bit 5 * * * * Bit 4 RST: Software reset bit Bit to specify the software reset An internal reset source in four instruction cycles caused by writing "0" into this bit. * Operations are not affected if "1" is written into this bit. * When this bit is read, "1" is always read. Reference: If the software reset is triggered in subclock mode, operation starts in main clock mode after taking the oscillation stabilization wait time. Thus, the reset signal is output during oscillation stabilization wait time. * * Bit to specify the transition to the watch mode Write operation to this bit is valid only in subclock mode (SYCC: SCS=0). A transition to the watch mode is caused by writing "1" into this bit. Operations are not affected if "0" is written into this bit. When this bit is read, "0" is always read. The read value is undefined. Writing has no effect on operation. Bit 3 TMD: Watch bit * * * Bit 2 Bit 1 Bit 0 Unused bits * * 84 3.7 Standby Mode (Low Power Consumption) 3.7.6 State Transition Diagram 1 (Power-On Reset and Dual Clock System) This section shows a state transition diagram when a power-on reset and the dual clock system are used. I State Transition Diagram 1 (Power-On Reset and Dual Clock System) Figure 3.7-2 State Transition Diagram 1 (Dual Clock) Power-on Power-on reset Oscillation stabilization wait reset state Reset state Main clock mode Main stop state Main RUN state Main sleep state Main clock oscillation stabilization wait Subclock mode Subclock oscillation stabilization wait Sub-RUN main clock oscillation stabilization wait Sub-stop state Sub-RUN state Sub-sleep state Watch state 85 CHAPTER 3 CPU Transition and release of the clock mode (non-standby mode) Table 3.7-3 Transition and Release of the Clock Mode (Power-on Reset is Available, Dual Clock System) State transition Transition to the normal state (main RUN) in main clock mode after power-on reset [1] [2] Reset in the main RUN state Transition from the main RUN state to the sub-RUN state Return from the sub-RUN state to the main RUN state [3] [4] [5] [6] [7] Reset in the sub-RUN state [8] Transition conditions Main clock oscillation stabilization wait time end (timebase timer output) Release of reset input External reset, software reset, or watchdog reset SYCC:SCS=0(*1) SYCC:SCS=1 Main clock oscillation stabilization wait time end (SYCC: can be checked by SCM) External reset, software reset, or watchdog reset External reset, software reset, or watchdog reset SYCC: System clock control register *1: A transition to the sub-RUN just after power-on occurs after the passage of the subclock oscillation stabilization wait time. 86 3.7 Standby Mode (Low Power Consumption) Transition and release of the standby mode Table 3.7-4 Transition and Release of the Standby Mode (Power-on Reset is Available, Dual Clock System) Transition conditions State transition Main clock mode Transition to the sleep mode Release of the sleep mode [1] [2] [3] Transition to the stop mode Release of the stop mode [4] [5] [6] STBC:SLP=1 Interrupt (various types) External reset STBC:STP=1 External interrupt Main clock oscillation stabilization wait time end (timebase timer output) External reset External reset (Waiting for oscillation stabilization) Subclock mode <1> STBC:SLP=1 <2> Interrupt (various types) <3> External reset <4> STBC:STP=1 <5> External interrupt <6> Subclock oscillation stabilization wait time end (watch prescaler output) <7> External reset <8> External reset (Waiting for oscillation stabilization) <9> STBC:TMD=1(*1) <10> External interrupt or watch interrupt <11> External reset STBC: Standby control register *1: A transition to the watch mode is only possible from the sub-RUN state (SYCC: SCS=0). Note: Since CPU and the watchdog timer are stopped in standby mode, no software reset and watchdog reset occur. When a single clock system is used, a transition to the subclock mode is prohibited. If a transition to the subclock mode occurs, CPU stops and there is no other way to return other than resetting. [7] [8] Transition to the watch mode Release of the watch mode - 87 CHAPTER 3 CPU 3.7.7 State Transition Diagram 2 (Single Clock System Option) This section shows two state transition diagrams for the single clock system option having a power-on reset. If a single clock system is used, the subclock mode and watch mode are not available. I State Transition Diagram 2 (Single Clock System Option) Figure 3.7-3 State Transition Diagram 2 Power-on Power-on reset Oscillation stabilization wait reset state [1] Reset state [2] [3] [7] [4] [1] [3] Main clock mode Main stop mode [5] [6] Main run state [2] Main sleep mode [8] Main clock oscillation stabilization wait I Transition to Ordinary State (run) and Release Table 3.7-5 Transition to Main Clock Mode Run State and Release (Single Clock System Option) State transition Transition condition Product having a power-on reset (Figure 3.7-3 "State Transition Diagram 2") Transition to ordinary state (run) after power-on Reset in the run state End of main clock oscillation stabilization wait time (Timebase timer output) Release of the reset input [3] External reset, software reset, and watchdog reset 88 3.7 Standby Mode (Low Power Consumption) I Transition to Standby Mode and Release Table 3.7-6 Transition to Standby Mode and Release (Single Clock System Option) State transition Transition condition Product having a power-on reset (Figure 3.7-3 "State Transition Diagram 2") Transition to the sleep mode Release of the sleep mode Transition to the stop mode Release of the stop mode [1] STBC:SLP=1 Interrupt External reset [4] STBC:STP=1 External interrupt End of the main clock oscillation stabilization wait time (Timebase timer output) External reset External reset (during oscillation stabilization wait) STBC: Standby control register 89 CHAPTER 3 CPU 3.7.8 Notes on Using Standby Mode A transition to the standby mode does not occur even if the standby mode is set on the standby control register (STBC) when an interrupt request has arrived from a peripheral function. When returning to a normal operation state from the standby mode caused by an interrupt, operations after the return are dependent on whether or not the interrupt request is accepted. I Transition to the Standby Mode and Interrupts When an interrupt request whose interrupt priority is higher than "11B" arrives at CPU from a peripheral function, a transition to the standby mode does not occur if "1" is written into the stop bit (STBC: STP), sleep bit (STBC: SLP) or watch bit (STBC: TMD) of the standby control register because such write operations are ignored (No transition to the standby mode occurs even after the interrupt processing is completed). This is not related to whether the interrupt is accepted by CPU. Even if CPU is processing an interrupt, a transition to the standby mode is possible if the interrupt request flag bit is cleared and there are no other interrupt requests. I Release of the Standby Mode by an Interrupt The standby mode is released if an interrupt request whose interrupt priority is higher than "11" comes from the peripheral functions in sleep mode or stop mode. This is not related to whether the interrupt is accepted by CPU. After releasing the standby mode, if the priority of the interrupt level setting register (ILR1- ILR4) corresponding to the interrupt request is higher than the interrupt level bits (CCR: IL1, IL0) of the condition code register and if the interrupt enable flag allows the interrupts (CCR: I=1), branching to an interrupt processing routine occurs. If the interrupt is not accepted, execution of the instruction following the instruction starting the standby mode is restarted. If no branching to an interrupt processing routine just after returning occurs, measures such as an interrupt prohibition are needed before setting the standby mode. 90 3.7 Standby Mode (Low Power Consumption) I Precaution in Setting the Standby Mode To set the standby mode using the standby control register (STBC), follow Table 3.7-7 "Low Power Consumption Settings by the Standby Control Register (STBC)". The priority order when "1" is written into these bits is the stop mode, watch mode, and sleep mode. However, it is preferable to set "1" to one bit at a time. Do not make a transition to the stop mode, sleep mode, and watch mode just after switching from the subclock mode to the main clock mode (SYCC: SCS=0 --> 1). Make a transition to these modes after checking that the clock monitor bit (SYCC: SCM) of the system control register is "1". However, the content written into the watch bit (STBC: TMD) is ignored during operation in main clock mode. Table 3.7-7 Low Power Consumption Settings by the Standby Control Register (STBC) STBC register Mode STP (bit 7) 0 0 0 1 I Oscillation Stabilization Wait Time Since the oscillator for oscillation is stopped in stop mode for both the main clock mode and subclock mode, it is necessary to take the oscillation stabilization wait time after the oscillator in each mode starts operation. As the oscillation stabilization wait time in main clock mode, take the oscillation stabilization wait time of the main clock created by the timebase timer (Select one from three different kinds of wait time). As the oscillation stabilization wait time in subclock mode, take the oscillation stabilization wait time of the subclock created by the watch prescaler. In main clock mode, if the selected interval time of the timebase timer is shorter than the oscillation stabilization wait time, an interval timer interrupt request may occur during oscillation stabilization wait time. Before making a transition to the stop mode in main clock mode, prohibit (TBTC: TBIE=0) the interrupt request output of the timebase timer if necessary. Likewise, a watch interrupt request may occur depending on the selected interval time of the watch prescaler. Before making a transition to the stop mode in subclock mode, prohibit (WPCR: WIE=0) the watch interrupt request output of the watch prescaler if necessary. SLP (bit 6) 0 0 1 0 TMD (bit 3) 0 1 0 0 Normal Watch Sleep Stop 91 CHAPTER 3 CPU 3.8 Memory Access Mode The operation mode for memory access of the MB89530/530H series is the single chip mode only. I Single Chip Mode The single chip mode uses only the internal RAM and ROM. Thus, CPU can access only the internal I/O area, RAM area, and ROM area (internal access). I Mode Pin (MOD0, 1) Set always "Vss" to the mode pin (MOD0 and MOD1). The mode data and reset vector are read from the internal ROM during reset. Do not change the settings of the mode pin after the reset operation (during operation) is completed. Table 3.8-1 "Settings of the Mode Pin" lists the settings of the mode pin. Table 3.8-1 Settings of the Mode Pin Pin state Contents MOD1 Vss Vss Vcc Vcc I Mode Data Set always 00H as the mode data in the internal ROM to select the single chip mode. Figure 3.8-1 Structure of the Mode Data Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 F F F DH MOD0 Vss Vcc Vss Vcc Setting prohibited The mode data and reset vector are read from the internal ROM Data 00H Operation Single chip mode selection Except 00H Reserved. Do not set here. 92 3.8 Memory Access Mode I Selection of the Memory Access Mode Only the single chip mode can be selected. Table 3.8-2 "Mode pins and mode data" lists the mode pins and mode data. Table 3.8-2 Mode Pins and Mode Data Memory access mode Single chip mode Other modes Mode pin (MOD0, 1) Vss Setting prohibited Mode data 00H Setting prohibited Figure 3.8-2 "Memory Access Selection Operation" shows the Operation of Memory Access Selection. Figure 3.8-2 Memory Access Selection Operation Reset source occurred Setting prohibited Mode pin check Others Mode pin (MODA) Single chip mode Mode data is read from the internal ROM I/O pin, high impedance Reset source release wait (external reset or oscillation stabilization wait time) Reset state Mode fetch Mode data and reset vector fetch from the internal ROM Mode data check Setting prohibited Others Mode data Single chip mode (00H) I/O pin function settings during program execution (RUN) Input/output settings of each I/O pin by the port direction register (DDR) I/O pins can be used as ports 93 CHAPTER 3 CPU 94 CHAPTER 4 I/O PORTS This chapter describes the functions and operation of the I/O ports. 4.1 "Overview of the I/O Ports" 4.2 "Port 0 and Port 1" 4.3 "Port 2" 4.4 "Port 3" 4.5 "Port 4" 4.6 "Port 5" 4.7 "Port 6" 4.8 "Sample I/O Port Program" 95 CHAPTER 4 I/O PORTS 4.1 Overview of the I/O Ports Fifty-three general-purpose I/O ports are provided. Each of the ports can be used for peripheral devices (as pins for peripheral functions). I Functions of the I/O ports The I/O ports output data received from the CPU to their I/O pins and input signals received at their I/O pins into the CPU through the port data registers (PDR). Some of the I/O ports provide a port direction register (DDR) to allow the direction (I/O) of each bit on the I/O pins to be specified. The following shows the function each port and peripheral device also supported by the port: * * * * * Port 0: General-purpose I/O port Port 1: General-purpose I/O port Port 2: General-purpose I/O port/Peripheral device (PWCK, 12-bit PPG01, 12-bit PPG02) also supported Port 3: General-purpose I/O port/Peripheral device (PPG03/MCO, SCK1(UCK1)/LMCO, SO1(UO1), SI1(UI1), PTO2, PWC, WTO, PTO1) also supported Port 4: General-purpose I/O port/Peripheral device (INT20/EC, INT21/SCK2, INT22/SO2/ SDA(*1), INT23/SI2/SCL(*1), INT24/UCK2, INT25/UO2, INT26/UI2, INT27/ADST) also supported The functions of SDA and SCL (I2C) cannot be used on the MB89535A, MB89537, MB89537H, MB89537A, MB89538, MB89538H, and MB89538A. * * Port 5: N-channel open-drain output-only port/Peripheral device (ADC input 8 channels) also supported Port 6: CMOS input-only port/Peripheral device (X1A, INT13/X0A, INT10 to INT12) also supported *1 N-channel open-drain pin Table 4.1-1 "List of the functions of each port" lists the functions of each port, and Table 4.1-2 "List of the registers on each port" lists the registers of each port. 96 4.1 Overview of the I/O Ports Table 4.1-1 List of the functions of each port Port name Pin name Input format Output format Function Generalpurpose I/O port Generalpurpose I/O port CMOS push-pull Peripheral device Generalpurpose I/O port Peripheral device CMOS push-pull (P42/INT22/ SO2/SDA and P43/ INT23/SI2/ SCL are Nchannel opendrains.) Generalpurpose I/O port bit7 P07 P17 bit6 P06 P16 bit5 P05 P15 bit4 P04 P14 bit3 P03 P13 bit2 P02 P12 bit1 P01 P11 bit0 P00 P10 Port 0 P00 to P07 CMOS Port 1 P10 to P17 P27 P26 P25 P24 P23 P22 P21 P20 P20/PWCK Port 2 to P27 - - - - - PPG02 PPG01 PWCK P37 P36 P35 P34 P33 P32 P31 P30 P30/PPG03/ Port 3 MC to P37/ CMOS PT01 (Resources are hysteretic.) PTO1 WTO PWC PTO2 SI1 (UI1) SO1 (UO1) SCK1 PPG03 (UCK1) /MCO /LMCO P47 P46 P45 P44 P43 P42 P41 P40 P40/INT4/ Port 4 EC to P47/ INT11/ADST Peripheral device INT27/ ADST INT26/ UI2 INT25/ UO2 INT24/ UCK2 INT23/ INT22/ INT21/ SI2/ SO2/ (*1) SDA(*1) SCK2 SCL INT20/ EC P50/AN0 to Port 5 P57/AN7 Analog input N-channel open-drain Output-only port Input to A/D converter Input-only port Peripheral device P57 P56 P55 P54 P53 P52 P51 P50 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Port 6 P60/INT0 to P64/X1A CMOS (Resources are hysteretic.) X1A: CMOS push-pull - - - P64 X1A(*2) P63 INT13/ X0A P62 P61 P60 - - - INT12 INT11 INT10 *1 Operates with N-channel open-drain output. *2 Operates with CMOS output. 97 CHAPTER 4 I/O PORTS Table 4.1-2 List of the registers on each port Register name Port 0 data register (PDR0) Port 0 direction register (DDR0) Port 0 pull-up resistor register (PURR0) Port 1 data register (PDR1) Port 1 direction register (DDR1) Port 1 pull-up resistor register (PURR1) Port 2 data register (PDR2) Port 2 direction register (DDR2) Port 2 pull-up resistor register (PURR2) Port 3 data register (PDR3) Port 3 direction register (DDR3) Port 3 pull-up resistor register (PURR3) Port 4 data register (PDR4) Port 4 direction register (DDR4) Port 4 pull-up resistor register (PURR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 6 pull-up resistor register (PURR6) Read/Write R/W W(*1) R/W R/W W(*1) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Address 0000H 0001H 0072H 0002H 0003H 0073H 000CH 000DH 0074H 000EH 000FH 0075H 0010H 0011H 0076H 0012H 0013H 0079H Initial value XXXXXXXXB 00000000B 11111111B XXXXXXXXB 00000000B 11111111B XXXXXXXXB 00000000B 11111111B XXXXXXXXB 00000000B 11111111B XXXXXXXXB 0000--00B 1111--11B 11111111B XXXXXXXXB ---11111B *1 DDR0 and DDR1 do not allow bit operation instructions to be used. R/W: Readable/Writable R: Read-only W: Write-only X: Unfixed -: Unused 98 4.2 Port 0 and Port 1 4.2 Port 0 and Port 1 Port 0 and Port 1 are general-purpose I/O ports. This section mainly describes the functions of the general-purpose I/O ports. This section also describes the configurations, pins, and block diagram of the pins, and registers related to Port 0 and Port 1. I Configurations of Port 0 and Port 1 Port 0 and Port 1 consist of the following four elements, respectively: Port 0 * * * * General-purpose I/O-exclusive pins (P00 to P07) Port 0 data register (PDR0) Port 0 direction register (DDR0) Port 0 pull-up resistor control register (PURR0) Port 1 * * * * General-purpose I/O-exclusive pins (P10 to P17) Port 1 data register (PDR1) Port 1 direction register (DDR1) Port 1 pull-up resistor control register (PURR1) I Pins of Port 0 and Port 1 Port 0 and Port 1 have eight CMOS I/O pins, respectively. Table 4.2-1 "Pins of Port 0 and Port 1" shows the pins of Port 0 and Port 1. Table 4.2-1 Pins of Port 0 and Port 1 I/O format Port name Port 0 Port 1 Pin name P00 to P07 General-purpose I/O P10 to P17 CMOS CMOS D Function Input Output Circuit type For details of the circuit types, see Section 1.7 "Explanations of the Pin Functions." 99 CHAPTER 4 I/O PORTS I Block diagram of Port 0 and Port 1 Figure 4.2-1 Block diagram of Port 0 and Port 1 pins PDR (port data register) Stop/watch mode (SPL=1) PDR read Port 0/1 pull-up resistor control register Internal data bus Pull-up resistor Approx. 50 k Pch PDR read (for bit operation instructions) Output latch PDR write Pch Pin DDR (Port direction register) Nch DDR write Stop/watch mode (SPL=1) SPL: Pin status specification bit of the standby control register (STBC) I Registers of Port 0 and Port 1: PDR0 and DDR0 Port 0 has three related registers, PDR0, DDR0, and PURR0. Port 1 has three related registers, PDR1, DDR1, and PURR1. Each bit of the registers corresponds to a pin of Port 0 and Port 1. Table 4.2-2 "Correspondence between bits and pins of the Port 0 and Port 1 registers" shows the correspondence between bits and pins of the Port 0 and Port 1 registers. Table 4.2-2 Correspondence between bits and pins of the Port 0 and Port 1 registers Port name Port 0 Corresponding pin PDR1,DDR1,PURR1 Port 1 Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10 P07 bit7 P06 bit6 P05 bit5 P04 bit4 P03 bit3 P02 bit2 P01 bit1 P00 bit0 Correspondence between bits and pins of the related registers PDR0,DDR0,PURR0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 100 4.2 Port 0 and Port 1 4.2.1 Registers of Port 0 and Port 1 (PDR0, DDR0, PURR0, PDR1, DDR1, PURR1) This section describes the registers related to Port 0 and Port 1. I Functions of the Port 0 and Port 1 registers Port 0 and Port 1 data registers (PDR0 and PDR1) The PDR0 and PDR1 registers indicate the states of the pins. Therefore, pins which have been set up for output allow for a value (0 or 1) which is the same as that of the output latch to be read. However, those set up for input do not allow for a value of the output latch to be read. Port 0 and Port 1 direction registers (DDR0 and DDR1) The DDR0 and DDR1 registers set the direction (I/O) of each pin by bit. Specifying 1 to the bit of a pin sets it up for output, and specifying 0 sets it up for input. Reference: The bit operation commands SETB and CLRB executed for registers other than the DDR0 or DDR1 register read states of output latches (not pins). Thus, executing bit operation instructions does not change the states of output latches related to bits not being operated. Note: The DDR0 and DDR1 registers are write-only: Do not use the bit operation instructions SETB and CLRB. Table 4.2-3 "Functions of the Port 0 and Port 1 registers" shows the functions of the Port 0 and Port 1 registers. Table 4.2-3 Functions of the Port 0 and Port 1 registers Register name Port 0 data register (PDR0) Value 0 1 Reading The pin is Level L. The pin is Level H. Writing For pins set up for output, Level L is output to the pins. R/W For pins set up for output, Level H is output to the pins. Operation of the output transistors is disabled, and the pins are set up for input. W 1 Unreadable Operation of the output transistors is enabled, and the pins are set up for output. For pins set up for output, Level L is output to the pins. R/W 1 The pin is Level H. For pins set up for output, Level H is output to the pins. 0002H XXXXXXXXB 0001H 00000000B 0000H XXXXXXXXB Read/ Write Address Initial value 0 Port 0 direction register (DDR0) Unreadable Port 1 data register (PDR1) 0 The pin is Level L. 101 CHAPTER 4 I/O PORTS Table 4.2-3 Functions of the Port 0 and Port 1 registers (Continued) Register name Value Reading Writing Operation of the output transistors is disabled, and the pins are set up for input. W Operation of the output transistors is enabled, and the pins are set up for output. 0003H 00000000B Read/ Write Address Initial value 0 Port 1 direction register (DDR1) 1 R/W: Readable/Writable W: Write-only X: Not specified Unreadable (write-only) I Port 0 and Port 1 pull-up resistor control registers (PURR0 and PURR1) Each Port 0 and Port 1 pin allows a pull-up resistor to be used. Write a pull-up resistor setting to each bit of the Port 0 and Port 1 pull-up resistor control registers. Enabling pull-up resistors in stop mode or watch mode (STBC:SPL=1) using the Port 0 and Port 1 pull-up resistor control registers does not set the pins to high impedance but rather to Level H (pulled up). However, during a reset, pull-up of the pins is invalidated and the pins are set to high impedance. (The Port 0 and Port 1 pull-up resistor control registers are initialized by a reset.) Figure 4.2-2 "Settings of the Port 0 and Port 1 pull-up register registers (PURR0 and PURR1)" shows the allowable settings of the Port 0 and Port 1 pull-up resistor control registers. 102 4.2 Port 0 and Port 1 Figure 4.2-2 Settings of the Port 0 and Port 1 pull-up register registers (PURR0 and PURR1) Port 0 (PURR0) Address 0072H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value PUR07 PUR06 PUR05 PUR04 PUR03 PUR02 PUR01 PUR00 11111111B R/W R/W R/W R/W R/W R/W R/W R/W PUR03 0 1 PUR02 PUR01 PUR00 P03 pull-up ON P02 pull-up ON P01 pull-up ON P00 pull-up ON P03 pull-up OFF P02 pull-up OFF P01 pull-up OFF P00 pull-up OFF PUR07 0 1 PUR06 PUR05 PUR04 P07 pull-up ON P06 pull-up ON P05 pull-up ON P04 pull-up ON P07 pull-up OFF P06 pull-up OFF P05 pull-up OFF P04 pull-up OFF Port 1 (PURR1) Address 0073H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value PUR17 PUR16 PUR15 PUR14 PUR13 PUR12 PUR11 PUR10 11111111B R/W R/W R/W R/W R/W R/W R/W R/W PUR13 0 1 PUR12 PUR11 PUR10 P13 pull-up ON P12 pull-up ON P11 pull-up ON P10 pull-up ON P13 pull-up OFF P12 pull-up OFF P11 pull-up OFF P10 pull-up OFF PUR17 PUR16 PUR15 PUR14 0 1 R/W : Readable/Writable : Initial value P17 pull-up ON P16 pull-up ON P15 pull-up ON P14 pull-up ON P17 pull-up OFF P16 pull-up OFF P15 pull-up OFF P14 pull-up OFF 103 CHAPTER 4 I/O PORTS 4.2.2 Operation of Port 0 and Port 1 This section describes the operation of Port 0 and Port 1. I Operation of Port 0 and Port 1 Operation of pins set up for output * * * * Specifying 1 to a bit of the DDR0 or DDR1 register sets the corresponding pin for output. For an output pin, operation of the output transistor is permitted and data in the output latch is output to the pin. Data written to the PDR0 register and/or PDR1 register remains in the output latches and is output to the pins as is. Reading the PDR0 and PDR1 registers outputs the values of the pins. operation instructions) (Except for bit Operation of pins set up for input * * * * Specifying 0 to a bit of the DDR0 or DDR1 register sets the corresponding pin for input. For an input pin, the output transistor is "OFF" and the pin is set to high impedance. Data written to the PDR0 register and/or PDR1 register remains in the output latches but is not output to the pins. Reading the PDR0 and PDR1 registers outputs the values in the pins. Operation on a reset * * Resetting the CPU initializes the DDR0 register and DDR1 register with zeros. Therefore, input to the pins is allowed and the pins are set to high impedance. The PDR0 and PDR1 registers are not initialized by a reset. Therefore, to use the pins for output, set output data to the PDR0 and PDR1 registers before setting the DDR0 or DDR1 register bits in output mode. Operation in stop mode and watch mode When Port 0 and Port1 are put in stop mode or watch mode, they are set to the status specified by the pin status specification bit of the standby control register, irrespective of the values of the DDR0 and DDR1 registers. Table 4.2-4 "Status of the Port 0 and Port 1 pins" shows the status of the Port 0 and Port 1 pins in each mode. 104 4.2 Port 0 and Port 1 Table 4.2-4 Status of the Port 0 and Port 1 pins Normal operation Main sleep Main stop (SPL=0) Sub-sleep Sub-stop (SPL=0) Watch mode (SPL=0) General-purpose I/O port P10 to P17 SPL: Pin status specification bit of the standby control register (STBC:SPL) Hi-z: High impedance Reference: When pull-up resistors are enabled by using the Port 0 or Port 1 pull-up resistor control register, the states of the pins do not become high impedance but rather become Level H (pulled-up) in stop mode or watch mode (STBC:SPL=1). However, the pins are not pulled up during a reset and their state becomes Hi-z. Pin name Main stop (SPL=1) Sub-stop (SPL=1) Watch mode (SPL=1) At reset P00 to P07 Hi-z Hi-z 105 CHAPTER 4 I/O PORTS 4.3 Port 2 Port 2 is a general-purpose I/O port used and is also used for resource input and output. The function of each pin can be switched between general-purpose I/O port and resource input and output for each bit. This section mainly describes the functions of the general-purpose I/O port. This section also describes the configuration, pins, and block diagram of the pins, and registers related to Port 2. I Configuration of Port 2 Port 2 consists of the following four types of element: * * * * I Pins of Port 2 Port 2 has eight CMOS I/O pins. Table 4.3-1 "Pins of Port 2" shows the pins of Port 2. Table 4.3-1 Pins of Port 2 Port name Pin name Function P23 to P27 General-purpose I/O P20 General-purpose I/O P21 toP22 General-purpose I/O Peripheral device also supported I/O format Input CMOS CMOS (Resources are hysteretic.) CMOS Output Circuit type D General-purpose I/O pin (P23 to P27), general-purpose I/O pin/PWCK (P20), generalpurpose I/O pin/PPG (P21/PPG01, P22/PPG02) Port 2 data register (PDR2) Port 2 direction register (DDR2) Port 2 pull-up resistor control register (PURR2) P23 to P27 Port 2 P20/PWCK P21/PPG01 to P22/PPG02 PWCK CMOS E PPG01, PPG02 D For details of the circuit types, see Section 1.7 "Explanations of the Pin Functions." 106 4.3 Port 2 I Block diagrams of Port 2 Figure 4.3-1 Block diagram of a Port 2 pin (for P20 only) To peripheral resource input PDR (port data register) Stop/watch mode (SPL=1) PDR read Internal data bus Pull-up resistor Approx. 50 k Port 2 pull-up resistor control register PDR read (for bit operation instructions) Pch Output latch PDR write Pch DDR (Port direction register) Pin Nch Stop/watch mode (SPL=1) DDR write DDR read SPL: Pin status specification bit of the standby control register (STBC) Figure 4.3-2 Block diagram of a Port 2 pin (for P21 only) PDR (port data register) Stop/watch mode (SPL=1) PDR read Internal data bus From peripheral resource output (P21) Port 2 pull-up resistor From output permission PDR read (for bit operation instructions) Pull-up resistor Approx. 50 k control register Pch Output latch PDR write Pch DDR (Port direction register) Pin Nch Stop/watch mode (SPL=1) DDR write DDR read SPL: Pin status specification bit of the standby control register (STBC) 107 CHAPTER 4 I/O PORTS Figure 4.3-3 Block diagram of a Port 2 pin (for P22 only) PDR (port data register) Stop/watch mode (SPL=1) PDR read Internal data bus From peripheral Port 2 pull-up resistor resource output (P22) control register From output permission Pull-up resistor Approx. 50 k PDR read (for bit operation instructions) Pch Output latch PDR write Pch DDR (Port direction register) Pin Nch Stop/watch mode (SPL=1) DDR write DDR read SPL: Pin status specification bit of the standby control register (STBC) Figure 4.3-4 Block diagram of a Port 2 pin (for P23 to P27) PDR (port data register) Stop/watch mode (SPL=1) PDR read Internal data bus Pull-up resistor Approx. 50 k Port 2 pull-up resistor control register PDR read (for bit operation instructions) Pch Output latch PDR write Pch DDR (Port direction register) Pin Nch Stop/watch mode (SPL=1) DDR write DDR read SPL: Pin status specification bit of the standby control register (STBC) Note: For input levels, CMOS input is applied to the pins and CMOS hysteresis input is applied to the resources. To use pins in input mode, prohibit operation of the corresponding resource. 108 4.3 Port 2 I Registers of Port 2 Port 2 has three related registers, PDR2, DDR2, and PURR2. Each bit of the register corresponds to a pin of Port 2. Table 4.3-2 "Correspondence between bit and pin of the Port 2 registers" shows the correspondence between bit and pin of the Port 2 registers. Table 4.3-2 Correspondence between bit and pin of the Port 2 registers Port name Port 2 Corresponding pin P27 P26 P25 P24 P23 P22 P21 P20 Correspondence between bits and pins of the related registers PDR2,DDR2,PURR2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 109 CHAPTER 4 I/O PORTS 4.3.1 Registers of Port 2 (PDR2, DDR2, PURR2) This section describes the registers related to Port 2. I Functions of the Port 2 registers Port 2 data register (PDR2) The PDR2 register indicates the states of the pins. Therefore, pins which have been set up for output allow for a value (0 or 1) which is the same as that of the output latch to be read. However, those set up for input do not allow for a value of the output latch to be read. Port 2 direction register (DDR2) The DDR2 register sets the direction (I/O) of each pin by bit. Specifying 1 to the bit of a pin sets it up for output, and specifying 0 sets it up for input. Settings for resource output To use a resource with output pins, enable each resource output permission bit. Output from the resource takes priority; thus, the setting values of the PDR2 register and DDR2 which correspond to the resource output pins have no effect irrespective of the resource output values and output permission settings that have been specified. Settings for resource input To use a resource with input pins, set pins which handle input from the resource for input. Values of the corresponding output latches have no effect. Reference: Bit operation commands (SETB, CLRB) do not read values from the pins but rather from output latches; thus, the values of output latches which correspond to the bit to be operated do not change. However, this does not apply to the pin described in the note below. Note: Pin exempted: P22 (PPG02) pin Executing an RMW-related command to the Port 2 data register (PDR2) while the resource is operating reads the level of the pin. Therefore, bit 2 of PDR2 may change its value. 110 4.3 Port 2 Table 4.3-3 "Functions of the Port 2 registers" shows the functions of the Port 2 registers. Table 4.3-3 Functions of the Port 2 registers Register name Port 2 data register (PDR2) Value 0 1 Reading The pin is Level L. The pin is Level H. Writing Concerning pins set up for output, Level L is output to the pins. R/W Concerning pins set up for output, Level H is output to the pins. Operation of the output transistors is disabled, and the pins are set up for input. R/W 1 R/W: Readable/Writable W: Write-only X: Not specified Output pin Operation of the output transistors is enabled, and the pins are set up for output. 000DH 00000000B 000CH XXXXXXXXB Read/ Write Address Initial value 0 Port 2 direction register (DDR2) Input pin Port 2 pull-up resistor control register (PURR2) Each Port 2 pin allows a pull-up resistor to be used. Write a pull-up resistor setting to each bit of the Port 2 pull-up resistor control register. Enabling pull-up resistors in stop mode or watch mode (STBC:SPL=1) using the Port 2 pull-up resistor control register does not set the pins to high impedance but rather to Level H (pulled up). However, during a reset, pull-up of the pins is invalidated and the pins are set to high impedance. (The Port 2 pull-up resistor control registers are initialized by a reset.) Figure 4.3-5 "Settings of the Port 2 pull-up resistor control register (PURR2)" shows the allowable settings of the Port 2 pull-up resistor control register. Figure 4.3-5 Settings of the Port 2 pull-up resistor control register (PURR2) Port 2 (PURR2) Address 0074H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value PUR27 PUR26 PUR25 PUR24 PUR23 PUR22 PUR21 PUR20 11111111B R/W R/W R/W R/W R/W R/W R/W R/W PUR23 PUR22 PUR21 PUR20 0 1 P23 pull-up ON P22 pull-up ON P21 pull-up ON P20 pull-up ON P23 pull-up OFF P22 pull-up OFF P21 pull-up OFF P20 pull-up OFF PUR27 PUR26 PUR25 PUR24 0 1 P27 pull-up ON P26 pull-up ON P25 pull-up ON P24 pull-up ON P27 pull-up OFF P26 pull-up OFF P25 pull-up OFF P24 pull-up OFF 111 CHAPTER 4 I/O PORTS 4.3.2 Operation of Port 2 This section describes operation of Port 2. I Operation of Port 2 Operation of pins set up for output * * * * Specifying 1 to a bit of the DDR2 register sets the corresponding pin for output. For an output pin, operation of the output transistor is permitted and data in the output latch is output to the pin. Data written to the PDR2 register remains in the output latches and is output to the pins as is. Reading the PDR2 register outputs the values of the pins. Operation of pins set up for input * * * * Specifying 0 to a bit of the DDR2 register sets the corresponding pin for input. For an input pin, the output transistor is "OFF" and the pin is set to high impedance. Data written to the PDR2 register remains in the output latches but is not output to the pins. Reading the PDR2 register outputs the values of the pins. Settings for resource output * Enabling a resource output permission bit sets up the corresponding pins for resource output. Settings for resource input * * * Specifying 0 to DDR2 register bits which correspond to resource input pins sets the pins for input. Values of the pins are always input into resource input (in stop mode or mode other than watch mode). Reading the PDR2 register outputs the values of the pins, irrespective of whether the resource is using input pins. Operation on a reset * * Resetting the CPU initializes the DDR2 register with zeros. Therefore, input to the pins is allowed and the pins are set to high impedance. The PDR2 register is not initialized by a reset. Therefore, to use the pins for output, set output data to the PDR2 register before setting the DDR2 register bits in output mode. Operation in stop mode and watch mode When Port 2 is put in stop mode or watch mode, it is set to the status specified by the pin status specification bit of the standby control register, irrespective of the values of the DDR2 register. 112 4.3 Port 2 Table 4.3-4 "Status of the Port 2 pins" shows the status of the Port 2 pins in each mode. Table 4.3-4 Status of the Port 2 pins Normal operation Main sleep Main stop (SPL=0) Sub-sleep Sub-stop (SPL=0) Watch mode (SPL=0) General-purpose I/O port Pin name Main stop (SPL=1) Sub-stop (SPL=1) Watch mode (SPL=1) At reset P20/PWCK,P21/ PPG01,P22/ PPG02,P23 to P27 Hi-z Hi-z SPL: Pin status specification bit of the standby control register (STBC:SPL) Hi-z: High impedance Reference: When pull-up resistors are enabled by using the Port 2 pull-up resistor control register, the states of the pins do not become high impedance but rather become Level H (pulled-up) in stop mode or watch mode (STBC:SPL=1). However, the pins are not pulled up during a reset and their state becomes Hi-z. 113 CHAPTER 4 I/O PORTS 4.4 Port 3 Port 3 is a general-purpose I/O port and is also used to input and output resources. The function of each pin can be switched between general-purpose I/O port and resource input and output for each bit. This section mainly describes the functions of the general-purpose I/O port. This section also describes the configuration, pins, and block diagram of the pins, and registers related to Port 3. I Configurations of Port 3 Port 3 consists of the following four types of element: * * * * I Pins of Port 3 Port 3 has eight CMOS I/O pins. These pins are used with various types of resources. When these pins are used with some kind of resource, Port 3 cannot be used as a general-purpose output port. Table 4.4-1 "Pins of Port 3" shows the pins of Port 3. Table 4.4-1 Pins of Port 3 Port name Pin name P30/PPG03/ MCO P31/ SCK1(UCK1) /LMCO P32/ SO1(UO1) Port 3 P33/SI1(UI1) P34/PTO2 P35/PWC P33 general-purpose I/O P34 general-purpose I/O P35 general-purpose I/O UI 8-bit UART/ SIO, data input PTO2 output PWC timer input CMOS (Resources are hysteretic.) CMOS CMOS (Resources are hysteretic.) CMOS E D E Function Peripheral device also supported PPG03 output, MCO output UCK 8-bit UART/ SIO, clock I/O, LMCO output UO 8-bit UART/ SIO, data output I/O format Input CMOS CMOS (Resources are hysteretic.) CMOS Output Circuit type D General-purpose I/O pin/Resource I/O pins (P30/PPG03/MCO to P37/PT01) Port 3 data register (PDR3) Port 3 direction register (DDR3) Port 3 pull-up resistor control register (PURR3) P30 general-purpose I/O P31 general-purpose I/O CMOS E P32 general-purpose I/O D 114 4.4 Port 3 Table 4.4-1 Pins of Port 3 (Continued) Port name Pin name P36/WTO Port 3 P37/PTO1 P37 general-purpose I/O PTO1 output Function P36 general-purpose I/O Peripheral device also supported PWC timer output CMOS D I/O format Input Output Circuit type D For details of the circuit types, see Section 1.7 "Explanations of the Pin Functions." I Block diagram of Port 3 Figure 4.4-1 Block diagram of a Port 3 pin P31, P33, and P35 only To peripheral resource input Pull-up resistor Approx. 50 k PDR (port data register) Stop/watch mode (SPL=1) PDR read Internal data bus From peripheral Port 3 pull-up resistor resource output control register Peripheral resource output permission Pch PDR read (for bit operation instructions) Output latch PDR write Pch Pin DDR (Port direction register) Nch DDR write Stop/watch mode (SPL=1) DDR read Only P30 and P31 have two peripheral resource output lines, respectively. P32, P34, P36, and P37 have one peripheral resource output line, respectively. SPL: Pin status specification bit of the standby control register (STBC) Reference: Continuously input values to the peripheral resource input (in mode other than stop mode/ watch mode). Note: For input levels, CMOS input is applied to the pins and CMOS hysteresis input is applied to the resources. 115 CHAPTER 4 I/O PORTS I Registers of Port 3 Port 3 has three related registers, PDR3, DDR3, and PURR3. Each bit of the register corresponds to a pin of Port 3. Table 4.4-2 "Correspondence between bit and pin of the Port 3 registers" shows the correspondence between bit and pin of the Port 3 registers. Table 4.4-2 Correspondence between bit and pin of the Port 3 registers Port name Port 3 Corresponding pin P37 P36 P35 P34 P33 P32 P31 P30 Correspondence between bits and pins of the related registers PDR3,DDR3,PURR3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 116 4.4 Port 3 4.4.1 Registers of Port 3 (PDR3, DDR3, PURR3) This section describes the registers related to Port 3. I Functions of the Port 3 registers Port 3 data register (PDR3) The PDR3 register indicates the states of the pins. Therefore, pins which have been set up for output allow for a value (0 or 1) which is the same as that of the output latch to be read. However, those set up for input do not allow for a value of the output latch to be read. Reference: The bit operation instructions SETB and CLRB read states of output latches (not pins). Thus, executing either bit operation command does not change the states of output latches related to bits not being operated. Port 3 direction register (DDR3) The DDR3 register sets the direction (I/O) of each pin by bit. Specifying 1 to the bit of a pin sets it up for output, and specifying 0 sets it up for input. Settings for resource output To use a resource with output pins, enable each resource output permission bit. Output from the resource takes priority; thus, setting values of the PDR3 register and DDR3 which correspond to the resource output pins have no effect irrespective of the resource output values and output permission settings that have been specified. Settings for resource input To use a resource with input pins, set pins which handle input from the resource for input. Values of the corresponding output latches have no effect. Table 4.4-3 "Functions of the Port 3 registers" shows the functions of the Port 3 registers. 117 CHAPTER 4 I/O PORTS Table 4.4-3 Functions of the Port 3 registers Register name Port 3 data register (PDR3) Value 0 1 Reading The pin is Level L. The pin is Level H. Writing Concerning pins set up for output, Level L is output to the pins. R/W Concerning pins set up for output, Level H is output to the pins. Operation of the output transistors is disabled, and the pins are set up for input. R/W 1 R/W: Readable/Writable X: Not specified Output pin Operation of the output transistors is enabled, and the pins are set up for output. 000FH 00000000B 000EH XXXXXXXXB Read/ Write Address Initial value 0 Port 3 direction register (DDR3) Input pin Port 3 pull-up resistor control register (PURR3) Each Port 3 pin allows a pull-up resistor to be used. Write a pull-up resistor setting to each bit of the Port 3 pull-up resistor control register. Enabling pull-up resistors in stop mode or watch mode (STBC:SPL=1) using the Port 3 pull-up resistor control register does not set the pins to high impedance but rather to Level H (pulled up). However, during a reset, pull-up of the pins is invalidated and the pins are set to high impedance. (The Port 3 pull-up resistor control registers are initialized by a reset.) Figure 4.4-2 "Settings of the Port 3 pull-up resistor control register (PURR3)" shows the allowable settings of the Port 3 pull-up resistor control register. Figure 4.4-2 Settings of the Port 3 pull-up resistor control register (PURR3) PURR3 Address 0075H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 11111111B PUR37 PUR36 PUR35 PUR34 PUR33 PUR32 PUR31 PUR30 R/W R/W R/W R/W R/W R/W R/W R/W PUR33 0 1 PUR32 PUR31 PUR30 P33 pull-up ON P32 pull-up ON P31 pull-up ON P30 pull-up ON P33 pull-up OFF P32 pull-up OFF P31 pull-up OFF P30 pull-up OFF PUR37 0 1 PUR36 PUR35 PUR34 P37 pull-up ON P36 pull-up ON P35 pull-up ON P34 pull-up ON P37 pull-up OFF P36 pull-up OFF P35 pull-up OFF P34 pull-up OFF 118 4.4 Port 3 4.4.2 Operation of Port 3 This section describes operation of Port 3. I Operation of Port 3 Operation of pins set up for output * * * * Specifying 1 to a bit of the DDR3 register sets the corresponding pin for output. When pins are set up for output, the output transistors are enabled and data of the output latches are output to the pins. Data written to the PDR3 register remains in the output latches and is output to the pins as is. Reading the PDR3 register outputs the values of the pins. Operation of pins set up for input * * * * Specifying 0 to a bit of the DDR3 register sets the corresponding pin for input. For an input pin, the output transistor is "OFF" and the pin is set to high impedance. Data written to the PDR3 register remains in the output latches but is not output to the pins. Reading the PDR3 register outputs the values of the pins. Settings for resource output * * Enabling a resource output permission bit sets up the corresponding pins for resource output. Even if resource output is enabled, values of the pins can be read by using the PDR3 register; thus, resource output values can be read. Settings for resource input * * Specifying 0 to DDR3 register bits which correspond to resource input pins set the pins for input. Reading the PDR3 register outputs the values of the pins, irrespective of whether the resource is using input pins. Operation on a reset * * Resetting the CPU initializes the DDR3 register with zeros. Thus, the output transistors are turned "OFF" (the pins are set for input) and the pins are set to high impedance. The PDR3 register is not initialized by a reset. Therefore, to use the pins for output, set output data to the PDR3 register before setting the DDR3 register bits in output mode. Operation in stop mode and watch mode When Port 3 is put in stop mode or watch mode, it is set to the status specified by the pin status specification bit of the standby control register, irrespective of the values of the DDR3 register. 119 CHAPTER 4 I/O PORTS Table 4.4-4 "Status of the Port 3 pins" shows the status of the Port 3 pins in each mode. Table 4.4-4 Status of the Port 3 pins Normal operation Main sleep Main stop (SPL=0) Sub-sleep Sub-stop (SPL=0) Watch mode (SPL=0) General-purpose I/O port/ Resource I/O Pin name Main stop (SPL=1) Sub-stop (SPL=1) Watch mode (SPL=1) At reset P30/PPG03/MCO to P37/PT01 Hi-z Hi-z SPL: Pin status specification bit of the standby control register (STBC:SPL) Hi-z: High impedance Reference: When pull-up resistors are enabled by using the Port 3 pull-up resistor control register, the states of the pins do not become high impedance but rather become Level H (pulled-up) in stop mode or watch mode (STBC:SPL=1). However, the pins are not pulled up during a reset and their state becomes Hi-z. 120 4.5 Port 4 4.5 Port 4 Port 4 is a general-purpose I/O port and is also used to input and output resources. The function of each pin can be switched between general-purpose I/O port and resource input and output for each bit. This section mainly describes the functions of the general-purpose I/O port. This section also describes the configuration, pins, and block diagram of the pins, and registers related to Port 4. I Configurations of Port 4 Port 4 consists of the following five types of element: * * * * * I Pins of Port 4 Port 4 has eight CMOS I/O pins. When P40/INT20/EC to P47/INT27/ADST are used for input, the Port 4 pins can be used as external interrupt input pins. Table 4.5-1 "Pins of Port 4" shows the pins of Port 4. Table 4.5-1 Pins of Port 4 Port name Pin name Function P40 generalpurpose I/O P41 generalpurpose I/O P42 N-channel open-drain I/O P43 N-channel open-drain I/O Peripheral device also supported External interrupt, external clock input pin CMOS P41/INT21/ SCK2 Port 4 P42/INT22/ SO2/SDA P43/INT23/ SI2/SCL External interrupt, SO2 output, I2C data pin External interrupt, SI2 input, I2C clock pin External interrupt, external clock input pin CMOS (Resources are hysteretic.) E G G I/O format Input Output Circuit type E General-purpose I/O pin/External interrupt 2/Resource I/O pin (P40/INT20/EC to P47/INT27/ ADST) Port 4 data register (PDR4) Port 4 direction register (DDR4) Port 4 pull-up resistor control register (PURR4) DDC select register (DDCR) P40/INT20/EC N-channel open drain 121 CHAPTER 4 I/O PORTS Table 4.5-1 Pins of Port 4 (Continued) Port name Pin name P44/INT24/ UCK2 P45/INT25/ UO2 Port 4 P46/INT26/ UI2 P47/INT27/ ADST P46 generalpurpose I/O P47 generalpurpose I/O External interrupt, UI 8-bit UART External interrupt, A/D activation pin Function P44 generalpurpose I/O P45 generalpurpose I/O Peripheral device also supported External interrupt, UCK 8-bit UART External interrupt, UO 8-bit UART CMOS (Resources are hysteretic.) I/O format Input Output Circuit type E E CMOS E E For details of the circuit types, see Section 1.7 "Explanations of the Pin Functions." I Block diagrams of Port 4 Figure 4.5-1 Block diagram of Port 4 pins (P40, P41, and P44 to P47) To external interrupt circuit Stop/watch mode (SPL=1) External interrupt permission P40, P41, P44, P45, P46, and P47 only To peripheral resource input Internal data bus PDR (port data register) Stop/watch mode (SPL=1) PDR read Peripheral resource output Port 4 pull-up resistor control register P41, P44, and P45 only Peripheral resource output permission Pull-up resistor Approx. 50 k Pch PDR read (for bit operation instructions) Output latch PDR write Pch Pin DDR (Port direction register) DDR write Stop/watch mode (SPL=1) DDR read SPL: Pin status specification bit of the standby control register (STBC) Nch 122 4.5 Port 4 Note: When Port 4 is used as an ordinary input port, operation of external interrupt circuits which use any of the Port 4 pins must be prohibited. See Chapter 13 "External Interrupt Circuit 1 (Edge)" and Chapter 14 "External Interrupt Circuit 2 (Level)." For input levels, CMOS input is applied to the pins and CMOS hysteresis input is applied to the resources. Figure 4.5-2 Block diagram of Port 4 pins (P42, P43) To external interrupt circuit Stop/watch mode (SPL=1) External interrupt permission To peripheral resource input Internal data bus PDR (port data register) Stop/watch mode (SPL=1) PDR read Peripheral resource output(*1) PDR read (for bit operation instructions) Output latch PDR write Pin Nch Stop/watch mode (SPL=1) SPL: *1 Pin status specification bit of the standby control register (STBC) P42 has two peripheral resource output lines. P43 has one peripheral resource output line. Note: When Port 4 is used as an ordinary input port, operation of external interrupt circuits which use any of the Port 4 pins must be prohibited. See Chapter 13 "External Interrupt Circuit 1 (Edge)" and Chapter 14 "External Interrupt Circuit 2 (Level)." For input levels, CMOS input is applied to the pins and CMOS hysteresis input is applied to the resources. Reference: To use P42 and P43 as I2C output pins or N-channel open-drain output pins, pull-up resistors are required on the external pins. Note that I2C can be used with the MB89PV530, MB89P538, MB89537HC/538HC, and MB89537AC/538AC only. MB89537C/538C, 123 CHAPTER 4 I/O PORTS I Registers of Port 4 Port 4 has three related registers, PDR4, DDR4, and PURR4. Each bit of the register corresponds to a pin of Port 4. Table 4.5-2 "Correspondence between bit and pin of the Port 4 registers" shows the correspondence between bit and pin of the Port 4 registers. Table 4.5-2 Correspondence between bit and pin of the Port 4 registers Port name Port 4 Corresponding pin P47 P46 P45 P44 Correspondence between bits and pins of the related registers PDR4,DDR4,PURR4 bit7 bit6 bit5 bit4 bit3 P43(*1) bit2 P42(*1) bit1 P41 bit0 P40 *1 Bit 2 and bit 3 of PURR4 are unused. Neither P42 nor P43 have internal pull-up resistors. 124 4.5 Port 4 4.5.1 Registers of Port 4 (PDR4, DDR4, PURR4, DDCR) This section describes the registers related to Port 4. I Functions of the Port 4 registers. Port 4 data register (PDR4) The PDR4 register indicates the states of the pins. Therefore, pins which have been set up for output allow for a value (0 or 1) which is the same as that of the output latch to be read. However, those set up for input do not allow for a value of the output latch to be read. Reference: Bit operation commands SETB and CLRB read states of output latches (not pins). Thus, executing either bit operation command does not change the states of output latches related to bits not being operated. Port 4 direction register (DDR4) The DDR4 register sets the direction (I/O) of each pin by bit. Specifying 1 to the bit of a pin sets it up for output, and specifying 0 sets it up for input. (Note that the DDR4 register does not allow bit 2 and bit 3 to be used.) Settings for external interrupt input In addition to use of interrupt circuit (external interrupt 1 or 2) permission, to use some of the pins as external interrupt input pins, the pins corresponding to them must be set for input. (The corresponding output latch data has no effect in this case.) Table 4.5-3 "Functions of the Port 4 registers" shows the functions of the Port 4 registers. Table 4.5-3 Functions of the Port 4 registers Register name Value Reading Writing 0 is set to the output latches, and Level L is output to the pins set up for output. R/W 1 The pin is Level H. 1 is set to the output latches, and Level H is output to the pins set up for output. Operation of the output transistors is disabled, and the pins are set up for input. R/W 1 R/W: Readable/Writable -: Unused X: Not specified Output pin Operation of the output transistors is enabled, and the pins are set up for output. 0011H 0000--00B 0010H XXXX11XXB Read/ Write Address Initial value 0 Port 4 data register (PDR4) The pin is Level L. 0 Port 4 direction register (DDR4) Input pin 125 CHAPTER 4 I/O PORTS Port 4 pull-up resistor control register (PURR4) Each Port 4 pin allows a pull-up resistor to be used. Write a pull-up resistor setting to each bit of the Port 4 pull-up resistor control register. Enabling pull-up resistors in stop mode or watch mode (STBC:SPL=1) using the Port 4 pull-up resistor control register does not set the pins to high impedance but rather to Level H (pulled up). However, during a reset, pull-up of the pins is invalidated and the pins are set to high impedance. (The Port 4 pull-up resistor control registers are initialized by a reset.) Figure 4.5-3 "Settings of the Port 4 pull-up resistor control register (PURR4)" shows the allowable settings of the Port 4 pull-up resistor control register. Figure 4.5-3 Settings of the Port 4 pull-up resistor control register (PURR4) PURR4 Address 0076H bit7 R/W bit6 R/W bit5 R/W bit4 R/W bit3 bit2 bit1 R/W bit0 R/W Initial value 1111--11B PUR47 PUR46 PUR45 PUR44 PUR41 PUR40 PUR41 0 1 PUR40 P41 pull-up ON P40 pull-up ON P41 pull-up OFF P40 pull-up OFF PUR47 0 1 R/W : Readable/Writable : Unused : Initial value PUR46 PUR45 PUR44 P47 pull-up ON P46 pull-up ON P45 pull-up ON P44 pull-up ON P47 pull-up OFF P46 pull-up OFF P45 pull-up OFF P44 pull-up OFF Reference: Neither P42 nor P43 have internal pull-up resistors. To use them as output pins, external pull-up resistors are required. 126 4.5 Port 4 I DDC select register (DDCR) Figure 4.5-4 "Block diagram of the DDC function" shows the block diagram of the DDC function. Figure 4.5-4 Block diagram of the DDC function P42 SDA SCL P43 P60/INT10 P43/INT23/ SI2/SCL External interrupt P41 SI2 SO2 SCK2 DDC F2MC-8L bus DDC This bit is used to select the rising edge or falling edge of serial data output. Select the source of an external interrupt circuit. Specifying 1 in the DDC bit prohibits serial data output and pulls down the SCL line with an interrupt from P43. DDC select register (DDCR) Figure 4.5-5 DDC select register (DDCR) DDC select register (DDCR) Address 0049H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value DDC -------0B R/W R/W : Readable/Writable - : Unused 127 CHAPTER 4 I/O PORTS Table 4.5-4 DDC select register (DDCR) Bit name bit1 to bit7 Unused * * Function Values in the bits are unfixed when they are read. Writing values in the bits has no effect. Serial data outputs falling edges. P60 is used for an external interrupt source. Serial data outputs rising edges. P43 is used for an external interrupt source. When an interrupt takes place, SIO output is prohibited and SCL is pulled down. When 0 is specified in the DDC bit: bit0 DDC When 1 is specified in the DDC bit: Operation of the DDC function Figure 4.5-6 Operation of I2C and SIO when the DDC function is enabled SCK2 Rising edge SO2/SDA #6 #7 #8 SO2/SDA output prohibited #1 #1 SO2/SDA permitted SI2/SCL released SI2/SCL Occurrence of an interrupt at an falling edge Interrupt End of the interrupt routine When 1 has been specified in the DDC bit of the DDCR register, serial data is output after a rising edge of SCK2. However, if a Level L signal has been input to the SI2/SCL pin, an external interrupt circuit is activated. In this routine, the interrupt circuit generates an interrupt signal to the CPU. This signal turns on a gate that pulls down the SI2/SCL pin and prohibits SO2 output. After the interrupt routine ends, the interrupt signal is reset. The connection of the circuits is restored to the previous state. See Figure 4.5-4 "Block diagram of the DDC function." 128 4.5 Port 4 4.5.2 Operation of Port 4 This section describes operation of Port 4. I Operation of Port 4 Operation of pins set up for output * * * * Specifying 1 to a bit of the DDR4 register sets the corresponding pin for output. For an output pin, operation of the output transistor is permitted and data in the output latch is output to the pin. Data written to the PDR4 register remains in the output latches and is output to the pins as is. Reading the PDR4 register outputs the values of the pins. Operation of pins set up for input * * * * Specifying 0 to a bit of the DDR4 register sets the corresponding pin for input. For an input pin, the output transistor is "OFF" and the pin is set to high impedance. Data written to the PDR4 register remains in the output latches but is not output to the pins. Reading the PDR4 register outputs the values of the pins. Settings for external interrupt input * * Specifying 0 to DDR4 register bits which correspond to external interrupt input set the pins for input. Reading the PDR4 register outputs the values of the pins, irrespective of whether external interrupt input or interrupt request output has been allowed or prohibited. Operation on a reset * * Resetting the CPU initializes the DDR4 register with zeros. Thus, the output transistors are turned "OFF" (all the pins are set for input) and the pins are set to high impedance. The PDR4 register is not initialized by a reset. Therefore, to use the pins for output, set output data to the PDR4 register before setting the DDR4 register bits in output mode. Operation in stop mode and watch mode When Port 4 is put in stop mode or watch mode, it is set to the status specified by the pin status specification bit of the standby control register, irrespective of the values of the DDR4 register. 129 CHAPTER 4 I/O PORTS Table 4.5-5 "Status of the Port 4 pins" shows the status of the Port 4 pins in each mode. Table 4.5-5 Status of the Port 4 pins Normal operation Main sleep Main stop (SPL=0) Sub-sleep Sub-stop (SPL=0) Watch mode (SPL=0) General-purpose I/O port/ External interrupt input/ Resource I/O Pin name Main stop (SPL=1) Sub-stop (SPL=1) Watch mode (SPL=1) At reset P40/INT4/EC to P47/INT10/UI2 Hi-z (external interrupt input) Hi-z SPL: Pin status specification bit of the standby control register (STBC:SPL) Hi-z: High impedance Reference: When pull-up resistors are enabled by using the Port 4 pull-up resistor control register, the states of the pins do not become high impedance but rather become Level H (pulled-up) in stop mode or watch mode (STBC:SPL=1). However, the pins are not pulled up during a reset and their state becomes Hi-z. Note that this does not apply to P42 and P43. 130 4.6 Port 5 4.6 Port 5 Port 5 is an N-channel open-drain output port which can also handle analog input. The function of each pin can be switched between analog input and N-channel open-drain output port for each bit. This section mainly describes the functions of the generalpurpose I/O port. This section also describes the configuration, pins, and block diagram of the pins, and registers related to Port 5. I Configuration of Port 5 Port 5 consists of the following two types of element: * * I Pins of Port 5 Port 5 has eight N-channel open-drain pins. Do not use them as output-only pins when analog signals are to be input from an A/D converter. Table 4.6-1 "Pins of Port 5" shows the pins of Port 5. Table 4.6-1 Pins of Port 5 Port name Pin name P50/AN0 P51/AN1 P52/AN2 P53/AN3 Port 5 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P54 N-channel output P55 N-channel output P56 N-channel output P57 N-channel output AN4 analog input 4 AN5 analog input 5 AN6 analog input 6 AN7 analog input 7 Function P50 N-channel output P51 N-channel output P52 N-channel output P53 N-channel output Peripheral device also supported AN0 analog input 0 AN1 analog input 1 AN2 analog input 2 AN3 analog input 3 Analog N-channel open drain output H I/O format Input Output Circuit type Output-only pin (P50/AN0 to P57/AN7) Port 5 data register (PDR5) For details of the circuit types, see Section 1.7 "Explanations of the Pin Functions." For information about operation of the pins to analog input, see Chapter 15 "A/D Converter." 131 CHAPTER 4 I/O PORTS I Block diagram of Port 5 Figure 4.6-1 Block diagram of a Port 5 pin A/D converter channel selector Internal data bus A/D converter analog input PDR (port data register) PDR read (for bit operation instructions) Output latch PDR write Pch Pin Nch Stop/watch mode (SPL=1) SPL: Pin status specification bit of the standby control register (STBC) Note: Do not use the pins for output when analog signals are to be input to Port 5. I Register of Port 5 Port 5 has one related register, PDR5. Each bit of the PDR5 register corresponds to a pin of Port 5. Table 4.6-2 "Correspondence between bit and pin of the Port 5 register" shows the correspondence between bit and pin of the Port 5 register. Table 4.6-2 Correspondence between bit and pin of the Port 5 register Port name PDR5 Port 5 Corresponding pin P57 P56 P55 P54 P53 P52 P51 P50 Correspondence between bits and pins of the related registers bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 132 4.6 Port 5 4.6.1 Register of Port 5 (PDR5) This section describes the register related to Port 5. I Functions of the Port 5 register Port 5 data register (PDR5) The PDR5 register indicates values of the output latches. Therefore, the states of the pins cannot be read. Settings for analog input To use Port 5 for analog input, write 1 to bits of the PDR5 register. The corresponding output transistors are turned "OFF" and the state of the pins becomes high impedance. Table 4.6-3 "Functions of the Port 5 register" shows the functions of the Port 5 register. Table 4.6-3 Functions of the Port 5 register Register name Value Reading The value of the output latch is "0." The value of the output latch is "1." Writing Level L is output to the pin. (Set 0 to the output latch to turn on the output transistor.) R/W 1 R/W: Readable/Writable The pin is set to high impedance. (Set 1 to the output latch to turn off the output transistor.) 0012H 11111111B Read/ Write Address Initial value 0 Port 5 data register (PDR5) 133 CHAPTER 4 I/O PORTS 4.6.2 Operation of Port 5 This section describes operation of Port 5. I Operation of Port 5 Operation of pins set up for output * Data written to the PDR5 register remains in the output latches. When the value of an output latch is "0," the output transistor is turned "ON" and Level L is output to the pin. When the value of an output latch is "1," the output transistor is turned "OFF" and state of the pin becomes high impedance. When an output pin is pulled up and if the value of the output latch is "1," it is pulled up. Reading the PDR5 register always outputs the values of the output latches. * Settings for analog input * * Specify 1 to a bit of the PDR5 register which corresponds to a target analog input pin to turn off the output transistor. Reading the PDR5 register always outputs the values of the output latches. Operation on a reset Resetting the CPU initializes values of the PDR5 register with ones. transistors are turned "OFF" and the pins are set to high impedance. Operation in stop mode and watch mode When Port 5 is put in stop mode or watch mode, it is set to the status specified by the pin status specification bit of the standby control register. Note that input is fixed to prevent leakage due to released input. Table 4.6-4 "Status of the Port 5 pins" shows the status of the Port 5 pins in each mode. Table 4.6-4 Status of the Port 5 pins Normal operation Main sleep Main stop (SPL=0) Sub-sleep Sub-stop (SPL=0) Watch mode (SPL=0) General-purpose I/O port/ Analog input Thus, all the output Pin name Main stop (SPL=1) Sub-stop (SPL=1) Watch mode (SPL=1) At reset P50/AN0 to P57/AN7 Hi-z Hi-z SPL: Pin status specification bit of the standby control register (STBC:SPL) Hi-z: High impedance 134 4.7 Port 6 4.7 Port 6 Port 6 is a general-purpose input port which is also used to input external interrupts. This section mainly describes the functions of the general-purpose input port. This section also describes the configuration, pins, and block diagram of the pins, and registers related to Port 6. I Configurations of Port 6 Port 6 consists of the following four types of element: * * * * I Pins of Port 6 Port 6 has five CMOS input-only type I/O pins (excluding P64/X1A). The P60/INT10 to P63/INT13/X0A pins can be used for both input and external interrupt at the same time. Table 4.7-1 Pins of Port 6 Port name Pin name P60/INT10 to P62/INT12 Port 6 P63/INT13/ X0A P64/X1A Function P60 to P62 General-purpose input P63 General-purpose input P64 General-purpose input Peripheral device also supported Input external interrupt 1 External interrupt 1, subclock input pin Subclock output pin I/O format Input CMOS (Resources are hysteretic.) Output CMOS Circuit type I I/A J/A General-purpose input pin/External interrupt/Sub-clock related element (P60/INT10 to P62/ INT12, P63/INT13/X0A, and P64/X1A) Port 6 data register (PDR6) Port 6 pull-up register (PURR6) DDC select register (DDCR) CMOS *1 Resources are hysteretic. For details of the circuit types, see Section 1.7 "Explanations of the Pin Functions." 135 CHAPTER 4 I/O PORTS I Block diagrams of Port 6 Figure 4.7-1 Block diagram of Port 6 pins (excluding P64/X1A) To external interrupt circuit Stop/watch mode (SPL=1) External interrupt permission Pull-up resistor Approx. 50 k Pull-up control register Pch Internal data bus PDR (port data register) Stop/watch mode (SPL=1) P63 only PDR read To X0A of Subclock selector a subclock circuit Pin P60/INT10 P61/INT11 P62/INT12 P63/INT13/X0A SPL: Pin status specification bit of the standby control register (STBC) Note: For a single-clock system device, a port input (P63) or external interrupt input (INT13) can be used. For a single-clock system device, a pull-up resistor can be set to the port input. However, do not use a pull-up resistor to the external interrupt input. For input levels, ports are CMOS input and resource is CMOS hysteresis input. For a dual-clock system device, a subclock input (X0A) is to be used; thus, no pull-up resistor can be set. Be sure to disable pull-up resistors by using the pull-up resistor control register. 136 4.7 Port 6 Figure 4.7-2 Block diagram of P64/X1A Pull-up resistor Approx. 50 k Pull-up control register Internal data bus Pch PDR (port data register) Stop/watch mode (SPL=1) PDR read To X1A of a subclock circuit Subclock selector Pin P64/X1A SPL: Pin status specification bit of the standby control register (STBC) Note: For a single-clock system device, a port input (P64) can be used. For a single-clock system device, a pull-up resistor can be set to the port input. For a dual-clock system device, a subclock input (X1A) is to be used; thus, no pull-up resistor can be set. Be sure to disable pull-up resistors by using the pull-up resistor control register. Port 6 has one related register, PDR6. Each bit of the PDR6 register corresponds to a pin of Port 6. Table 4.7-2 "Correspondence between bit and pin of the Port 6 register" shows the correspondence between bit and pin of the Port 6 register. Table 4.7-2 Correspondence between bit and pin of the Port 6 register Port name Port 6 Corresponding pin P64 P63 P62 P61 P60 Correspondence between bits and pins of the related registers PDR6,PURR6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 137 CHAPTER 4 I/O PORTS 4.7.1 Register of Port 6 (PDR6, PURR6, DDCR) This section describes the register related to Port 6. I Functions of the Port 6 register Port 6 data register (PDR6) The PDR6 register keeps the states of the pins. The pins are input ports; thus, the status of the output latches cannot be read. Table 4.7-3 "Functions of the Port 6 register" shows the functions of the Port 6 register. Table 4.7-3 Functions of the Port 6 register Register name Port 6 data register (PDR6) R: Read-only Value 0 1 Reading The pin is Level L. R The pin is Level H. 0013H XXXXXXXXB Read/Write Address Initial value X: Not specified I Port 6 pull-up resistor control register (PURR6) Each Port 6 pin allows a pull-up resistor to be used. Write a pull-up resistor setting to each bit of the Port 6 pull-up resistor control register. Enabling pull-up resistors in stop mode or watch mode (STBC:SPL=1) using the Port 6 pull-up resistor control register does not set the pins to high impedance but rather to Level H (pulled up). However, during a reset, pull-up of the pins is invalidated and the pins are set to high impedance. (The Port 6 pull-up resistor control registers are initialized by a reset.) Figure 4.7-3 "Settings of the Port 6 pull-up resistor control register (PURR6)" shows the allowable settings of the Port 6 pull-up resistor control register. 138 4.7 Port 6 Figure 4.7-3 Settings of the Port 6 pull-up resistor control register (PURR6) PURR6 Address 0079H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value PUR64 PUR63 PUR62 PUR61 PUR60 ---11111B R/W R/W R/W R/W R/W PUR63 0 1 PUR62 PUR61 PUR60 P63 pull-up ON P62 pull-up ON P61 pull-up ON P60 pull-up ON P63 pull-up OFF P62 pull-up OFF P61 pull-up OFF P60 pull-up OFF PUR64 0 1 R/W : Readable/Writable : Initial value P64 pull-up ON P64 pull-up OFF I DDC select register (DDCR) Figure 4.7-4 "Block diagram of the DDC function" shows the block diagram of the DDC function. Figure 4.7-4 Block diagram of the DDC function P42 SDA SCL P43 P60/INT10 P43/INT23/ SI2/SCL External interrupt P41 SI2 SO2 SCK2 DDC F2MC-8L bus DDC This bit is used to select the rising edge or falling edge of serial data output. Select the source of an external interrupt circuit. Specifying 1 in the DDC bit prohibits serial data output and pulls down the SCL line with an interrupt from P43. 139 CHAPTER 4 I/O PORTS DDC select register (DDCR) Figure 4.7-5 DDC select register (DDCR) DDC select register (DDCR) Address 0049H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value DDC -------0B R/W R/W : Readable/Writable - : Unused Table 4.7-4 DDC select register (DDCR) Bit name bit1 to bit7 Unused * * Function Values in the bits are not specified when they are read. Writing values in the bits has no effect. Serial data outputs falling edges. P60 is used for an external interrupt source. Serial data outputs rising edges. P43 is used for an external interrupt source. When an interrupt takes place, SIO output is prohibited and SCL is pulled down. When 0 is specified in the DDC bit: bit0 DDC When 1 is specified in the DDC bit: Operation of the DDC function Figure 4.7-6 Operation of I2C and SIO when the DDC function is enabled SCK2 Rising edge SO2/SDA #6 #7 #8 SO2/SDA output prohibited #1 #1 SO2/SDA permitted SI2/SCL released SI2/SCL Occurrence of an interrupt at an falling edge Interrupt End of the interrupt routine When 1 has been specified in the DDC bit of the DDCR register, serial data is output after a rising edge of SCK2. However, if a Level L signal has been input to the SI2/SCL pin, an external interrupt circuit is activated. In this routine, the interrupt circuit generates an interrupt signal to the CPU. This signal turns on a gate that pulls down the SI2/SCL pin and prohibits SO2 output. After the interrupt routine ends, the interrupt signal is reset. The connection of the circuits is restored to the previous state. See Figure 4.7-4 "Block diagram of the DDC function." 140 4.7 Port 6 4.7.2 Operation of Port 6 This section describes operation of Port 6. I Operation of Port 6 Operation of pins set up for output * Reading the PDR6 register outputs the values of the pins. Settings for external interrupt input * Reading the PDR6 register outputs the values of the pins, irrespective of whether external interrupt input or interrupt request output has been allowed or prohibited. Operation on a reset * The PDR6 register is not initialized by a reset. Operation on a reset * The PDR6 register is not initialized by a reset. Operation in stop mode and watch mode When Port 6 is put in stop mode or watch mode, it is set to the status specified by the pin status specification bit of the standby control register. Table 4.7-5 "Status of the Port 6 pins" shows the status of the Port 6 pins in each mode. Table 4.7-5 Status of the Port 6 pins Normal operation Main sleep Main stop (SPL=0) Sub-sleep Sub-stop (SPL=0) Watch mode (SPL=0) General-purpose input port/ External interrupt input Pin name Main stop (SPL=1) Sub-stop (SPL=1) Watch mode (SPL=1) At reset P60/INT0 to P64/X1A Hi-z (external interrupt input) Hi-z SPL: Pin status specification bit of the standby control register (STBC:SPL) Hi-z: High impedance Reference: When all the output register bits are turned "OFF," the states of the pins with pull-up resistors enabled do not become high impedance but rather become Level H (pulled-up). Note: When "rising edge," "falling edge," or "both edges" is set in the bit for selecting the edge polarity in stop mode (SPL=1), interrupt input is allowed and not blocked. In this case, keep the electric potential of the pin constant using the pull-up option setting register, external pullup register, or external-pull-down register. 141 CHAPTER 4 I/O PORTS 4.8 Sample I/O Port Program This section provides a sample of a program with I/O ports used. I Sample I/O port program Processing specifications * * By using Port 0 and Port 1, light all the 7 segments (8 segments including Dp) of a LED. The P00 pin is used for a LED anode common pin, and P10 to P17 pins are used for the segment pins. Figure 4.8-1 "Example of connection of an 8-segment LED" shows an example of connection of an 8-segment LED. Figure 4.8-1 Example of connection of an 8-segment LED MB89530/530H/530A P00 P17 P16 P10 Sample coding PDR0 DDR0 PDR1 DDR1 EQU EQU EQU EQU 0000H 0001H 0002H 0003H ; ; ; ; Address Address Address Address of of of of the the the the port Port Port Port 0 0 1 1 data register direction register data register direction register ;----------Main program----------------------------------------------------CSEG ; [CODE SEGMENT] : CLRB PDR0:0 ; Set P00 Level L. MOV PDR1, #11111111B ; Set all the Port 1 pins to Level H. MOV DDR0, #11111111B ; Set P00 for output; specify #xxxxxxx1B. MOV DDR1, #11111111B ; Set Port 1 to allow all-bit output. : ENDS ;--------------------------------------------------------------------------END 142 CHAPTER 5 TIMEBASE TIMER This chapter describes the functions and operations of the timebase timer. 5.1 "Overview of the Timebase Timer" 5.2 "Configuration of the Timebase Timer" 5.3 "Timebase Timer Control Register (TBTC)" 5.4 "Timebase Timer Interrupt" 5.5 "Operation of the Timebase Timer" 5.6 "Notes on Using the Timebase Timer" 5.7 "Program Example of the Timebase Timer" 143 CHAPTER 5 TIMEBASE TIMER 5.1 Overview of the Timebase Timer The timebase timer is a 21-bit free-run counter that counts up in synchronization with the internal count clock (divide-by-two of the main clock oscillation) and which provides the interval timer function that enables the selection of four types of interval time. The timebase timer also supplies timer output for the oscillation stabilization wait time, an operating clock for the watchdog timer and continuous activation for the A/D converter. The timebase timer stops its operations in a mode in which the main clock oscillation stops. I Interval Timer Function The interval timer is a function used to generate an interrupt repeatedly at constant intervals. * * An interrupt occurs if the interval timer bit of the counter of the timebase timer overflows. The interval timer bit (interval time) can be selected from four kinds of interval time. Table 5.1-1 "Interval Time of the Timebase Timer" lists the interval time of the timebase timer. Table 5.1-1 Interval Time of the Timebase Timer Internal count clock cycle Interval time 213/FCH (Approx. 0.82 ms) 215/FCH (Approx. 3.3 ms) 218/FCH (Approx. 26.2 ms) 222/FCH (Approx. 419.4 ms) 2/FCH (0.2s) FCH: Main clock oscillation Values in ( ) shows the interval time when the main clock operates with 10 MHz oscillation. 144 5.1 Overview of the Timebase Timer I Clock Supply Function The clock supply function supplies operating clocks for the timer outputs (three types) of the main clock oscillation stabilization wait time and for some peripheral functions. Table 5.1-2 "Clocks Supplied from the Timebase Timer" lists the cycles of clocks supplied to each peripheral function from the timebase timer. Table 5.1-2 Clocks Supplied from the Timebase Timer Clock supply destination Main clock oscillation stabilization wait time Watchdog timer A/D converter Clock cycle 214/FCH (Approx. 1.64 ms) 217/F CH Remarks Selected by the oscillation stabilization wait time select bits (SYCC: WT1, WT0) of the system clock control register in the clock controller Count-up clock of the watchdog timer Clock for continuous start (Approx. 13.10 ms) 218/FCH (Approx. 26.20 ms) 221/FCH (Approx. 209.7 ms) 28/FCH (Approx. 25.5 s) FCH: Main clock oscillation Values in ( ) shows the interval time when the main clock operates with 10 MHz oscillation Note: The oscillation cycle is unstable just after the oscillation start and the oscillation stabilization wait time serves as a guideline. 145 CHAPTER 5 TIMEBASE TIMER 5.2 Configuration of the Timebase Timer The timebase timer is made up of the following four blocks: * Timebase timer counter * Counter clear circuit * Interval timer selector * Timebase timer control register (TBTC) I Block Diagram of the Timebase Timer Figure 5.2-1 Block Diagram of the Timebase Timer To A/D converter Timebase timer counter To watchdog timer Divide-by-two of FCH Counter clear 21 22 23 26 27 28 29 210 211 212 213 214 215 216 217 220 221 OF Watchdog timer clear Power-on reset Subclock mode start Stop mode start (in main clock mode) IRQE Timebase timer interrupt OF: Overflow FCH: Main clock oscillation OF Counter clear circuit Interval timer selector To oscillation stabilization wait time selector of clock controller OF OF TBOF TBIE TBC1 TBC0 TBR Timebase timer control register (TBTC) Timebase timer counter 21-bit up-counter using the count clock of divide-by-two of the main clock oscillation. This counter stops operating when the main clock oscillation stops. Counter clear circuit Clears the counter when, in addition to the setting (TBTC: TBR=0) by the TBTC register, a transition to the main stop mode (STBC: STP=1) or subclock mode (SYCC: SCS=0), or a power-on reset occurs. 146 5.2 Configuration of the Timebase Timer Interval timer selector Circuit to select one bit for the interval timer from four bits of the timebase timer counter. The overflow of the selected bit causes an interrupt. Timebase timer control register (TBTC) This register is used to select the interval time, clear the counter, control interrupts, and check the states. 147 CHAPTER 5 TIMEBASE TIMER 5.3 Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) is used to select the interval time, clear the counter, control interrupts, and check the state. I Timebase Timer Control Register (TBTC) Figure 5.3-1 Timebase Timer Control Register (TBTC) Address 0 0 0 AH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00---000B TBOF TBIE R/W R/W TBC1 TBC0 TBR R/W R/W W TBR 0 1 Timebase timer initialization bit Read Write Clear the counter of the timebase timer "1" is always read No change and no effects on others TBC1 TBC0 0 0 1 1 0 1 0 1 Interval time select bits 213/FCH 215/FCH 218/FCH 222/FCH FCH: Main clock oscillation TBIE 0 1 Interrupt request enable bit Prohibit interrupt request output Allow interrupt request output Overflow interrupt request flag bit Read No overflow of specified bit Overflow of specified bit Write Clear this bit No change and no effects on others TBOF R/W : Read/write enabled W : Write only : Unused :Initial value 0 1 148 5.3 Timebase Timer Control Register (TBTC) Table 5.3-1 Explanation of Functions of Each Bit of the Timebase Timer Control Register (TBTC) Bit name * TBOF: Overflow interrupt request flag bit * * Function This bit is set to "1" if the specified bit of the counter of the timebase timer overflows. If both this bit and the interrupt enable bit (TBIE) are "1", an interrupt request is output. If "0" is written into this bit, the counter is cleared. If "1" is written, no change occurs and operations are not affected. Bit to allow/prohibit interrupt request output to CPU. If both this bit and the overflow interrupt request flag bit (TBOF) are "1", an interrupt request is output. The read value is undefined. Writing has no effect on operation. Bits to select the interval timer cycle Bits for the interval timer of the counter of the timebase timer are specified. Four kinds of interval time can be selected. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TBIE: Interrupt request enable bit * Unused bits * * * * * * * TBC1, TBC0: Interval time select bit Bit 0 TBR: Timebase timer initialization bit Bit to clear the counter of the timebase timer If "0" is written into this bit, the counter is cleared to "000000H". If "1" is written, no change occurs and operations are not affected. Reference: "1" is always read. 149 CHAPTER 5 TIMEBASE TIMER 5.4 Timebase Timer Interrupt As an interrupt source of the timebase timer, an overflow of the specified bit of the timebase timer counter is available (interval timer function). I Interrupt when the Interval Timer Function is Active If an overflow of the selected interval timer bit occurs after the counter is counted up by the internal count clock, the overflow interrupt request flag bit (TBTC: TBOF) is set to "1". At this time, if the interrupt request enable bit is set (TBTC: TBIE=1), an interrupt request to CPU (IRQE) is generated. Clear the interrupt request by writing "0" into the TBOF bit using an interrupt processing routine. The TBOF bit is set whenever an overflow of the specified bit occurs regardless of the value of the TBIE bit. Note: To allow interrupt request output (TBTC: TBIE=1) after releasing a reset, clear (TBTC: TBOF=0) the TBOF bit at the same time. Reference: If the TBIE bit is changed from prohibition to permission (0 --> 1) when the TBOF bit is "1", an interrupt request is issued immediately. If the counter clear (TBTC: TBR=0) and an overflow of the selected bit occur at the same time, the TBOF bit is not set. I Oscillation Stabilization Wait Time and Timebase Timer Interrupts If interval time shorter than the oscillation stabilization wait time of the main clock is set, an interval interrupt request (TBTC: TBOF=1) of the timebase timer is generated when the operation in main clock mode starts. In this case, prohibit (TBTC: TBIE=0) interrupts of the timebase timer when making a transition to a mode in which the oscillation of the main clock stops (main stop and subclock modes). I Register and Vector Table Related to the Timebase Timer Interrupts Table 5.4-1 Register and Vector Table Related to the Timebase Timer Interrupts Interrupt name IRQE Interrupt level setting register Register ILR4 (007EH) Bit to be set LE1 (bit 5) LE0 (bit 6) Vector table address Upper FFDEH Lower FFDFH For the interrupt operations, see Section 3.4.2 "Interrupt Processing". 150 5.5 Operation of the Timebase Timer 5.5 Operation of the Timebase Timer The timebase timer provides the interval timer function and supplies the clock to part of the peripheral functions. I Operation of the Interval Timer Function (Timebase Timer) The setting in Figure 5.5-1 "Setting of the Interval Timer Function" is required for the operation of the interval timer function. Figure 5.5-1 Setting of the Interval Timer Function bit7 TBTC bit6 bit5 bit4 bit3 bit2 bit1 bit0 : Bit used 1 : 1 is set 0 : 0 is set TBOF TBIE 0 1 TBC1 TBC0 TBR 0 The counter of the timebase timer continues to count up provided the main clock oscillates in synchronization with the internal count clock (divide-by-two of the main clock oscillation). If the counter is cleared (TBR=0), it starts counting up from "0". If an overflow of the bit for the interval timer occurs, "1" is set to the overflow interrupt request flag bit (TBOF). That is, starting when clearing occurs, an interrupt request is generated at regular intervals of the selected time. I Operation of the Clock Supply Function The timebase timer is also used as a timer to generate the oscillation stabilization wait time of the main clock. Counting of the oscillation stabilization wait time starts when the counter of the timebase timer is cleared and ends when an overflow of the bit for oscillation stabilization wait time occurs. Three kinds of oscillation stabilization wait time can be selected by the setting of the oscillation stabilization wait time select bits (SYCC: WT1, WT0) of the system clock control register. The timebase timer supplies the clock to the watchdog timer and A/D converter, and LCD controller/driver. When the counter of the timebase timer is cleared, operations of the continuous activation cycles of the A/D converter are affected. If the timebase timer counter is cleared by changing to main clock operation (STBC:STP = 1) or by changing to subclock operation (STCC:SCS = 0) when timebase timer output is selected (WDTC:CS = 0), the counter of the watchdog timer is cleared at the same time. 151 CHAPTER 5 TIMEBASE TIMER I Operations of the Time-based Timer Figure 5.5-2 "Operations of the Timebase Timer" shows the operations in the following states: * * * * When a power-on reset occurs When a transition to the sleep mode occurs during operation of the interval timer function in main clock mode When a transition to the main stop mode occurs When the counter clear is requested In subclock mode and main stop mode, the timebase timer is cleared and its operation is stopped. When returning from the subclock mode or main stop mode, the oscillation stabilization wait time is counted by the timebase timer. Figure 5.5-2 Operations of the Timebase Timer Counter value 1FFFFFH Clearing by transition to the main stop mode Oscillation stabilization wait overflow 00000H CPU operation Interval cycle (TBTC: TBC1, TBCO=11B) start Power-on reset (option) Clear by an interrupt processing routine Counter clear (TBTC: TBR=0) TBOF bit TBIE bit SLP bit (STBC register) Sleep release by IRQ7 STP bit (STBC register) Stop release by an external interrupt When "11B" is set to the interval time select bits (TBTC: TBC1, TBC0) of the timebase timer control register (222/FCH). : Indicates the oscillation stabilization wait time Sleep Stop 152 5.6 Notes on Using the Timebase Timer 5.6 Notes on Using the Timebase Timer The following describes the precautions to take when using the timebase timer. I Notes on Using the Timebase Timer Precautions when setting the timebase timer with programs Because it is impossible to return from interrupt processing if the interrupt request flag bit (TBTC: TBOF) is "1" and the interrupt request enable bit (TBTC: TBIE=1) is allowed, the TBOF bit must be cleared. Clearing the timebase timer The timebase timer is cleared, in addition to clearing by the timebase timer initialization bit (TBTC: TBR=0), when the oscillation stabilization wait time of the main clock is required. If the timebase timer is selected (WDTC: CS=0) as the count clock of the watchdog timer, the watchdog timer is cleared when the timebase timer is cleared. Using the timebase timer as a timer for the oscillation stabilization wait time Since the main clock oscillation is stopped when the power is turned on or is in main stop mode or subclock mode, the oscillator takes the oscillation stabilization wait time of the main clock. The appropriate oscillation stabilization wait time must be selected according to the type of resonator connected to the oscillator (clock generator) of the main clock. For details, see Section 3.6.5 "Oscillation Stabilization Wait Time" Precautions for peripheral functions to which the clock is supplied from the timebase timer In a mode in which the main clock oscillation stops, the counter is cleared and the timebase timer stops its operation. In addition, if the counter of the timebase timer is cleared, the "H" level period of the clock supplied by the timebase timer may become shorter or its "L" level period may become longer by half a cycle at the most, since the clock is output from the initial state. The clock for the watchdog timer is also output from the initial state. However, the watchdog timer counter is cleared at the same time and the watchdog timer operates in normal cycles. 153 CHAPTER 5 TIMEBASE TIMER 5.7 Program Example of the Timebase Timer The following shows a program example of the timebase timer. I Program Example of the Timebase Timer Processing specifications Generate the interval timer interrupt of 218/FCH (FCH: main clock oscillation) repeatedly. The interval time at this time is about 26 ms (for 10 MHz operations). Coding example TBTC TBOF ILR4 INT_V EQU EQU EQU 0000AH TBTC:7 007EH ; Address of the timebase timer control ; Definition of overflow interrupt request flag bit ; Address of the interrupt level setting register 4 ; [DATA SEGMENT] DSEG ABS ORG 0FFDEH IRQE DW WARI ; Setting interrupt vector INT_V ENDS ;----Main program----------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) and other are assumed to have been initialized : CLRI ; Interrupt disable MOV ILR4,#11011111B ; Setting interrupt level(level 1) MOV TBTC,#01000100B ; Clearing the overflow interrupt request flag, enabling the interrupt request output, selecting 218/FCH, and clearing the timebase timer ; Interrupt enable SETI : ;----Interrupt program-----------------------------------------------------WARI CLRB TBOF ; Clearing interrupt request flag PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ; -------------------------------------------------------------------------END 154 CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer. 6.1 "Overview of the Watchdog Timer" 6.2 "Configuration of the Watchdog Timer" 6.3 "Watchdog Timer Control Register (WDTC)" 6.4 "Operation of the Watchdog Timer" 6.5 "Notes on Using the Watchdog Timer" 6.6 "Program Example of the Watchdog Timer" 155 CHAPTER 6 WATCHDOG TIMER 6.1 Overview of the Watchdog Timer The watchdog timer is a 1-bit counter which accepts the output of either the timebase timer operating with the main clock or the watch prescaler operating with the subclock as the count clock. If the watchdog timer is not cleared for a specified period of time after activation, CPU is reset. I Watchdog Timer Function The watchdog timer is a counter against program runaway. Once the watchdog timer is activated, it is necessary to continue clearing it periodically within a specified period of time. If the watchdog timer is not cleared for a specified period of time, for example, because the program slips into an endless loop, a watchdog reset of the four instruction cycles is generated to CPU. As the count clock of the watchdog timer, the output of either the timebase timer or watch prescaler can be selected. The interval time of the watchdog timer is as listed in Table 6.1-1 "Interval Time of the Watchdog Timer". If the watchdog timer is not cleared, a watchdog reset occurs between the minimum and maximum times. Clear the counter within the minimum time of this table. Table 6.1-1 Interval Time of the Watchdog Timer Count clock Timebase timer output (for main clock oscillation 10 MHz) Minimum time maximum time Approx. 209.7 ms(*1) Approx. 419.4 ms watch prescaler output (for subclock oscillation 32. 768 kHz) 500 ms(*2) 1000 ms *1: Divide-by-two of the main clock oscillation (FCH) x count of the timebase timer (221) *2: Cycle of the subclock oscillation (FCL) x count of the watch prescaler (214) For the minimum and maximum times of the interval time of the watchdog timer, see Section 6.4 "Operation of the Watchdog Timer" Note: The watchdog timer counter is cleared as soon as the timebase timer is cleared (TBTC: TBR = 0) when the timebase timer output is selected for the count clock. The watchdog timer counter is also cleared as soon as the watch prescaler is cleared (WPCR: WCLR = 0) when the watch prescaler is selected for the count clock. Thus, if the counter used as the count clock (timebase timer or watch prescaler) is cleared repeatedly within the watchdog timer interval time, it does not function as the watchdog timer. Reference: If a transition to the sleep mode, stop mode, or watch mode occurs, the counter of the watchdog timer is cleared and will not operate until normal operation (RUN state) is resumed. 156 6.2 Configuration of the Watchdog Timer 6.2 Configuration of the Watchdog Timer The watchdog timer is made up of the following six blocks: * Count clock selector * Watchdog timer counter * Reset control circuit * Watchdog timer clear selector * Counter clear control circuit * Watchdog timer control register (WDTC) I Block Diagram of the Watchdog Timer Figure 6.2-1 Block Diagram of the Watchdog Timer Watchdog control register (WDTC) CS WTE3 WTE2 WTE1 WTE0 221/FCH (Timebase timer output) 214/FCL (Watch prescaler output) Clear signal from the timebase timer Clear signal from the watch prescaler Sleep mode start Stop mode start Watch mode start FCH: Main clock oscillation FCL: Subclock oscillation Watchdog timer Count clock selector Clear Start Overflow Reset control circuit 1-bit counter RST Watchdog timer clear selector Counter clear control circuit Count clock selector The count clock selector selects the count clock of the watchdog timer counter. As the count clock, the output of either the timebase timer or the watch prescaler can be selected. Watchdog timer counter (1-bit counter) The watchdog timer counter is a 1-bit counter whose count clock is the output of either the timebase timer or the watch prescaler. 157 CHAPTER 6 WATCHDOG TIMER Reset control circuit The reset control circuit generates a reset signal to CPU when an overflow of the watchdog timer counter occurs. Watchdog timer clear selector The watchdog timer clear selector selects the watchdog timer clear signal from the timebase timer or watch prescaler simultaneously with the count clock selector. Counter clear control circuit The counter clear control circuit controls the watchdog timer counter clearing and operation stop. Watchdog timer control register (WDTC) The watchdog timer control register is used to select the count clock and activate/clear the watchdog timer counter. Since this register is write only, bit manipulation instructions cannot be used. 158 6.3 Watchdog Timer Control Register (WDTC) 6.3 Watchdog Timer Control Register (WDTC) The watchdog timer Control Register (WDTC) is used to activate/clear the watchdog timer. I Watchdog Timer Control Register (WDTC) Figure 6.3-1 Watchdog Timer Control Register (WDTC) Address 0 0 0 9H bit7 CS W bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0---XXXXB WTE3 WTE2 WTE1 WTE0 W W W W WTE3 WTE2 WTE1 WTE0 0 1 0 1 Watchdog control bit - Activate watchdog timer (for the 1st write after reset) - Clear watchdog timer (for the 2nd and later write after reset) No operation Otherwise CS 0 Count clock switch bit Timebase timer output cycle (221/FCH *1) 14/FCL *2) W : write only Watch prescaler output cycle (2 1 : Unused X : Undefined : Initial value (Note) Since this register is write only, bit manipulation instructions cannot be used. *1: FCH : Main clock oscillation *2: FCL : Subclock oscillation 159 CHAPTER 6 WATCHDOG TIMER Table 6.3-1 Explanation of the Functions of Each Bit of the Watchdog Timer Control Register (WDTC) Bit name * Function Select the count clock of the watchdog timer when activating the watchdog timer. * As the count clock, the output of either the timebase timer or the watch prescaler can be selected. Note: * To use the subclock mode, select the output of the watch prescaler. * Select the count clock simultaneously with activation of the watchdog timer and do not change it after the activation. * Bit manipulation instructions cannot be used. * * * The read value is undefined. Writing has no effect on operation. Bit 7 CS: Count clock switch bit Bit 6 Bit 5 Bit 4 Unused bist Bit 3 Bit 2 Bit 1 Bit 0 WTE3, WTE2, WTE1, WTE0: Watchdog control bit If "0101B" is written into these bits, the watchdog timer is activated (the 1st write after reset) or cleared (the 2nd or later write after reset). * Writing anything other than "0101B" does not affect operations. Note: "1111B" is read. Bit manipulation instructions cannot be used. 160 6.4 Operation of the Watchdog Timer 6.4 Operation of the Watchdog Timer The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. I Operation of the Watchdog Timer Activating the watchdog timer * The watchdog timer can be activated by writing the 1st "0101B" into the watchdog control bits (WDTC: WTE3 to 0) of the watchdog timer control register after a reset. At this time, specify the count clock switch bit (WDTC: CS) simultaneously. A watchdog timer that is activated can only be stopped by a reset. * Clearing the watchdog timer * The counter of the watchdog timer can be cleared by writing the 2nd or subsequent "0101B" into the watchdog control bits (WDTC: WTE3 to 0) of the watchdog timer control register after a reset. If the counter is not cleared within the interval time of the watchdog timer, an overflow of the counter occurs and an internal reset signal of the four instruction cycles is generated. * Watchdog timer interval time The interval time is changed by the timing of clearing the watchdog timer. Figure 6.4-1 "Watchdog Timer Clearing and Interval Time" shows the relations between the clearing timing of the watchdog timer and the interval time when the output of the timebase timer is selected as the count clock (if the main clock oscillation is 10 MHz). 161 CHAPTER 6 WATCHDOG TIMER Figure 6.4-1 Watchdog Timer Clearing and Interval Time Minimum time Timebase timer count clock output Watchdog clear Watchdog 1 bit counter Overflow 209.7ms Watchdog reset Maximum time Timebase timer count clock output Watchdog clear Watchdog 1 bit counter Watchdog reset 419.4ms Overflow 162 6.5 Notes on Using the Watchdog Timer 6.5 Notes on Using the Watchdog Timer The following describes the precautions to take when using the watchdog timer. I Notes on Using the Watchdog Timer Stopping the watchdog timer A watchdog timer that is activated can only be stopped by a reset. Selecting the count clock The count clock switch bit (WDTC: CS) can be rewritten only if "0101B" is written into the watchdog control bits (WDTC: WTE3 to 0) when the watchdog timer is activated. Thus, a write operation by bit manipulation instructions is not possible. Do not change the settings after activation. Since the main clock oscillation stops in subclock mode, the timebase timer does not operate. To enable operation of the watchdog timer in subclock mode, the watch prescaler (WDTC: CS=1) must be selected as the count clock in advance. Clearing the watchdog timer * * If the counter (timebase timer or watch prescaler) used as the count clock of the watchdog timer is cleared, the counter of the watchdog timer is cleared at the same time. If a transition to the sleep mode, stop mode, or watch mode occurs, the counter of the watchdog timer is cleared. Precautions when creating a program When creating a program in which the watchdog timer is cleared repeatedly in the main loop, the processing time of the main loop including interrupt processing must be equal to or less than the minimum watchdog timer interval time. Operations in subclock mode If a watchdog reset occurs in subclock mode, operation starts in main clock mode after taking the oscillation stabilization wait time. At this time, a reset signal is output during oscillation stabilization wait time. 163 CHAPTER 6 WATCHDOG TIMER 6.6 Program Example of the Watchdog Timer The following shows a program example in which the watchdog timer is used. I Program Example of the Watchdog Timer Processing specifications * * * Select the watch prescaler just after starting the program to activate the watchdog timer. Clear the watchdog timer each time in a loop of the main program. The main loop must make a round in less than the interval minimum time (about 209.7 ms for 10 MHz operation), including the interrupt processing time, of the watchdog timer. 164 6.6 Program Example of the Watchdog Timer Coding example (comply with Softune V1) EQU 00009H ; Address of the watchdog timer control register EQU 10000101B DSEG ABS ; [DATA SEGMENT] ORG 0FFFEH RST_V DW PROG ; Setting reset vector VECT ENDS ;----Main program---------------------------------------------------------------CSEG ; [CODE SEGMENT] PROG ; Initialization routine for reset MOVW SP,#0280H ; Setting initial value of stack pointer (for interrupt) : Initializing interrupt or other peripheral functions : INIT MOV WDTC,#WDT_CLR ; Activating watchdog timer Selection of the watch prescaler as the count clock : MAIN MOV WDTC,#WDT_CLR ; Clearing watchdog timer : User processing (interrupt may occur in this processing.) : JMP MAIN ; Ensure that the time necessary for running the loop is shorter than the minimum time interval of the watchdog timer. ENDS ;-------------------------------------------------------------------------------END WDTC WDT_CLR VECT 165 CHAPTER 6 WATCHDOG TIMER 166 CHAPTER 7 WATCH PRESCALER This chapter describes the functions and operations of the watch prescaler. 7.1 "Overview of the Watch Prescaler" 7.2 "Configuration of the Watch Prescaler" 7.3 "Watch Prescaler Control Register (WPCR)" 7.4 "Watch Prescaler Interrupt" 7.5 "Operation of the Watch Prescaler" 7.6 "Notes on Using the Watch Prescaler" 7.7 "Program Example of the Watch Prescaler" 167 CHAPTER 7 WATCH PRESCALER 7.1 Overview of the Watch Prescaler The watch prescaler is a 17-bit free-run counter that counts up in synchronization with the subclock generated in the clock generator and has an interval timer function that provides for the selection of six kinds of interval time. The watch prescaler also supplies the timer output of subclock oscillation stabilization wait time and the operating clock of the watchdog and other timers. I Interval Timer Function (Watch Interrupt) The interval timer function is a function used to generate an interrupt repeatedly at regular intervals using the subclock as the count clock. * * * An interrupt is generated by divide-by output for the interval timer of the watch prescaler. Six kinds of divide-by output (interval time) for the interval timer can be selected. The counter of the watch prescaler can be cleared. Table 7.1-1 "Interval Time of the Watch Prescaler" lists the interval time of the watch prescaler. Table 7.1-1 Interval Time of the Watch Prescaler Subclock cycle Interval time 210/FCL (31.25 ms) 213/FCL (0.25 s) 1/FCL (Approx. 30.5 s) 214/FCL (0.50 s) 215/FCL (1.00 s) 216/FCL (2.00 s) 217/FCL (4.00 s) FCL: Subclock oscillation Values in ( ) represent the interval time when the subclock oscillation is operating at 32.768 kHz. Note: The watch prescaler cannot be used when the single clock system is selected for option setting. 168 7.1 Overview of the Watch Prescaler I Clock Supply Function The clock supply function of the watch prescaler is a function used to supply the timer output (one) for oscillation stabilization wait time of the subclock and the clock for the watchdog timer. Table 7.1-2 "Clocks Supplied from the Watch Prescaler" lists the clock cycles supplied to each peripheral function from the watch prescaler. Table 7.1-2 Clocks Supplied from the Watch Prescaler Subclock supply destination Subclock oscillation stabilization wait time Watchdog timer Subclock cycle 215/FCL (1.00 s) 214/FCL (0.50 s) Remarks Do not make a transition to the subclock mode during oscillation stabilization wait time Count-up clock of the watchdog timer FCL: Subclock oscillation Values in ( ) represent the subclock cycles when the subclock oscillation is operating at 32.768 kHz. Reference: Because the oscillation cycles are unstable just after the oscillation starts, the oscillation stabilization wait timer serves as a guideline. 169 CHAPTER 7 WATCH PRESCALER 7.2 Configuration of the Watch Prescaler The watch prescaler comprises the following blocks: * watch prescaler counter * Counter clear circuit * Interval timer selector * watch prescaler control register (WPCR) I Block Diagram of the Watch Prescaler Figure 7.2-1 Block Diagram of the Watch Prescaler Watch prescaler counter To watchdog timer 3 24 0 FCL 21 1 22 2 23 4 25 5 26 6 27 7 28 8 29 9 210 10 211 11 12 212 213 13 214 14 215 15 216 16 217 To oscillation stabilization wait timer selector in clock controller Interval timer selector Watchdog timer clear IRQF watch prescaler interrupt Watch prescaler control register (WPCR) WIF WIE WS2 WS1 Counter clear circuit Power-on reset Stop mode start (in subclock mode) WS0 WCLR FCL: Subclock oscillation Values in ( ) represent the cycles when the subclock oscillation is operating at 32.768 kHz. Watch prescaler counter 17-bit up-counter using the subclock oscillation as the count clock. Counter clear circuit The counter clear circuit clears the counter when, in addition to the setting by the WPCR register (WPCR: WCLR=0), a transition to the sub-stop mode (STBC: STP=1) or an optional power-on reset occurs. Interval timer selector Circuit to select one divide-by output from four kinds of divide-by output from the watch prescaler counter. The falling edges of the selected divide-by output become an interrupt 170 7.2 Configuration of the Watch Prescaler source. Watch prescaler control register (WPCR) This register is used to select the interval time, clear the counter, control interrupts, and check status. 171 CHAPTER 7 WATCH PRESCALER 7.3 Watch Prescaler Control Register (WPCR) The watch prescaler control register (WPCR) is a register used to select the interval time, clear the counter, control interrupts, and check status. I Watch Prescaler Control Register (WPCR) Figure 7.3-1 Watch Prescaler Control Register (WPCR) Address 0 0 0 BH bit7 WIF R/W bit6 WIE R/W bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00--0000B WS2 WS1 R/W R/W WS0 WCLR R/W R/W WCLR Watch prescaler clear bit Read Write Clear the watch prescaler No change and does not affect others 31.25 ms 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s 0 1 "1" is always read WS2 WS1 WS0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Watch interrupt interval time select bit 210/FCL 213/FCL 214/FCL 215/FCL 216/FCL 217/FCL FCL: Subclock oscillation WIE 0 1 Interrupt request enable bit Prohibit interrupt request output Allow interrupt request output Watch interrupt request flag bit Read No interval interrupt Interval interrupt present Write Clear this bit No change and does not affect others WIF 0 1 R/W: read/write enabled - : Unused : Initial value 172 7.3 Watch Prescaler Control Register (WPCR) Table 7.3-1 Explanation of the Functions of Each Bit of the Watch Prescaler Control Register (WPCR) Bit name * Bit 7 WIF: Watch interrupt request flag bit * * * * * * * * * * * Function "1" is set by the falling edges of the selected divide-by output for interval timer. If both this bit and the interrupt request enable bit (WIE) are "1", an interrupt request is output. This bit is cleared if "0" is written into this bit. If "1" is written, no change occurs and no operation is affected. Bit to allow/prohibit interrupt request output to CPU. If both this bit and the watch interrupt request flag bit (WIF) are "1", an interrupt request is output. The read value is undefined. Writing has no effect on operation. Bits to select the interval timer cycle Bits for the interval timer of the counter of the watch prescaler are specified. Six kinds of interval time can be selected. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 WIE: Interrupt request enable bit Unused bits WS2, WS1, WS0: Watch interrupt interval time select bit Bit 0 WCLR: watch prescaler clear bit Bit to clear the counter of the watch prescaler If "0" is written into this bit, the counter is cleared to "0000H". If "1" is written, no change occurs and no operation is affected. Reference: "1" is always read. 173 CHAPTER 7 WATCH PRESCALER 7.4 Watch Prescaler Interrupt The watch prescaler generates interrupt requests using the falling edges of the selected divide-by output (interval timer function). I Interrupt when the Interval Timer Function is Active (Watch Interrupt) The counter for the watch prescaler counts up using the subclock oscillation. When the specified interval time passes, if not in main stop mode, the watch interrupt request flag bit (WPCR: WIF=1) is set to "1". At this time, if the interrupt request enable bit is set (WPCR: WIE=1), an interrupt request to CPU (IRQF) is issued. Clear the interrupt request to "0" by writing "0" into the WIF bit using an interrupt processing routine. The WIF bit is set whenever the specified divide-by output falls regardless of the value of the WIE bit. Note: To allow interrupt request output (WPCR: WIE=1) after releasing a reset, clear (WPCR: WIF=0) the WIF bit at the same time. Reference: If the WIE bit is changed from prohibition to permission (WPCR: WIE=0 --> 1) when the WIF bit is "1", an interrupt request is issued immediately. If the counter clear (WPCR: WCLR=0) and an overflow of the selected bit occur at the same time, the WIF bit is not set. I Oscillation Stabilization Wait Time and Watch Interrupts If an interval time period shorter than the oscillation stabilization wait time of the subclock is set, a watch interrupt request (WPCR: WIF=1) of the watch prescaler is issued when returning from the sub-stop mode following an external interrupt. In this case, prohibit (WPCR: WIE=0) interrupts of the watch prescaler when making a transition to the sub-stop mode. I Register and Vector Table Related to the Watch Prescaler Interrupts Table 7.4-1 "Register and Vector Table Related to the Watch Prescaler Interrupts" lists the register and vector table related to the watch prescaler interrupts. Table 7.4-1 Register and Vector Table Related to the Watch Prescaler Interrupts Interrupt name IRQF Interrupt level setting register Register ILR4 (007EH) Bit to be set LF1 (bit 7) LF0 (bit 6) Vector table address Upper FFDCH Lower FFDDH For interrupt operations, see Section 3.4.2 "Interrupt Processing". 174 7.5 Operation of the Watch Prescaler 7.5 Operation of the Watch Prescaler The watch prescaler operates to provide the interval timer function . I Operation of the Interval Timer Function (Watch Prescaler) The setting in Figure 7.5-1 "Setting of the Interval Timer Function" is required for the operation of the interval timer function. Figure 7.5-1 Setting of the Interval Timer Function bit7 WPCR WIF 0 bit6 WIE 1 bit5 bit4 bit3 WS2 bit2 WS1 bit1 bit0 : Bit used 1 : 1 is set 0 : 0 is set WS0 WCLR 0 The 17-bit counter of the watch prescaler continues to count up the subclock provided the subclock oscillates. If the counter is cleared (WPCR: WCLR=0), it starts to count up from "0000H". When "1FFFEH" is reached, counting continues starting from "0000H". When the time set with the watch interrupt interval time selection bit is reached during count-up, if the main stop mode is not in effect, "1" is set in the watch interrupt request flag bit (WPCR: WIF). That is, starting with the time when cleared, a watch interrupt request is generated at regular intervals of the selected time. I Operation of the Clock Supply Function The watch prescaler is also used as a timer to generate the oscillation stabilization wait time of the subclock. Counting of the oscillation stabilization wait time of the subclock (215/FCL, FCL: subclock oscillation) starts when the watch prescaler is cleared and ends when the highest bit falls. 175 CHAPTER 7 WATCH PRESCALER I Operations of the Watch Prescaler Figure 7.5-2 "Operations of the Watch Prescaler" shows the counter values if a transition to the sleep mode or stop mode occurs, or the counter clearing is requested when the interval timer function is operating in subclock mode. The transition to the watch mode is the same as that to the sub-sleep mode. Figure 7.5-2 Operations of the Watch Prescaler Counter value 1FFFFH Clearing by transition to the sub-stop mode 0000H Subclock oscillation stabilization wait time Power-on reset WIF bit WIE bit SLP bit (STBC register) STP bit (STBC register) Stop release by an external interrupt If "11B" is set to the interrupt interval time select bits (WPCR: WS1, WS0) of the watch prescaler control register (215/FCL) Sub-sleep Subclock oscillation stabilization Counter clear wait time (WPCR: WCLR=0) Clearing by an interrupt processing routine Interval cycle Sleep release by IRQF Sub-stop 176 7.6 Notes on Using the Watch Prescaler 7.6 Notes on Using the Watch Prescaler The following describes the precautions when using the watch prescaler. The watch prescaler cannot be used when a single clock source is specified with the option setting. I Notes on Using the Watch Prescaler Precautions when setting the watch prescaler in programs It is impossible to return from interrupt processing if the interrupt request flag bit (WPCR: WIF) is "1" and the interrupt request enable bit is set (WPCR: WIF=1). The WIF bit must be cleared. Clearing the watch prescaler The watch prescaler is cleared, in addition to clearing by the watch prescaler clear bit (WPCR: WCLR=0), when the oscillation stabilization wait time of the subclock is required. If the watch prescaler is selected (WDTC: CS=1) as the count clock of the watchdog timer, the watchdog timer is also cleared when the watch prescaler is cleared. Using the watch prescaler as a timer for the oscillation stabilization wait time Since the subclock oscillation is stopped when the power is turned on or operating in sub-stop mode, the oscillator takes the oscillation stabilization wait time using the watch prescaler after activating operations. Do not make a transition from the main clock mode to the subclock mode during oscillation stabilization wait time, such as just after power-on. The oscillation stabilization wait time of the subclock is fixed. For details, see Section 3.6.5 "Oscillation Stabilization Wait Time". Precautions when using watch interrupts In main stop mode, the watch prescaler performs a count operation but a watch interrupt (IRQF) does not occur. Precautions when using the peripheral functions that use clocks supplied from the prescaler. If the counter of the watch prescaler is cleared, the "H" level of the clock supplied by the watch prescaler is short and its "L" level may be longer by a maximum of 1/2 cycle because the output originates from the initial state. Though the clock for the watchdog timer is also output from the initial state, the watchdog timer works in normal cycles because the counter of the watchdog timer is cleared simultaneously. 177 CHAPTER 7 WATCH PRESCALER 7.7 Program Example of the Watch Prescaler The following shows a program example of the watch prescaler. I Program Example of the Watch Prescaler Processing specifications Generate the watch interrupt of 215/FCL (FCL: subclock oscillation) repeatedly. The interval time is about 1 s (for 32.768 kHz operation). Coding example WPCR WIF ILR4 EQU EQU EQU 000BH WPCR:7 007EH ; Address of the watch prescaler control register ; Definition of watch interrupt request flag bit ; Address of the interrupt level setting register ; [DATA SEGMENT] INT_V DSEG ABS ORG 0FFDCH IRQF DW WARI ; Setting interrupt vector INT_V ENDS ;----Main program----------------------------------------------------------CSEG ; [CODE SEGMENT] ; Stack pointer (SP) and other are assumed to have been initialized : CLRI ; Interrupt disable MOV ILR4,#10111111B ; Setting interrupt level (level 2) MOV WPCR,#01000110B ; Clearing interrupt request flag, enabling interrupt request output, selecting 215/FCL, and clearing watch prescaler SETI ; Interrupt enable : ;----Interrupt program-----------------------------------------------------WARI CLRB WIF ; Clearing interrupt request flag PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ; -------------------------------------------------------------------------END 178 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS This chapter describes the functions and operation of the 2-channel 8-bit PWM timer. 8.1 "Overview of the 2-Channel 8-Bit PWM Timer (Interval Timer Function)" 8.2 "Overview of the 2-Channel 8-Bit PWM Timer (PWM Timer Function)" 8.3 "Configuration of the 2-Channel 8-Bit PWM Timer" 8.4 "Pins of the 2-Channel 8-Bit PWM Timer" 8.5 "Registers of the 2-Channel 8-Bit PWM Timer" 8.6 "2-Channel 8-Bit PWM Timer Interrupts" 8.7 "Interval Timer Function Operation" 8.8 "Explanation of the 2-Channel 8-Bit PWM Timer Operation in 8-Bit PWM Mode" 8.9 "2-Channel 8-Bit PWM Timer Operation in 7-Bit PWM Mode" 8.10 "Explanation of the 2-Channel 8-Bit PWM Timer Operation in CH12PWM Mode" 8.11 "Explanation of Prescaler Operation of 2-Channel 8-Bit PWM Timer" 8.12 "State of 2-Channel 8-Bit PWM Timer Operation in Each Mode" 8.13 "Notes on Using the 2-Channel 8-Bit PWM Timer Usage" 8.14 "Program Examples of the 2-Channel 8-Bit PWM Timer (Interval Timer Function)" 8.15 "Program Examples of the 2-Channel 8-Bit PWM Timer (PWM Timer Function)" 179 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.1 Overview of the 2-Channel 8-Bit PWM Timer (Interval Timer Function) The 2-channel 8-bit PWM timer consists of two 8-bit PWM timers (CH1 and CH2) that increment the counter value in synchronization with four internal count clocks. CH1 and CH2 each have an interval timer function that outputs square waves and an 8- or 7-bit resolution PWM timer function. CH1 and CH2 can select any of these functions. The interval timer function provides two modes: 8-bit timer mode and CK12 mode. In 8-bit timer mode, CH1 and CH2 are used separately. In CK12 mode, CH1 and CH2 are used combined. The output cycles of CH1 and CH2 can be used as UART transfer clocks. I Interval Timer Function (Square Wave Output Function) The interval timer function is used to repeatedly generate interrupts at arbitrary time intervals. This function can also output square waves at an arbitrary frequency because it can invert the output level of a pin (PT01, PT02 pin) each time an interrupt occurs. 8-bit timer mode * * * In 8-bit timer mode, the CH1 and CH2 8-bit PWM timers operate independently. Interval timer operation is possible with 1 to 28 count clock cycles. One of four count clocks can be selected. Table 8.1-1 "Interval Times and Square Wave Output Ranges (CH1, CH2)" lists the interval times and square wave output ranges. Table 8.1-1 Interval Times and Square Wave Output Ranges (CH1, CH2) Count clock cycle 1tinst Internal count clock 8tinst 16tinst 64tinst Interval time 1tinst to 28tinst 23tinst to 211tinst 24tinst to 212tinst 26tinst to 214tinst Square wave output range (Hz) 1/(2tinst) to 1/2(9tinst) 1/(24tinst) to 1/2(12tinst) 1/(25tinst) to 1/2(13tinst) 1/(27tinst) to 1/2(15tinst) tinst: Instruction cycle (affected by the clock mode and other factors) 180 8.1 Overview of the 2-Channel 8-Bit PWM Timer (Interval Timer Function) Reference: [Example of calculating interval time and square wave frequency] When the oscillation (FCH) of the main clock is 10 MHz, the value of the PWM compare register (COMR) is DDH(221), and the count clock cycle is 1 tinst, and the interval timer function is used continuously without modifying the COMR register value, the interval time and the square wave frequency output to the PWM pin are calculated as shown below. Note, however, that the calculated values are valid only when the fastest clock (SYCC: CS1, CS0 = 11B, 1 instruction cycle = 4/FCH) available in main clock mode (SYCC: SCS = 1) is selected with the system clock control register (SYCC). Interval time = (1 x 4/FCH) x (COMR register value + 1) = (4/10MHz) x (221+1) = 88.8 s Output frequency = FCH/ (1 x 8 x (COMR register value + 1)) = 10MHz/ (8 x (221 + 1)) 5.63kHz CK12 mode CK12 mode is the mode in which CH1 and CH2 are combined. In this mode, the CH1 square wave output is used as the CH2 count clock. * * * For CH1 and CH2, interval timer operation from 1 to 28count clock cycles is possible. For CH1, one of four count clocks can be selected. The CH2 count clock is provided by the CH1 square wave output. Table 8.1-2 "Interval Times and Square Wave Output Ranges" lists the interval times and square wave output ranges. Table 8.1-2 Interval Times and Square Wave Output Ranges Count clock cycle 1tinst CH1 Internal count clock 8tinst 16tinst 64tinst CH2 CH1 square wave output 2tinst to 215tinst Interval time 1tinst to 28tinst 23tinst to 211tinst 24tinst to 212tinst 26tinst to 214tinst 2tinst to 223tinst Square wave output range (Hz) 1/(2tinst) to 1/2(9tinst) 1/(24tinst) to 1/2(12tinst) 1/(25tinst) to 1/2(13tinst) 1/(27tinst) to 1/2(15tinst) 1/(22tinst) to 1/2(24tinst) tinst: Instruction cycle (affected by the clock mode and other factors) 181 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS Reference: [Example of calculating the interval time and square wave frequency] When the oscillation (FCH) of the main clock is 10 MHz, the values of both PWM compare registers 1 and 2 (COMR1 and COMR2) are "DDH(221)," and the CH1 count clock cycle is 1 tinst, and the interval timer function is used continuously without modifying the values of the COMR registers, the interval time and the square wave frequency output to the PWM pin are calculated as shown below: Note, however, that the calculated values are valid only when the fastest clock (CS1, CS0 = 11B, 1 instruction cycle = 4/FCH) available in main clock mode (SCS = 1) is selected with the system clock control register (SYCC). CH1 Interval time = (1 x 4/FCH) x (COMR1 register value + 1) = (1 x 4/10MHz) x (221+1) = 88.8 s CH1 output frequency = FCH/ (1 x 8 x (COMR1 register value + 1)) = 10MHz/ (1 x 8 x (221 + 1)) 5.63kHz CH2 Interval time = (1 x 4/CH1 output frequency) x (COMR2 register value + 1) = (1 x 4/5.63kHz) x (221+1) = 157.7ms CH2 output frequency = CH1 output frequency/ (1 x 8 x (COMR2 register value + 1)) = 5.63kHz/ (1 x 8 x (221 + 1)) 3.17Hz 182 8.2 Overview of the 2-Channel 8-Bit PWM Timer (PWM Timer Function) 8.2 Overview of the 2-Channel 8-Bit PWM Timer (PWM Timer Function) The 2-channel 8-bit PWM timer consists of two 8-bit PWM timers (CH1 and CH2) that increment the counter value in synchronization with four internal count clocks. CH1 and CH2 each have an interval timer function that outputs square waves and an 8- or 7-bit resolution PWM timer function. CH1 and CH2 can select any of these functions. I Overview of 2-Channel 8-Bit PWM Timer (PWM Timer Function) The PWM timer function supports 8-bit PWM mode, 7-bit PWM mode (high-speed mode), and CH12PWM mode. The 8-bit PWM mode uses CH1 and CH2 separately. The CH12PWM mode generates a PWM wave on the assumption that CH1 is the "L" width and CH2 is a cycle. It is also possible to operate CH1 in 8-bit timer mode and select square wave output as the CH2 count clock (CK12PWM mode). The 2-channel 8-bit PWM timer can be used as a D/A converter by connecting a low-pass filter to the PWM output. Figure 8.2-1 Example of Using the 2-Channel 8-Bit PWM Timer as a D/A Converter by Connecting a LowPass Filter to PWM Output PWM output PTO pin Analog output (Va) Analog output waveform Relationship between analog output voltage and PWM output waveform Tr indicates the time required until the output becomes stable. PWM output waveform 183 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS Reference: [Example of calculating the PWM wave (CH12PWM mode)] When the oscillation (FCH) of the main clock is 10 MHz, the values of the PWM compare registers (COMR1 and COMR2) are 01H and 03H, respectively, and each count clock cycle is 1 tinst, the PWM wave is calculated as shown below. Note, however, that the calculated values are valid only when the fastest clock (SYCC: CS1, CS0 = 11B, 1 instruction cycle = 4/FCH) of the main clock (SYCC: SCS = 1) mode is selected with the system clock control register (SYCC). "L" width = (1 x 4/FCH) x (COMR1 register value + 1) = (1 x 4/10MHz) x (1+1) = 0.8 s 1-cycle width = (1 x 4/FCH) x (COMR2 register value + 1) = (1 x 4/10MHz) x (3+1) = 1.6 s I PWM Timer Function The PWM timer function controls the "H" width of one cycle or controls the "L" width and cycles independently to output a PWM wave to the PT01 or PT02 pin. This function can also be used to provide a D/A converter by connecting a low-pass filter to the PWM output. When used independently, CH1 and CH2 each can select 8-bit PWM mode and 7-bit PWM mode (high-speed mode). 8-bit PWM mode * * PWM waves can be output at a duty ratio of 0 to 99.6% because the "H" width of one cycle can be controlled at a resolution of 1/256. A PWM wave cycle is 28 count clock cycles. Four PWM wave cycles are provided, one of which can be selected. 7-bit PWM mode (high-speed mode) * * PWM waves can be output at a duty ratio of 0 to 99.2% because the "H" width of one cycle can be controlled at a resolution of 1/128. A PWM wave cycle is 27 (1/2 of 8-bit PWM mode) times the count clock cycle. Four PWM wave cycles are available, one of which can be selected. CK12PWM mode (8-bit PWM, 7-bit PWM) * * CH2 can select 8-bit PWM mode or 7-bit PWM mode. However, the count clock is provided by the CH1 square wave output. CH1 operates in 8-bit timer mode and can control PWM wave cycles. 184 8.2 Overview of the 2-Channel 8-Bit PWM Timer (PWM Timer Function) CH12PWM mode * * * * The "L" width of a PWM wave can be controlled for up to 28 count clock cycles for each of the four CH1 count clocks. PWM wave cycles can be controlled for up to 28 count clock cycles for each of the four CH2 count clocks. PWM waves can be usually controlled at a resolution of 1/256 and can be output at a duty ratio of 0 to 99.6%. PWM waves can be controlled up to a resolution of 1/214 (minimum), but the duty ratio is limited. PWM wave cycles in each mode Table 8.2-1 PWM Wave Cycles That Can Be Set by the PWM Timer Function Independent use of CH1, CH2 (normal mode) Count clock cycle Cycle in 8-bit PWM mode Cycle in 7bit PWM mode (highspeed mode) 27tinst 210tinst 211tinst 213tinst 28tinst to 222tinst CH12PWM mode "L" width (CH1) 1-cycle width (CH2) CH1 and CH2 in nonCK12PWM mode Internal count clock 1tinst 8tinst 16tinst 64tinst 28tinst 211tinst 212tinst 214tinst 29tinst to 223tinst 1tinst to 28tinst 23tinst to 211tinst 24tinst to 212tinst 26tinst to 214tinst 1tinst to 28tinst 23tinst to 211tinst 24tinst to 212tinst 26tinst to 214tinst CH2 in CK12PWM mode CH1 square wave output 2tinst to 215tinst tinst: Instruction cycle (affected by the clock mode and other factors) 185 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.3 Configuration of the 2-Channel 8-Bit PWM Timer The 2-channel 8-bit PWM timer consists of the following seven blocks: * Prescaler * 8-bit PWM timer 1 (CH1) * 8-bit PWM timer 2 (CH2) * PWM compare registers 1 and 2 (COMR1 and COMR2) * PWM control registers 1, 2, and 3 (CNTR1, CNTR2, and CNTR3) * CK12 selector * CH12PWM output control circuit I Block Diagram of 2-Channel 8-Bit PWM Timer Figure 8.3-1 Block Diagram of the 2-Channel 8-Bit PWM Timer Internal data bus PWM control register 2 (CNTR2) TPE1 TPE2 CK12 TIR1 TIR2 TIE1 TIE2 PWM control register 1 (CNTR1) PTX1 PTX2 P7M1 P7M2 SC11 SC10 SC21 SC20 PWM control register 3 (CNTR3) OE2 OE3 CH12 2 2 8-bit PWM timer 1 (CH1) COMR1 PWM compare register 1 COMR2 PWM compare register 2 8-bit PWM timer 2 (CH2) 7MOD OUT Comparator STOP X1 PWM 7MOD generation and output control OUT circuit 7MOD OUT Comparator PWM 7MOD generation and output control circuit OUT 1tinst X6 CLK X 16 X 64 PRESCALER Selector START CLK CLEAR 7MOD START 7MOD Selector 8-bit counter CLK CK12 CLEAR 8-bit counter P34/PT02 Selector OVERFLOW OVERFLOW Pin PT02 To UART SET CH2 PWM output control OUT circuit RESET Selector P37/PT01 Pin PT01 To UART 4 IRQ6 1 tinst: Instruction cycle IRQ5 Prescaler This circuit divides operating clocks for peripheral circuits. When any of the counter operation enable bits (CNTR2: TPE1 and TPE2) of PWM control register CNTR2 is "1," the prescaler operates and outputs four internal count clocks. 186 8.3 Configuration of the 2-Channel 8-Bit PWM Timer 8-bit PWM timer 1 (CH1) and 8-bit PWM timer 2 (CH2) Count clock selector: This circuit selects the four internal count clocks. The selected clock functions as the clock for incrementing the 8-bit counter. 8-bit counter: The 8-bit counter is incremented according to the count clock selected by the counter clock selector. Comparator: When the value of the 8-bit counter is 00H, the comparator latches the COMR register value. It also compares the 8-bit counter value with the latched COMR register value to detect a match. PWM generation and output control circuit: If a match is detected during operation as an interval timer, an interrupt request is not generated. If output pin control bit 2 (OE2 bit or OE3 bit of CNTR3) is "1" when an interrupt request is generated, the output control circuit inverts the output level of the PWM pin and at the same time clears the 8-bit counter. If a match is detected during operation as a PWM timer, the PWM generation circuit changes the output level of the PWM pin from High to Low. If the 8-bit counter overflows later, the output level of the PWM pin changes to High. PWM compare registers 1 and 2 (COMR1 and COMR2) These registers are used to set the values to be compared with the values of the 8-bit counter. PWM control registers 1, 2, and 3 (CNTR1, CNTR2, and CNTR3) CNTR1, CNTR2, and CNTR3 are used to select an operating mode, enable and disable operations, set count clocks, control interrupts, and check interrupt states. If PWM timer mode (CNTR1: PTX1 or PTX2 = 1) is selected as the operating mode, clearing of an 8-bit counter by the match detection signal from the comparator and interrupt requests are disabled. CK12 selector This input clock switching circuit changes the input clock of 8-bit PWM timer 2 (CH2) to the counter clock selector output or the square wave output of 8-bit PWM timer 1 (CH1). CH12PWM output control circuit The CH12PWM output control circuit controls the "L" width (L --> H) and cycle (H --> L) of a PWM wave according to outputs from CH1 and CH2 in CH12PWM mode. Interrupt related to the 2-channel 8-bit PWM timer * IRQ5: If the output of interrupt requests is enabled (CNTR2: TIEI = 1) when the counter value matches the value set in COMR1 of the CH1 interval timer function, an interrupt request occurs. (Interrupt requests do not occur when the ordinary PWM function is operating.) IRQ6: If interrupt requests are enabled (CNTR2: TIE2 = 1) when the counter value matches the value set in the COMR2 register in the CH2 interval timer function, or in CH12PWM mode, an interrupt request occurs. (Interrupt requests do not occur when the ordinary PWM function is operating.) * 187 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.4 Pins of the 2-Channel 8-Bit PWM Timer This section describes 2-channel 8-bit PWM timer pins and provides a block diagram of the pins. I 2-Channel 8-Bit PWM Timer Pins The 2-channel 8-bit PWM timer pins consist of the P34/PT02 and P37/PT01 pins. P34/PT02 and P37/PT01 pins The P34 and P37 pins function as the general-purpose I/O ports. They also serve as interval or PWM timer outputs (PT01 and PT02). PT01, PT02 When the interval timer function is used, a square wave is output to these pins. When the PWM timer function is used, a PWM wave is output to these pins. When the resource output pin control bit is set to "1" (CNTR3: OE = 1), the P34/PT02 and P37/PT01 pins automatically function as output pins without reference to the values of the port data direction register output latch data (DDR: bit 1). That is, they function as PT01 and PT02 pins. 188 8.4 Pins of the 2-Channel 8-Bit PWM Timer I Block Diagram of the 2-Channel 8-Bit PWM Timer Pins Figure 8.4-1 Block Diagram of the 2-Channel 8-Bit PWM Timer Pins PDR (port data register) Stop and watch mode (SPL = 1) PDR read From resource output From resource output enabled (CNTR:OE3, CNTR:OE2) Pull-up resistor About 50 k Pull-up control resistor Internal data bus PDR read (for bit manipulation instructions) Pch Output latch PDR write Pch DDR (Port data direction register) Pin Nch Stop and watch mode (SPL = 1) DDR write P37/PT01 P34/PT02 DDR read SPL: This bit specifies the pin state of the standby control register (STBC). Reference: When "pull-up resistor available" is selected in the pull-up option setting register, the pin state in stop and watch mode (STBC: SPL = 1) is High (pull-up state), not high impedance. During a reset, however, pull-up is invalid and the pin state becomes Hi-z. 189 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.5 Registers of the 2-Channel 8-Bit PWM Timer This section describes 2-channel 8-bit PWM timer registers. I Registers of the 2-Channel 8-Bit PWM Timer Figure 8.5-1 Registers of the 2-Channel 8-Bit PWM Timer (PWM control registers 1, 2, 3) Address Initial value Address Initial value Address Initial value (PWM compare registers 1, 2) Address Initial value Address Initial value R/W W X : : : : Can be read and written Write only Unused Undefined Note: PWM compare registers 1 and 2 (COMR1 and COMR2) cannot use bit manipulation instructions because they are write-only registers. 190 8.5 Registers of the 2-Channel 8-Bit PWM Timer 8.5.1 PWM Control Register 1 (CNTR1) PWM control register 1 (CNTR1) is used to select an operating mode (interval timer operation or PWM timer operation) for the 2-channel 8-bit PWM timer and count clock. CNTR1 is also used to change the resolution of the PWM timer function. I PWM Control Register 1 (CNTR1) Figure 8.5-2 PWM Control Register 1 (CNTR1) Address Initial value CH2 clock selection bit CH1 clock selection bit CH2 PWM resolution change bit 8-bit PWM mode 7-bit PWM mode (high-speed mode) CH1 PWM resolution change bit 8-bit PWM mode 7-bit PWM mode (high-speed mode) CH2 operating mode selection bit Interval timer operation PWM timer operation CH1 operating mode selection bit Interval timer operation PWM timer operation tinst : Instruction cycle R/W : Can be read and written : Initial value 191 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS Table 8.5-1 Function of the PWM Control Register 1 (CNTR1) Bits Bit * PTX1: CH1 operating mode selection bit Description This bit is used to select CH1 interval timer operation or CH1 PWM timer operation. * If this bit is set to "0," CH1 interval timer operation is selected. If this bit is set to "1," CH1 PWM timer operation is selected. Note: Before writing this bit, stop counter operation (CNTR2: TPE1 = 0), disable interrupt requests (CNTR2: TIE1 = 0), and clear the request level flag bit (CNTR2: TIR1 = 0). When the CH12 bit of CNTR3 is "1" (CH12 mode), this bit is meaningless. * PTX2: CH2 operating mode selection bit This bit is used to select CH2 interval timer operation or CH2 PWM timer operation. * If this bit is set to "0," CH2 interval timer operation is selected. If this bit is set to "1," CH2 PWM timer operation is selected. Note: Before writing this bit, stop counter operation (CNTR2: TPE2 = 0), disable interrupt requests (CNTR2: TIE2 = 0), and clear the request level flag bit (CNTR2: TIR2 = 0). When the CH12 bit of CNTR3 is "1" (CH12 mode), this bit is meaningless. * bit5 P7M1: CH1 PWM resolution change bit For CH1 PWM timer operation, this bit is used to change 8-bit PWM mode to 7-bit PWM mode (high-speed mode) or vice versa. * Setting this bit to "0" changes 7-bit PWM mode to 8-bit PWM mode. Setting this bit to "1" changes 8-bit PWM mode to 7-bit PWM mode. Note: For interval timer operation, do not set this bit to "1." * bit4 P7M2: CH2 PWM resolution change bit For CH2 PWM timer operation, this bit is used to change 8-bit PWM mode to 7-bit PWM mode (high-speed mode) or vice versa. * Setting this bit to "0" changes 7-bit PWM mode to 8-bit PWM mode. Setting this bit to "1" changes 8-bit PWM mode to 7-bit PWM mode. Note: For interval timer operation, do not set this bit to "1." * bit3 bit2 SC11, SC10: CH1 clock selection bits These bits are used to select the count clocks for the CH1 interval timer function and CH1 PWM timer function. * One out of four internal count clocks can be selected. Note: Do not change from the CH1 interval timer function to the CH1 PWM timer function or vice versa while the CH1 counter is operating (CNTR2: TPE1 =1). These bits are used to select the count clocks of the CH2 interval timer function and CH2 PWM timer function. * One out of four internal count clocks can be selected. Note: Do not change from the CH2 interval timer function to the CH2 PWM timer function or vice versa while the CH2 counter is operating (CNTR2: TPE2 = 1). * bit1 bit0 SC21, SC20: CH2 clock selection bits bit7 bit6 192 8.5 Registers of the 2-Channel 8-Bit PWM Timer 8.5.2 PWM Control Register 2 (CNTR2) PWM control register 2 (CNTR2) is used to enable and disable 2-channel 8-bit PWM timer operation, select a CK12 mode, control interrupts, and check interrupt states. I PWM Control Register 2 (CNTR2) Figure 8.5-3 PWM Control Register 2 (CNTR2) Address Initial value 000-0000B CH2 interrupt request enable bit Disables CH2 interrupt request output. Enables CH2 interrupt request output. CH1 interrupt request enable bit Disables CH1 interrupt request output. Enables CH1 interrupt request output. CH2 interrupt request flag bit During reading When the interval timer function is used When the PWM timer function is used During writing This bit is cleared. Unchanged; no effect elsewhere This bit remains unchanged The counter value matches (Other than in CH12PWM mode). the set value. The counter value does not match the set value. CH1 interrupt request flag bit During reading During writing When the PWM timer When the interval timer function is used function is used The counter value does not match the set value. The counter value matches the set value. This bit is This bit remains cleared. unchanged (Other than in Unchanged; CH12PWM mode). no effect elsewhere CH2 input clock change bit Clock to be selected by the SC21 and SC20 bits CH1 square wave output (CH12 mode) CH2 counter operation enable bit Stops CH2 counter operation. Starts CH2 counter operation. CH1 counter operation enable bit Stops CH1 counter operation. Starts CH1 counter operation. R/W : Can be read and written : Unused : Initial value 193 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS Table 8.5-2 Functions of PWM Control Register 2 (CNTR2) Bits Bit TPE1: CH1 counter operation enable bit TPE2: CH2 counter operation enable bit * * * * * * CK12: CH2 input clock change bit Description This bit is used to start and stop CH1 interval operation and PWM timer operation. Setting this bit to "1" starts the count operation. Setting this bit to "0" clears the counter value to 00H and stops the count operation. This bit is used to start and stop CH2 interval operation and PWM timer operation. Setting this bit to "1" starts the count operation. Setting this bit to "0" clears the counter value to 00H and stops the count operation. bit7 bit6 bit5 This bit is used to change the CH2 input clock. When this bit is set to "0," the clock selected by the SC21 and SC20 bits is used as the input clock. * When this bit is set to "1," CH1 square wave output is used as the input clock, and operation is in CK12 mode without reference to the values of the SC21 and SC20 bits. Note: When the CH12 bit of CNTR3 is "1" (CH12PWM mode) or the PTX1 bit of CNTR1 is "1" (CH1 PWM timer operation is selected), do not set this bit to "1." * * * The value read from this bit is undefined. Writing to this bit has no effect on operation. If the count value matches the value in PWM compare register 1 (COMR1) when the CH1 interval timer function is being used, this bit is set to "1." When this bit and the CH1 interrupt request enable bit (TIE1) are "1," an interrupt request is output to the CPU. If the PWM timer function is used in a mode other than CH12PWM mode, interrupt requests do not occur. Writing "0" clears this bit. Writing "1" has no effect. If the count value matches the value in PWM compare register 2 (COMR2) when the CH2 interval timer function and CH12PWM mode are being used, this bit is set to "1." When this bit and the CH2 interrupt request enable bit (TIE2) are "1," an interrupt request is output to the CPU. If the PWM timer function is used in a mode other than CH12PWM mode, interrupt requests do not occur. Writing "0" clears this bit. Writing "1" has no effect. bit4 Unused bit3 TIR1: CH1 interrupt request flag bit * * * * bit2 TIR2: CH2 interrupt request flag bit * * * * bit1 TIE1: CH1 interrupt request enable bit This bit is used to enable and disable the output of CH1 interrupt requests to the CPU. * When this bit and the CH1 interrupt request flag bit (TIR1) are "1," an interrupt request is output. Note: When the CH12 bit of CNTR3 is "1" (CH12PWM mode), disable the output of interrupt requests (TIE1 = 0). * * This bit is used to enable and disable the output of CH2 interrupt requests to the CPU. When this bit and the CH2 interrupt request flag bit (TIR2) are "1," an interrupt request is output. bit0 TIE2: CH2 interrupt request enable bit 194 8.5 Registers of the 2-Channel 8-Bit PWM Timer 8.5.3 PWM Control Register 3 (CNTR3) PWM control register 3 (CNTR3) is used to select CH12PWM mode for the 2-channel PWM timer and control output pins. I PWM Control Register 3 (CNTR3) Figure 8.5-4 PWM Control Register 3 (CNTR3) Address Initial value -000----B CH12PWM mode setting bit Normal mode CH12PWM mode Output pin control bit 3 Uses the P37/PWM1 pin as a general port (P42). Uses the P37/PWM1 pin in CH12PWM mode or as the CH1 interval timer or PWM output pin (PWM1). Output pin control bit 2 Uses the P43/PWM2 pin as a general port (P34). R/W : Can be read and written : Unused : Initial value Uses the P43/PWM2 pin as the CH2 interval timer or PWM output pin (PT02). 195 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS Table 8.5-3 Functions of PWM Control Register 3 (CNTR3) Bits Bit bit7 Unused * * * OE2: Output pin control bit 2 * Description The value read from this bit is undefined. Writing to this bit has no effect on operation. This bit is used to set whether the P34/PT02 pin is to be used as a general port or a dedicated pin. When this bit is set to "0," the P34/PT02 pin is used as a general port (P34). When this bit is set to "1," the P34/PT02 pin is used as a dedicated pin (PT02). The PT02 pin is a CH2 output pin. When the interval timer function is used, a square wave is output. When the PWM timer function is used, a PWM wave is output. This bit is used to set whether the P37/PT01 pin is used as a general port or a dedicated pin. When this bit is set to "0," the P37/PT01 pin is used as a general port (P37). When this bit is set to "1," the P37/PT01 pin is used as a dedicated pin (PT01). The PT01 pin is a CH1 output pin. When the interval timer function is used, a square wave is output. When the PWM timer function or CH12PWM mode is used, a PWM wave is output. bit6 * * OE3: Output pin control bit 3 * bit5 * * bit4 CH12: PWM mode setting bit This bit is used to switch from normal mode to CH12PWM mode or vice versa. * Setting this bit to "0" sets CH1 and CH2 to operate independently. Setting this bit to "1" selects CH12PWM mode in which the "L" width is specified in CH1 and a cycle is specified in CH2. * The operating mode selection bits (PTX1 and PTX2 bits of CNTR1) are meaningless in CH12PWM mode. Note: When the CK12 bit of CNTR2 is "1" (CK12 mode is set), do not set this bit to "1." When the TIE1 or TIE2 bit of CNTR2 is "1" (the CH1 or CH2 counter is operating), do not rewrite this bit. * * Values read from these bits are undefined. Writing to these bits has no effect on operation. bit3 bit2 bit1 bit0 Unused 196 8.5 Registers of the 2-Channel 8-Bit PWM Timer 8.5.4 PWM Compare Register 1 (COMR1) PWM compare register 1 (COMR1) is a CH1 data register. When the interval timer function is operating, the value set in COMR1 defines the interval time. When the normal PWM timer function is operating, the value is the "H" width of a pulse. When CH12PWM mode is used, the value is the "L" width of a pulse. I PWM Compare Register 1 (COMR1) Figure 8.5-5 "PWM Compare Register 1 (COMR1)" shows the bit configuration of COMR1. Bit manipulation instructions cannot be used for COMR1 because COMR1 is a write-only register. Figure 8.5-5 PWM Compare Register 1 (COMR1) Address COMR1 Initial value W : Write only X : Undefined * : This bit is meaningless when 7-bit PWM mode (high-speed mode) is used. When the interval timer is operating (8-bit timer mode and CK12 mode) The value to be compared with the counter value is set in COMR1, which is used to specify the interval time (square wave output frequency). When the value set in COMR1 matches the counter value, the counter is cleared and the interrupt request flag bit is set to "1" (TIR1 bit of CNTR2 = 1). The value written to COMR1 when the counter is operating takes effect starting with the next cycle (after match detection). Reference: The value set in COMR1 when the 8-bit timer or CK12 mode is in effect can be calculated from the expression shown below. Note that the instruction cycle is affected by the clock mode and gear function. Value set in COMR1 = interval time/(count clock cycle x instruction cycle) - 1 197 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS When the PWM timer is operating (8-bit PWM mode and 7-bit PWM mode) The value to be compared with the counter value is set in COMR1, which is used to specify the "H" width of a pulse. "H" level is output to the PWM pin until the value set in COMR1 matches the counter value. When the value set in COMR1 matches the counter value, "L" level is output until the counter value overflows. The value written to COMR1 when the counter is operating takes effect starting with the next cycle (after the counter value has overflowed). Reference: The value set in COMR1 when the PWM timer is operating and the PWM wave cycle can be calculated from the expressions shown below. Note that the instruction cycle is affected by the clock mode and gear function. * 8-bit PWM mode Value set in COMR1 = duty ratio (%) x 256 PWM wave cycle = count clock cycle x instruction cycle x 256 * 7-bit PWM mode Value set in COMR1 = duty ratio (%) x 128 PWM wave cycle = count clock cycle x instruction cycle x 128 During operation in CH12PWM mode The value to be compared with the counter value is set in COMR1, which is used to specify the "L" width of a pulse. "L" level is output to the PWM1 pin until the value set in COMR1 matches the counter value. The value written to COMR1 when the counter is operating takes effect starting with the next cycle. Reference: The COMR1 setting value for operation in CH12PWM mode can be calculated from the equation shown below. However, note that the instruction cycle is affected by the clock mode and gear function. COMR1setting value = "L" width time of PWM wave/(count clock cycle x instruction cycle) - 1 198 8.5 Registers of the 2-Channel 8-Bit PWM Timer 8.5.5 PWM Compare Register 2 (COMR2) PWM compare register 2 (COMR2) is the CH2 data register. When the interval timer function is in operation, the value in COMR2 defines the interval time. When the normal PWM timer function is in operation, the value defines the "H" width of a pulse. In CH12PWM mode, the value defines the PWM wave cycle. I PWM Compare Register 2 (COMR2) Figure 8.5-6 "PWM Compare Register 2 (COMR2)" shows the bit configuration of COMR2. Bit manipulation instructions cannot be used for COMR2 because COMR2 is a write-only register. Figure 8.5-6 PWM Compare Register 2 (COMR2) Address COMR2 Initial value W : Write only X : Undefined * : This bit is meaningless when 7-bit PWM mode (high-speed mode) is used. When the interval timer is operating (8-bit timer mode and CK12 mode) The value to be compared with the counter value is set in COMR2, which is used to specify the interval time. When the value set in COMR2 matches the counter value, the counter is cleared and the interrupt request flag bit is set to "1" (TIR2 bit of CNTR2 = 1). The value written to COMR2 when the counter is operating takes effect starting with the next cycle (after match detection). Reference: The COMR2 setting value for the case when the interval timer is in operation can be calculated from the equation shown below. However, note that the instruction cycle is affected by the clock mode and gear function. * 8-bit timer mode COMR2 setting value = interval time/(count clock cycle x instruction cycle) - 1 * CK12 mode Value set in COMR2 = interval time/CH1 square wave output - 1 199 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS When the PWM timer is operating (8-bit PWM mode and 7-bit PWM mode) The value to be compared with the counter value is set in COMR2, which is used to specify the "H" width of a pulse. "H" level is output to the PT02 pin until the value set in COMR2 matches the counter value. The value written to COMR2 when the counter is operating takes effect starting with the next cycle (after the counter value has overflowed). Reference: The value set in COMR2 when the PWM timer is operating and the PWM wave cycle can be calculated as shown below. Note that the instruction cycle is affected by the clock mode and gear function. * 8-bit PWM mode COMR2 setting value = duty ratio (%) x 256 PWM wave cycle = count clock cycle x instruction cycle x 256 * 7-bit PWM mode COMR2 setting value = duty ratio (%) x 128 PWM wave cycle = count clock cycle x instruction cycle x 128 When CH12PWM mode is in effect The value to be compared with the counter value is set in COMR2, which is used to specify a PWM wave cycle. When the value set in COMR2 matches the counter value, the CH1 and CH2 counter values are cleared at the same time and the interrupt request flag bit (TIR2 bit of CNTR2) is set to "1." In this case, the PT01 pin goes Low. The value written to COMR2 when the counter is operating takes effect starting with the next cycle. Reference: The value set in COMR2 when CH12PWM mode is in effect can be calculated as shown below. Note that the instruction cycle is affected by the clock mode and gear function. COMR2 setting value = 1-cycle time of PWM wave/(count clock cycle x instruction cycle) - 1 200 8.6 2-Channel 8-Bit PWM Timer Interrupts 8.6 2-Channel 8-Bit PWM Timer Interrupts The 2-channel 8-bit PWM timer causes an interrupt if the counter value matches the value set in the PWM compare register when the interval timer function is operating. If the PWM timer function is operating in a mode other than CH12PWM mode, interrupt requests do not occur. I Interrupts When the Interval Timer Function Is Operating and CH12PWM Mode Is in Effect The counter value is incremented starting at 00H, according to the selected count clock. When the counter value matches the value set in PWM compare register (COMR), the corresponding interrupt request flag bits are set to "1" (TIR1 and TIR2 bits of CNTR2). In this case, when the interrupt request enable bit is set to "enable" (TIE2 bit of CNTR2 = 1), the 2-channel 8-bit PWM timer generates an interrupt request (IRQ6) for the CPU. Set the TIR bit to "0" and clear the interrupt request with the interrupt processing routine. When the counter value matches the value set in COMR1 or COMR2, the TIR1 and TIR2 bits are set to "1" irrespective of the values of the TIE1 and TIE2 bits. Note: For CH1, interrupts that occur in CH12 PWM mode cannot be used, because interrupts are disabled (TIE1 bit of CNTR = 0). For CH2, interrupts can be used in the same way as during operation with the interval timer function. Reference: When the counter value matches the COMR value and at the same time the counter stops (TPE1 and TPE2 bits of CNTR2 = 0), the TIR bit are not set. If the TIE bit changes from "0" (disabled) to "1" (enabled) when the TIR bit are "1," an interrupt request is generated immediately. I Register and Vector Table Related to 2-Channel 8-Bit PWM Timer Interrupts Table 8.6-1 Register and Vector Table Related to 2-Channel 8-Bit PWM Timer Interrupts Interrupt name IRQ5 IRQ6 Interrupt level setting register Register ILR2 (007CH) ILR2 (007CH) Setting bit L51 (bit3) L61 (bit5) L50 (bit2) L60 (bit4) Vector table address Upper FFF0H FFEEH Lower FFF1H FFEFH For information on the operation of interrupts, see Section 3.4.2 "Interrupt Processing." 201 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.7 Interval Timer Function Operation This section explains the operation of the interval timer function of the 2-channel 8-bit PWM timer in 8-bit timer mode and CK12 mode. I Operation of Interval Timer Function To use the 2-channel 8-bit PWM timers (CH1 and CH2) as the interval timer function in 8-bit timer mode and CK12 mode, the settings shown in Figure 8.7-1 "Settings of Interval Timer Function" must be made. Figure 8.7-1 Settings of Interval Timer Function Setting of CH1 interval time (compare value) Setting of CH2 interval time (compare value) X 1 0 CH1 CH2 CK12 : : : : : : : Used Unused (0 is set.) "1" is set. "0" is set. CH1 in 8-bit timer mode CH2 in 8-bit timer mode CK12 mode When the counter is activated, incrementing begins on the rising edge of the selected count clock, starting at 00H. When the counter value matches the value (compare value) set in COMR, the level of the PWM pin is inverted on the rising edge of the next count clock and the counter is cleared. Then, the interrupt request flag bit is set (TIR1 and TIR2 bits of CNTR2 = 1) and the count operation is restarted at 00H. In CK12 mode, the CH1 square wave that is output functions as the CH2 count clock. Figure 8.7-2 "Operation of the 2-Channel 8-Bit PWM Timer" shows operation of the 2-channel 8bit PWM timer. 202 8.7 Interval Timer Function Operation Figure 8.7-2 Operation of the 2-Channel 8-Bit PWM Timer Counter value Compare value (FFH) Compare value (80H) Time Timer cycle COMR value (FFH) Modification of COMR value (FFH 80H)(*1) Cleared by program TIR bit TPE bit OE bit PT01 pin PT02 pin When the output pin control bit (OE) is "0," this pin functions as a general I/O port. *1 If the compare register (COMR) value is modified while the counter is operating, the interval timer function takes effect starting with the next cycle. Note: When the interval timer function is operating (TPE1 and TPE2 bits of CNTR2 = 1), do not change the corresponding count clock cycle (SC11 and SC10 bits or SC21 and SC20 bits of CNTR1). In CK12 mode, however, the SC21 and SC20 bits are meaningless. Reference: Setting the COMR value to "00H" causes the PT01 or PT02 pin output to be inverted in the selected count clock cycle. When the interval timer function is operating, the output level of the PT01 or PT02 pin when the counter is stopped (TPE1 and TPE2 bits of CNTR2 = 0) is Low. 203 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.8 Explanation of the 2-Channel 8-Bit PWM Timer Operation in 8-Bit PWM Mode This section explains the operation of the 2-channel 8-bit PWM timer in 8-bit PWM mode. I PWM Timer Function Operation For operation of the 2-channel 8-bit PWM timers (CH1 and CH2) as the PWM timer function in 8-bit PWM mode, the settings shown in Figure 8.8-1 "Settings of 8-Bit PWM Mode" must be made. Figure 8.8-1 Settings of 8-Bit PWM Mode Setting of "H" width of CH1 pulse (compare value) Setting of "H" width of CH2 pulse (compare value) : X: 1: 0: CH1: CH2: Used Unused (0 is set.) "1" is set. "0" is set. CH1 in 8-bit timer mode CH2 in 8-bit timer mode As soon as the counter starts, incrementing begins at the rising edge of the selected count clock, starting at 00H. The PT01, PT02 pin output (PWM waveform) is kept at the "H"-level till the counter value matches the value in COMR. After that, the output of the PWM pin is kept at the "L"-level until a counter overflow occurs (FFH-->00H). If CH1 operates in 8-bit timer mode and CH2 operates in the PWM mode after the CK12 bit has been set to "1," the 2-channel 8-bit PWM timer enters CK12PWM mode. Figure 8.8-2 "Example of PWM Waveform Output in 8-Bit PWM Mode" shows the PWM waveforms output to the PT01, PT02 pin. 204 8.8 Explanation of the 2-Channel 8-Bit PWM Timer Operation in 8-Bit PWM Mode Figure 8.8-2 Example of PWM Waveform Output in 8-Bit PWM Mode When the COMR value is 00H (duty ratio: 0%) Counter value PWM waveform When the COMR value is 40H (duty ratio: 50%) Counter value PWM waveform When the COMR value is FFH (duty ratio: 99.6%) Counter value PWM waveform By 1 count Note: When the PWM timer function is operating (TPE1 and TPE2 bits of CNTR2 = 1), do not change the corresponding count clock cycle (SC11 and SC10 bits or SC21 and SC20 bits of CNTR1). When the CH1 PWM timer is operating, CK12 mode (CK12 bit of CNTR2 = 1) cannot be set. Reference: When the PWM timer function is operating, the PT01, PT02 pin output when the counter is stopped (TPE1 bit of CNTR2 = 1, TPE2 bit of CNTR2 = 0) is kept at the level in effect before the counter stopped. 205 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.9 2-Channel 8-Bit PWM Timer Operation in 7-Bit PWM Mode This section explains the operation of the 2-channel 8-bit PWM timer in 7-bit PWM mode (high-speed mode). I High-Speed PWM Timer Function Operation For operation of 2-channel 8-bit PWM timers (CH1 and CH2) as the PWM timer function in 7-bit PWM mode, the settings shown in Figure 8.9-1 "Settings of 7-Bit PWM Mode" must be made. Figure 8.9-1 Settings of 7-Bit PWM Mode Setting of "H" width of CH1 pulse (compare value) Setting of "H" width of CH2 pulse (compare value) : X: 1: 0: CH1: CH2: Used Unused (0 is set.) "1" is set. "0" is set. CH1 in 7-bit timer mode CH2 in 7-bit timer mode When the counter is started, incrementing begins at the rising edge of the selected count clock, starting with 00H. The PT01, PT02 pin output (PWM waveform) is kept at the "H"-level till the counter value matches the value in COMR. Afterwards, the PWM pin output is kept at the "L"-level till a counter overflow occurs (7FH--> 00H). The number of counter bits in 7-bit PWM mode is one bit less than that in the 8-bit PWM mode. For this reason, the operation speed in 7-bit PWM mode becomes twice as fast as that in the 8bit PWM mode (the cycle time in 7-bit PWM mode is one half of the cycle time in 8-bit PWM mode). If CH1 is operated in 8-bit timer mode and CH2 is operated in PWM mode after the CK12 bit has been set to "1," the 2-channel 8-bit PWM timer enters the CK12PWM mode. 206 8.9 2-Channel 8-Bit PWM Timer Operation in 7-Bit PWM Mode Figure 8.9-2 "Example of PWM Waveform Output in 7-Bit PWM Mode" shows the PWM waveforms output to the PT01, PT02 pin. Figure 8.9-2 Example of PWM Waveform Output in 7-Bit PWM Mode When the COMR value is 00H (duty ratio: 0%) Counter value PWM waveform When the COMR value is 40H (duty ratio: 50%) Counter value PWM waveform When the COMR value is 7FH (duty ratio: 99.2%) Counter value PWM waveform By 1 count Note: When the PWM timer function is operating (TPE1 and TPE2 bits of CNTR2 = 1), do not change the corresponding count clock cycle (SC11 and SC10 bits or SC21 and SC20 bits of CNTR1). When the CH1 PWM timer is operating, CK12 mode (CK12 bit of CNTR2 = 1) cannot be set. Reference: When the PWM timer function is operating, the PT01, PT02 pin output when the counter is stopped (TPE1 bit of CNTR2 = 1, TPE2 bit of CNTR2 = 0) is kept at the level in effect before the counter stopped. 207 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.10 Explanation of the 2-Channel 8-Bit PWM Timer Operation in CH12PWM Mode This section explains the operation of the 2-channel 8-bit PWM timer in CH12PWM mode. I 2-Channel 8-Bit PWM Timer Operation in CH12PWM Mode For operation of 2-channel 8-bit PWM timers (CH1 and CH2) as the PWM timer function in CH12PWM mode, the settings shown in Figure 8.10-1 "Settings of CH12PWM Mode" must be made. Figure 8.10-1 Settings of CH12PWM Mode Setting of "L" width of PWM wave (compare value) Setting of 1 cycle of PWM wave (compare value) : Used X : Unused (0 is set.) 1 : "1" is set. 0 : "0" is set. At the start of the CH1 or CH2 counter, incrementing begins with the rising edge of the selected count clock, starting at 00H. The PT01 pin output (PWM waveform) is kept at "L"-level till the CH1 counter value matches the value in COMR1. When the CH1 counter value matches the value set in COMR1, the PWM pin output becomes "H"-level. When the CH2 counter value matches the value in COMR2, the CH1 and CH2 counters are cleared at the same time and counting is restarted at 00H. In this case, the PT01 pin output becomes "L"-level and the interrupt request flag bit is set (TIR2 bit of CNTR2 = 1). Start the CH1 and CH2 counters at the same time (TPE1 and TPE2 bits of CNTR2 = 1). Starting these counters separately would have an effect on the "L" width of the first cycle of a PWM wave or on its cycle time. If the CH1 timer period that determines the "L" width of the PWM wave becomes greater than the CH2 timer period that determines the cycle of a PWM wave, PWM wave output is disabled. Figure 8.10-2 "Example of PWM Waveform (PWM pin) Output" shows the PWM waveforms output to the PT01 pin when the same count clock cycle is selected for CH1 and CH2. 208 8.10 Explanation of the 2-Channel 8-Bit PWM Timer Operation in CH12PWM Mode Figure 8.10-2 Example of PWM Waveform (PWM pin) Output When the COMR1 value is 00H and the COMR2 value is 80H (duty ratio: 0%) (CH1 timer time CH2 timer time) CH1 counter value CH2 counter value PWM waveform When the COMR1 value is 40H and the COMR2 value is 80H (duty ratio: 50%) CH1 counter value CH2 counter value PWM waveform When the COMR1 value is 00H and the COMR2 value is FFH (duty ratio: 99.6%) CH1 counter value CH2 counter value PWM waveform For a count of 1 (*1) *1 The minimum value of the "L" width can be reduced by making the FCH1 count clock faster than the CH2 count clock. Note: When the PWM timer function is operating (TPE1 and TPE2 bits of CNTR2 = 1), do not change the count clock cycle (SC11 and SC10 bits or SC21 and SC20 bits of CNTR1). When the 2-channel 8-bit PWM timer is operating in CH12PWM mode, CK12 mode (CK12 bits of CNTR21 and CNTR22 = 1) cannot be set. Disable output of CH2 interrupt requests (TIE1 bit of CNTR2 = 0) Reference: When the PWM timer function is operating, the PT01 pin output when the counter is stopped (TPE1 bit of CNTR2 = 1, TPE2 bit of CNTR2 = 0) is kept at the level in effect before the counter stopped. 209 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.11 Explanation of the Prescaler Operation of 2-Channel 8-Bit PWM Timer This section explains the prescaler operation of the 2-channel 8-bit PWM timer. I Prescaler Operation Prescaler operation of the 2-channel 8-bit PWM timer is enabled when the TPE1 or TPE2 bit of CNTR2 (counter operation enable bit) of PWM control register 2 is "1." For this reason, when the TPE1 and TPE2 bits are set to "1" at the same time, the operations with respect to both CH1 and CH2 are completely identical to those in the first cycle. However, if the operation of another counter is enabled when the TPE1 or TPE2 bit is already "1," the first cycle will contain a difference of up to one count clock cycle, because incrementing is started asynchronously. Figure 8.11-1 "Prescaler Operation" shows prescaler operation. Figure 8.11-1 Prescaler Operation Count clock CH1 square wave output (COMR1 value: 01H) CH2 square wave output (COMR2 value: 01H) Note: B produces a difference that is within 1 count clock cycle for A. 210 8.11 Explanation of the Prescaler Operation of 2-Channel 8-Bit PWM Timer Figure 8.11-2 Prescaler Output tinst: Instruction cycle 211 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.12 State of the 2-Channel 8-Bit PWM Timer Operation in Each Mode This section explains the operation of the 2-channel 8-bit PWM timer when the timer switches to sleep or stop mode or when a stop request before completion is issued during operation of the interval timer function or PWM timer function. I Operation in Standby Mode and for a Stop before Completion Figure 8.12-1 "Counter Operation in Standby Mode and for a Stop before Completion (When Interval Timer Function is Operating)" and Figure 8.12-2 "Counter Operation in Standby Mode and for a Stop before Completion (When PWM Timer Function Is Operating)" show the counter value states if the 2-channel 8-bit PWM timer switches to sleep or stop mode or a stop request before completion is issued when the interval timer function and PWM timer function are operating. When the 2-channel 8-bit PWM timer switches to stop mode, the counter retains the value and stops. If stop mode is released by an external interrupt, the counter starts operation at the retained value. For this reason, the first interval time and PWM wave cycle do not become the values that have been set. After stop mode has been released, reinitialize the 8-bit PWM timer. Release from watch mode (TMD bit of STBC = 1) is performed in the same way as a release from stop mode. Watch mode is released by a watch interrupt or an external interrupt. 212 8.12 State of the 2-Channel 8-Bit PWM Timer Operation in Each Mode When the interval timer function is in operation Figure 8.12-1 Counter Operation in Standby Mode and for a Stop before Completion (When Interval Timer Function is Operating) Counter value COMR value (FFH) Cleared by operation stop Timer cycle Cleared by program Stop request Oscillation stabilization wait time Time Operation stop Operation restart TIR bit TPE bit PT01 or PT02 pin (CNTR3:0E2 or 0E3 = 1) SLP bit (STBC register) STP bit (STBC register) Sleep Stop This bit is kept Low when operation is stopped. Sleep release by IRQ5 or IRQ6 Releasing of stop state by external interrupt *1 When the pin state specification bit (SPL) of the standby control register (STBC) is "1," the PT01, PT02 pin, which is in stop mode, is set to high impedance. 213 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS When the PWM timer function is operating Figure 8.12-2 Counter Operation in Standby Mode and for a Stop before Completion (When PWM Timer Function Is Operating) PT01 or PT02 pin (PWM waveform) The level in effect before operation stops is retained. TPE bit Operation stop Sleep SLP bit (STBC register) Sleep release by a means other than IRQ5 and IRQ6 (IRQ5 and IRQ6 do not occur.) Stop Operation restart STP bit (STBC register) Oscillation stabilization wait time Release of stop state by external interrupt *1 When the pin state specification bit (SPL) of the standby control register (STBC: SPL) is "1," the PT01 or PT02 pin, which is in stop mode, is set to high impedance. When the SPL bit is "0," the value in effect before the two-channel 8-bit PWM timer switches to stop mode is retained. 214 8.13 Notes on Using the 2-Channel 8-Bit PWM Timer Usage 8.13 Notes on Using the 2-Channel 8-Bit PWM Timer Usage This section provides notes on using the 2-channel 8-bit PWM timer. I Notes on Using the 2-Channel 8-Bit PWM Timer Deviation Start of the counter by a program is asynchronous with the start of incrementing the counter with the selected count clock. For this reason, the deviation that exists till the counter value matches the value in the PWM compare register (COMR) may become shorter by up to one count clock cycle. Figure 8.13-1 "Deviation that Remains till the Start of Count Operation" shows a deviation that exists till the start of count operation. Figure 8.13-1 Deviation that Remains till the Start of Count Operation Counter value Count clock 1 cycle Deviation 00H cycle Counter start Notes on program settings * When the interval timer function and PWM timer function are operating (TPE1 and TPE2 bits of CNTR2 = 1), do not modify the corresponding count clock cycle (SC11 and SC10 bits or SC21 and SC20 bits of CNTR1). Switch the interval timer function and PWM timer function (CNTR1:PTX1, PTX2) when the counter is stopped (CNTR2:TPE1 = 0, TPE2 = 0), interrupts are disabled (CNTR2:TIE1 = 0, TIE2 = 0), and interrupt requests have been cleared (CNTR2:TIR1 = 0, TIR2 = 0). In CK12 mode (CK12 bit of CNTR2 = 1), do not set CH12PWM mode (CH12 bit of CNTR3 = 1) and CH1 PWM timer operation (PTX1 bit of CNTR1 = 1). In CK12PWM mode, disable output of CH2 interrupt requests (TIE1 bit of CNTR2 = 0). Also, do not set CK12 mode. If the interrupt request flag bits (TIR1 and TIR2 bits of CNTR2) are "1" and the interrupt request enable bits are set to "enable" (TIE1 and TIE2 bits of CNTR2 = 1), control cannot return from interrupt processing. In this case, be sure to clear the TIR1 or TIR2. When the counter value matches the value set in COMR and at the same time the counter stops (TPE1 and TPE2 bits of CNTR2 = 0), the TIR1 or TIR2 bit is not set. * * * * * 215 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.14 Program Examples of the 2-Channel 8-Bit PWM Timer (Interval Timer Function) This section provides examples of 8-bit timer mode programs and CK12 mode programs for the 2-channel 8-bit PWM timer. I Examples of 8-Bit Timer Mode Programs Processing specifications * * * * CH1 operates as an interval timer in 8-bit timer mode. 5 ms interval timer interrupts are generated repeatedly. The square wave to be inverted at the interval time is output to the PT01 pin. The COMR1 value whose interval time is about 5 ms when the oscillation of the main clock is 10 MHz is shown below. The count clock is 64 tinst of the internal count clock (tinst: Divide-by-4 of oscillation when the main clock speed (gear) is set as the maximum speed). COMR1 value = 5ms/ (64 x 4/10MHz) -1 = 194.3 (0C2H) 216 8.14 Program Examples of the 2-Channel 8-Bit PWM Timer (Interval Timer Function) Coding example (comply with Softune V1) EQU 0027H ;Address of PWM control register 1 EQU 0028H ;Address of PWM control register 2 EQU 0029H ;Address of PWM control register 3 EQU 002AH ;Address of PWM compare register 1 EQU CNTR2:7 ;Definition of CH1 counter operation enable bit EQU CNTR2:3 ;Definition of CH2 interrupt request flag bit EQU 007C ;Address of interrupt level setting register DSEG ABS ; [DATA SEGMENT] ORG OFFE0H IRQ5 DW WARI1 ;Setting of interrupt vector INT_V ENDS ;-------------Main program------------------------------------------------------CSEG ; [CODE SEGMENT] ;We assume here that the stack pointer (SP) register is already initialised. : CLRI ;Disable interrupts. CLRB TPE1 ;Stop counter operation. MOV ILR3,#11110111B ;Set interrupt level (level 1). MOV COMR1,#0C2H ;Compare the value in COMR1 with the counter value (interval time). MOV CNTR1,#00001100B ;Interval timer operation, clearing of the CH1 clock, and 64tinst selection. MOV CNTR3,#00100000B ;Enable output to the PWM1 pin. MOV CNTR2,#10000000B ;Start counter operation and output an interrupt request. SETI ;Enable interrupts. : ;-----------Interrupt program---------------------------------------------------WARI1 CLRB TIR1 ;Clear the interrupt request flag. PUSHW A XCHW A,T ;Save A and T. PUSHW A : User processing : POPW A XCHW A,T ;Return A and T. POPW A RETI ENDS ;-------------------------------------------------------------------------------- CNTR1 CNTR2 CNTR3 COMR1 TPE1 TIR1 ILR2 INT_V 217 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS I Examples of CK12 Mode Programs Processing specifications * * * * CH1 assumes that the interval timer time is 5 ms (square wave output cycle = 10 ms) and that interrupts are not used. CH2 causes a 100 ms interval timer interrupt repeatedly on the assumption that CH1 is a count clock. The square wave to be inverted at the CH2 interval time is output to the PT02 pin. The COMR1 value for which the CH1 timer interval time becomes about 5 ms at a main clock oscillation of 10 MHz is shown below. The count clock is 64 tinst of the internal count clock (tinst: Divide-by-4 of oscillation when the main clock speed (gear) is set to the maximum speed). COMR1 value = 5ms/ (64 x 4/10MHz) -1 = 194.3 (0C2H) * The COMR2 value whose CH2 timer interval time is about 100 ms when a CH1 square wave is output is shown below. COMR2 value = 100ms/ (5 x 4/2) ms = 10 (00AH) 218 8.14 Program Examples of the 2-Channel 8-Bit PWM Timer (Interval Timer Function) Coding example (comply with Softune V1) EQU 0027H ;Address of PWM control register 1 EQU 0028H ;Address of PWM control register 2 EQU 0029H ;Address of PWM control register 3 EQU 002AH ;Address of PWM compare register 1 EQU 002BH ;Address of PWM compare register 2 EQU CNTR2:7 ;Definition of CH1 counter operation enable bit EQU CNTR2:6 ;Definition of CH2 counter operation enable bit EQU CNTR2:2 ;Definition of CH2 interrupt request flag bit EQU 007C ;Address of interrupt level setting register DSEG ABS ; [DATA SEGMENT] ORG OFFEEH IRQ6 DW WARI ;Setting of interrupt vector INT_V ENDS ;-------------Main program------------------------------------------------------CSEG ; [CODE SEGMENT] ;We assume here that the stack pointer (SP) register is already initialised. : CLRI ;Disable interrupts. CLRB TPE1 ;Stop counter operation. CLRB TPE2 MOV ILR2,#11110111B ;Set interrupt level (level 1). MOV COMR1,#0C2H ;Compare the value in COMR1 with the counter value (interval time). MOV COMR2,#00AH MOV CNTR1,#00001100B ;Interval timer operation, clearing of the CH1 clock, and 64tinst selection. MOV CNTR3,#01000000B ;Enable output to the PWM2 pin. MOV CONT2,#11100001B ;Start counter operation and output an interrupt request. SETI ;Enable interrupts. : ;-----------Interrupt program---------------------------------------------------WARI1 CLRB TIR2 ;Clear the CH2 interrupt request flag. PUSHW A XCHW A,T ;Save A and T. PUSHW A : User processing : POPW A XCHW A,T ;Return A and T. POPW A RETI ENDS ;-------------------------------------------------------------------------------END CNTR1 CNTR2 CNTR3 COMR1 COMR2 TPE1 TPE2 TIR2 ILR2 INT_V 219 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS 8.15 Program Examples of the 2-Channel 8-Bit PWM Timer (PWM Timer Function) This section provides program examples for the PWM timer function in 8-bit PWM mode, 7-bit PWM mode, and CH12PWM mode PWM of the 2-channel timer. I Examples of PWM Timer Function Programs Processing specifications * * * * * CH1 operates as a PWM timer in 8-bit PWM mode and square waves are output to the PT01 pin. CH2 operates as a PWM timer in 7-bit PWM mode (high-speed mode) and square waves are output to the PT02 pin. PWM waves with a 50% duty ratio are generated and the duty ratio is subsequently changed to 25%. No interrupts are generated. If the oscillation of the main clock is 10 MHz, each count clock is 16 tinst of the internal count clock (tinst: Divide-by-4 of oscillation when the main clock speed (gear) is set to the maximum speed), the CH1 PWM wave cycle becomes 16 x 4/10 MHz x 256 = 1.6384 ms and the CH2 PWM wave cycle becomes 16 x 4/10 MHz x 128 = 0.8192 ms. The COMR1 value whose duty ratio is 50% in 8-bit PWM mode is shown below. * COMR1 value = 50/100 x 256 = 128 (080H) * The COMR2 value whose duty ratio is 50% in 7-bit PWM mode is shown below. COMR2 value = 50/100 x 128 = 64 (040H) 220 8.15 Program Examples of the 2-Channel 8-Bit PWM Timer (PWM Timer Function) Coding example CNTR1 EQU 0027H ;Address of PWM control register 1 CNTR2 EQU 0028H ;Address of PWM control register 2 CNTR3 EQU 0029H ;Address of PWM control register 3 COMR1 EQU 002AH ;Address of PWM compare register 1 COMR2 EQU 002BH ;Address of PWM compare register 2 TPE1 EQU CNTR2:7 ;Definition of CH1 counter operation enable bit TPE2 EQU CNTR2:6 ;Definition of CH2 counter operation enable bit ;-------------Main program------------------------------------------------------CSEG ; [CODE SEGMENT] : CLRB TPE1 ;Stop counter operation. CLRB TPE2 MOV COMR1,#80H ;Specify the "H" width of a pulse and a duty ratio of 50%. MOV COMR2,#40H ;Specify 1 cycle of a pulse. MOV CNTR1,#11011010B ;Select PWM timer, 8/7-bit PWM mode and 16 tinst. MOV CNTR3,#01100000B ;Enable output to the PT01 and PT02 pin MOV CNTR2,#11000000B ;Start counter operation and disable output of interrupt requests. : : MOV COMR1,#40H ;Change the duty ratio to 25% (takes effect starting with the next PWM wave cycle). MOV COMR2,#20H : ENDS ;-------------------------------------------------------------------------------END 221 CHAPTER 8 2-CHANNEL 8-BIT PWM TIMERS I Program Examples for CH12PWM Mode Processing specifications * * * * * * * CH1 is set to 8-bit PWM mode to enable CH1 to operate as the PWM timer. CH2 is set to 8-bit PWM mode to enable CH2 to operate as the PWM timer. The initial duty ratio of the PWM value is set to 50%. No interrupts are generated. When the oscillation clock frequency is 10 MHz, each clock is 16tinst (tinst: Divided-by-4 value of the oscillation when the main clock speed (gear) is set to the maximum speed). The COMR1 register value ("L" width) is set to 40H to set the duty ratio to 50%. The COMR2 register value (cycle interval) is set to 80H to set the duty ratio to 50%. Coding example CNTR1 EQU 0027H ;Address of PWM control register 1 CNTR2 EQU 0028H ;Address of PWM control register 2 CNTR3 EQU 0029H ;Address of PWM control register 3 COMR1 EQU 002AH ;Address of PWM compare register 1 COMR2 EQU 002BH ;Address of PWM compare register 2 TPE1 EQU CNTR2:7 ;Definition of CH1 counter operation enable bit TPE2 EQU CNTR2:6 ;Definition of CH2 counter operation enable bit ;----------Main program---------------------------------------------------------CSEG ; [CODE SEGMENT] : CLRB TPE1 ;Stop counter operation. CLRB TPE2 MOV COMR1,#40H ;Specify the "L" width of a pulse and a duty ratio of 50%. MOV COMR2,#80H ;Specify 1 cycle of a pulse. MOV CNTR1,#11001010B ;Enable the counter to operate as the PWM timer and select 16tinst. MOV CNTR3,#00110000B ;Enable output to the PT01 pin and set the CH12PWM mode. MOV CNTR2,#11000000B ;Start counter operation and disable output of interrupt requests. : ENDS ;-------------------------------------------------------------------------------END 222 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) This chapter describes the functions and operations of the pulse width count timer (PWC). 9.1 "Overview of the Pulse Width Count Timer" 9.2 "Configuration of the Pulse Width Count Timer" 9.3 "Pins of the Pulse Width Count Timer" 9.4 "Registers of the Pulse Width Count Timer" 9.5 "Pulse Width Count Timer Interrupts" 9.6 "Operation of the Interval Timer Function" 9.7 "Operation of the Pulse Width Measurement Function" 9.8 "Status of the Pulse Width Count Timer in Each Mode" 9.9 "Notes on Using the Pulse Width Count Timer" 9.10 "Program Examples for the Interval Timer Function of the Pulse Width Count Timer" 9.11 "Program Example for the Pulse Width Measurement Function of the Pulse Width Count Timer" 223 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) 9.1 Overview of the Pulse Width Count Timer The pulse width count timer (PWC) has two functions: it can act as an interval timer that counts down in synchronization with three types of internal count clock, and it can provide a pulse width measurement function for measuring the width of pulses input to an external pin. Each of the functions can be selected. These functions allow the PWC to provide the settings for the 8-bit interval timer and to output square waves at a given frequency by using the output of this timer. The PWC can also be used for input capture by repeating external input pulse width measurements continuously. I Interval Timer Function (Square Wave Output Function) In the interval timer function, the PWC repeatedly generates interrupts at given time intervals. Also, the function can invert the output level of the pin (WT0) at each time interval to output square waves with a given frequency. * * * * * The interval time for the timer function ranges from one clock to 28 clocks of the internal count clock. The internal count clock can be selected from three types. The timer function can operate in either reload timer mode (in continuous operation) or in one-shot mode (one-time operation). The P20/PWCK pin can be selected as the external clock of PWC. The timer output bit (PCR2:T0) can be used as the count clock of the 8-bit PWM timer. Table 9.1-1 "Interval Times and Square Wave Output Ranges" lists the interval times and square wave output ranges. Table 9.1-1 Interval Times and Square Wave Output Ranges Internal count clock period 1tinst 4tinst 32tinst Interval time 1tinst to 28tinst 22tinst to 210tinst 25tinst to 213tinst Square wave output (Hz) 1/(2tinst) to 1/(29tinst) 1/(23tinst) to 1/(211tinst) 1/(26tinst) to 1/(214tinst) tinst: Instruction cycle (influenced by clock mode and others) Reference: Examples of interval time and square wave output frequency calculations are shown below. When the main clock source oscillation (FCH) is 10 MHz, the value of the PWC reload buffer register (RLBR) is DDH (221), and the count clock period is 1 tinst, the interval time and square wave output frequency can be calculated as follows: 224 9.1 Overview of the Pulse Width Count Timer Interval value Output frequency (1 x 4/F CH) x (RLBR register value) (4/10MHz) x 221 88.8 s FCH / (1 x 8 x (RLBR register value) 10MHz/ (8 x 221) 5.6kHz I Pulse Width Measurement Function The pulse width measurement function measures the width of "H" or "L" pulses, or one-cycle width of pulses input to an external pin (PWC pin). * * * The function also allows consecutive measurement of multiple pulses. There are three measurement speeds (internal clock count types) that can be selected. Moreover, the width of a long input pulse can be measured as well. Table 9.1-2 "Pulse Widths That Can Be Measured by the Pulse Width Measurement Function" lists the pulse widths that can be measured by the pulse width measurement function. Table 9.1-2 Pulse Widths That Can Be Measured by the Pulse Width Measurement Function Internal count clock period 1tinst 4tinst 32tinst Interval time 1tinst to 28tinst 22tinst to 210tinst 25tinst to 213tinst tinst: Instruction cycle (1/4 of the source oscillation of the main clock) 225 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) 9.2 Configuration of the Pulse Width Count Timer The pulse width count timer consists of the following six blocks: * Count clock selector * 8-bit down counter * Input pulse edge detection circuit * PWC reload buffer register (RLBR) * PWC pulse width control register 1 (PCR1) * PWC pulse width control register 2 (PCR2) I Block Diagram of the Pulse Width Count Timer Figure 9.2-1 Block Diagram of the Pulse Width Count Timer PWC pulse width control register 1 (PCR1) EN TOE IE UF IR BF P36/WTO Pin W2 W1 W0 Count clock selector of the 8-bit PWM timer P35/PWC 8-bit down counter Input pulse edge detection circuit Pin IRQ7 PWC pulse width control register 2 (PCR2) Internal data bus FC RM TO C1 C0 Count clock selector PWC reload buffer register (RLBR) tinst: Instruction cycle X1 X4 X 32 1tinst P20/PWCK Pin Counter clock selector This circuit selects the count down clock for the 8-bit down counter from three types of usable internal count clocks and external clock P20/PWCK. To select the external clock, set the P20/ PWCK port as the input port (DDR2:bit 0 = 0). 226 9.2 Configuration of the Pulse Width Count Timer 8-bit down counter This counter starts countdown either from the value obtained by subtracting 1 from the value of the PWC reload buffer register (RLBR) (when the interval timer function is used) or from FFH (when the pulse width is measured). When the counter value changes from 00H to FFH, the counter inverts the timer output bit (PCR2:TO). The TO bit is output to the WTO pin by setting the output pin control bit to a dedicated pin (PCR1:TOE = 1). Input pulse edge detection circuit This circuit operates when the pulse width measurement function is active. It controls the start and end of a countdown by the 8-bit down counter based on the input edge from the PWC pin that matches the edge set in PWC pulse width control register 2 (PCR2). PWC reload buffer register (RLBR) In the reload timer mode of the interval timer function, when the counter value changes from 00H to FFH, the value obtained by subtracting 1 from the RLBR register value is again set in the counter. Counting continues. In the case of the pulse width measurement function, the value of the 8-bit down counter is transferred to the RLBR register upon completion of the measurement. PWC pulse width control registers 1 and 2 (PCR1 and PCR2) These registers are used to select the function of the PWC, set the operating conditions, enable or disable operation, exert interrupt control, and check the PWC status. I Interrupts Related to Pulse Width Count Timer IRQ7: When the count value changes from 01H to 00H during operation of the interval timer function or pulse width measurement function, PWC generates an interrupt request if interrupt request output is enabled (PCR1:IE = 1). Also, PWC generates an interrupt request of the pulse width measurement function when: the pulse width measurement function completes the measurement of the pulse width, or interrupt request output is enabled (PCR1:IE = 1) with the pulse width measurement value retained in the RLBR register. 227 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) 9.3 Pins of the Pulse Width Count Timer This section describes the pulse width count timer pins and provides block diagrams of the pins. I Pins Related to the Pulse Width Count Timer The pins related to the pulse width count timer are P35/PWC and P36/WT0. P35/PWC and P36/WT0 pins The P35/PWC and P36/WT0 pins are used for multiple functions. P35 and P36 are used as general-purpose I/O ports, the PWC acts as an input pin for pulses to be measured, and WT0 acts as an output pin for the timer output bit (PCR2: T0). PWC: When the pulse width measurement function is selected, the counter measures the width of pulses that are input to this pin. When using this pin as the PWC pin for the pulse width measurement function, set it to the input port (DDR3:bit 5 = 0) by using the port data direction register. WT0: When the interval timer function is selected, the output level of this pin is inverted if the counter value changes from 00H to FFH. In reload timer mode, the pin outputs square waves. If the output pin control bit is set as a dedicated pin (PCR1: T0E = 1), the P36/WT0 pin automatically serves as an output pin that functions as the WT0 pin, regardless of the value of the port direction register (DDR3: bit 6). 228 9.3 Pins of the Pulse Width Count Timer I Block Diagrams of the Pins Related to the Pulse Width Count Timer Figure 9.3-1 Block Diagram of the Pins Related to the Pulse Width Count Timer (P35/PWC, P36/WTO) P35/PWC only To peripheral resource input PDR (port data register) Stop and watch mode (SPL = 1) Pull-up resistor About 50 k PDR read Internal data bus From timer output bit (PCR2: TO) From PCR1:TOE WTO pin only(*1) Pull-up control register Pch PDR read (for bit manipulation instructions) Output latch PDR write Pch DDR (Port data direction register) Pin Nch Stop and watch mode (SPL = 1) DDR write P35/PWC P36/WTO DDR read SPL: This bit specifies the pin state of the standby control register (STBC). *1 P36/WTO only Reference: If "pull-up resistor available" is selected in the pull-up option setting register, the pin is set to the "H" level (pull-up state), not the high-impedance state, in stop or watch mode (STBC:SPL = 1). However, the pull-up state is disabled during a reset, in which case the pin enters the Hi-z state. 229 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) Figure 9.3-2 Block Diagram of Pins Related to Pulse Width Count Timer (P20/PWCK) To peripheral resource input PDR (port data register) Stop and watch mode (SPL = 1) Pull-up resistor About 50 k PDR read Internal data bus Pull-up control register PDR read (for bit manipulation instructions) Pch Output latch PDR write Pch DDR (Port data direction register) Pin Nch Stop and watch mode (SPL = 1) P20/PWCK DDR write DDR read SPL: This bit specifies the pin state of the standby control register (STBC). Reference: If "pull-up resistor available" is selected in the pull-up register, the pin is set to the "H" level (pull-up state), not the high-impedance state, in stop or watch mode (STBC:SPL = 1). However, the pull-up state is disabled during a reset, in which case the pin enters the highimpedance state. 230 9.4 Registers of the Pulse Width Count Timer 9.4 Registers of the Pulse Width Count Timer This section describes the registers related to the pulse width count timer. I Registers Related to the Pulse Width Count Timer Figure 9.4-1 Registers Related to the Pulse Width Count Timer PCR1 and PCR2 (PWC pulse width control registers 1 and 2) Address Initial value Address Initial value RLBR (PWC reload buffer register) Address Initial value When the interval timer function is selected When the pulse width measurement function is selected R/W: R: : X: Read/write enabled Read only Not used Undefined 231 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) 9.4.1 PWC Pulse Width Control Register 1 (PCR1) PWC pulse width control register 1 (PCR1) is used to enable or disable the functions of the pulse width count timer, exert interrupt control, and check the PWC status. I PWC Pulse Width Control Register 1 (PCR1) Figure 9.4-2 PWC Pulse Width Control Register 1 (PCR1) Address Initial value 000--000B Buffer full flag bit Pulse width measurement value not defined Pulse width measurement value defined Measurement-end interrupt request flag bit Read Write Pulse width measurement not completed Pulse width measurement completed This bit is cleared. Unchanged; no other effect Underflow (00H --> FFH) interrupt request flag bit Read Counter value does not change from 00H --> FFH Counter value changes from 00H --> FFH Write This bit is cleared. Unchanged; no other effect The UF, IR, and BF bits are all interrupt request flag bits. Interrupt request enable bit Disables interrupt request output Enables interrupt request output Output pin control bit Used as a general-purpose port (P36) Used as the T0 bit output pin (WT0) T0 bit: Timer output bit (PCR2: TO, bit5) Counter operation enable bit Disables/stops counter operation Read/write enabled Read only Not used Initial value Enables/starts counter operation 232 9.4 Registers of the Pulse Width Count Timer Table 9.4-1 Functions of the PWC Pulse Width Control Register 1 (PCR1) Bits Bit name * Function If this bit is set to "1" when the interval timer function is selected, the counter starts countdown from the value set in the PWC reload buffer register (RLBR). Writing "0" stops counter operation. * If this bit is set to "1" when the pulse width measurement function is selected, measurement with the counter is enabled and, upon detection of the specified edge of the pulse to be measured, the counter starts countdown from FFH. Writing "0" stops counter operation. Note: If the pulse width measurement function is selected and if counter operation is disabled (EN = 0) during measurement, counter operation will stop. However, the counter value is not transferred to the RLBR register in this case. Restarting the counter (EN =1) sets its value to FFH, enabling counter operation. This bit specifies whether the P36/WT0 pin is to be used as a general-purpose port (T0E = 0) or a dedicated pin (interval timer output) (T0E = 1). * If the pin is set to be used as a dedicated pin, the value of the timer output bit (PCR2: T0) is output to the WT0 pin. Reference: If the output pin control bit is set to specify the use of the dedicated pin (T0E = 1), the pin functions as the WT0 pin, regardless of the state of the general-purpose port (P36). * * * * * * This bit enables or disables the output of interrupt requests to the CPU. If this bit or any of the interrupt request flag bits (UF, IR, and BF) is set to "1," an interrupt request is output to the CPU. The values of these bits are undefined during read operations. Write operations have no effect on the values of these bits. * bit7 EN: Counter operation enable bit bit6 TOE: Output pin control bit bit5 IE: Interrupt request enable bit Unused bits bit4 bit3 bit2 UF: Underflow (00H-->FFH) interrupt request flag bit This bit is set to "1" if the counter value changes from 00H to FFH. If both this bit and the interrupt request enable bit (IE) are set to "1," an interrupt request is output. * Writing "0" clears this bit. Writing "1" has no effect. Reference: * If the counter value changes from 00H to FFH when the interval timer function is selected, the timer output bit (PCR2: T0) is inverted. In reload timer mode, the counter continues countdown from the value set in the RLBR register. In one-shot timer mode, the counter automatically stops countdown (EN = 0). * If the counter value changes from 00H to FFH while the pulse width measurement function is measuring a long input pulse, the counter sets this bit to "1" and continues countdown. * This bit is used when the pulse width measurement function is selected. The bit is set to "1" when pulse width measurement is completed. If this bit and the interrupt request enable bit (IE) are set to "1," an interrupt request is output. During a write operation, setting "0" clears this bit. Setting "1" has no effect, and the bit is unchanged. This bit has no meaning when the interval timer function is selected. 233 bit1 IR: Measurementend interrupt request flag bit * * * * CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) Table 9.4-1 Functions of the PWC Pulse Width Control Register 1 (PCR1) Bits (Continued) Bit name * Function This bit is an interrupt request flag that is set to "1" if the RLBR register retains a measurement value when the pulse width measurement function is selected. If this bit and the interrupt request enable bit (IE) are set to "1," an interrupt request is output. The bit is set to "1" when the pulse width measurement is completed. It is cleared to "0" when the measurement value is read from the RLBR register. This is a read-only bit. Any attempt to write to this bit has no effect on counter operation. This bit has no meaning when the interval timer function is selected. * bit0 BF: Buffer full flag bit * * * 234 9.4 Registers of the Pulse Width Count Timer 9.4.2 PWC Pulse Width Control Register 2 (PCR2) PWC pulse width control register 2 (PCR2) is used to select the operation mode of the pulse width count timer (pulse width measurement, interval timer operation, etc.), select the count clock type, set the pulse to be measured (measurement edge), and check the timer output status. I PWC Pulse Width Control Register 2 (PCR2) Figure 9.4-3 PWC Pulse Width Control Register 2 (PCR2) Address Initial value Measured pulse selection bits Effective only when the pulse width measurement function is selected (Fc=1) "H" level (rising edge - falling edge) "L" (rising edge - falling edge) Rising edge - rising edge (one cycle) Falling edge - falling edge (one cycle) Detection of "H" level (rising edge falling edge) and the rising edge - rising edge Count clock selection bits External clock (P20/PWCK) Instruction cycle Timer output bit Read Write counter is stopped. The current output An output value can be set when the value is read. Reload mode selection bit Effective only when the interval timer function is selected (Fc = 0) Reload timer mode One-shot timer mode Operation mode selection bit R/W X : : : : Read/write enabled Unused Undefined Initial value Operates as the interval timer function Operates as the pulse width measurement function 235 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) Table 9.4-2 Functions of the PWC Pulse Width Control Register 2 (PCR2) Bits Bit name * bit7 FC: Operation mode selection bit Function This bit is used to toggle between the interval timer function (FC = 0) and the pulse width measurement function (FC = 1). Note: When the pulse width measurement function (FC = 1) is selected, specify the P35/PWC pin as an input port. * bit6 RM: Reload mode selection bit When the interval timer function is selected This bit is used to toggle between reload timer mode (RM = 0) and oneshot timer mode (RM = 1). When the pulse width measurement function is selected This bit is meaningless. This bit is inverted each time the counter value changes from 00H to FFH. When the output pin control bit (PCR1: T0E) of PWC pulse width control register 1 is set to "1," the value of this bit is output from the WT0 pin. By counting the number of times this bit is inverted (the counter value changes from 00H to FFH), the timer can measure pulses longer than 28 clocks of the selected count clock. When the counter is stopped (PCR1: EN = 0) and when output is enabled (PCR1: T0E = 1), the value this bit is set to become the initial value for the WT0 pin. * * * bit5 TO: Timer output bit * bit4 bit3 C1, C0: Count clock selection bits These bits select the count clock for the interval timer and pulse width measurement functions. * Three types of internal count clock inputs can be set for port P20/ PWCK. Note: To use the external clock, set the port (P20/PWCK) as the input port. * When the pulse width measurement function is selected These bits enable selection of the pulse edge type used as the condition for starting or stopping the measurement of the pulse to be measured. These bits enable the setting of five pulse widths and a cycle. When the interval timer function is selected These bits have no meaning. * bit2 bit1 bit0 W2, W1, W0: Measured pulse selection bits * Note: Do not modify the PCR2 register data while the counter is operating (PCR1: EN = 1). 236 9.4 Registers of the Pulse Width Count Timer 9.4.3 PWC Reload Buffer Register (RLBR) The PWC reload buffer register (RLBR) functions as a reload register when the interval timer function is selected. When the pulse width measurement function is selected, it serves as a measured value storage register. I PWC Reload Buffer Register (RLBR) Figure 9.4-4 "PWC Reload Buffer Register (RLBR)" shows the bit configuration of the PWC reload buffer register. Figure 9.4-4 PWC Reload Buffer Register (RLBR) Address Initial value When the interval timer function is selected When the pulse width measurement function is selected Read/write enabled Read only Undefined When the interval timer function is selected The RLBR register functions as a reload register that specifies the interval time. When counter operation is enabled (PCR1:EN = 1), the timer starts countdown from the value obtained by subtracting 1 from the value written into this register. In reload timer mode, when the counter value changes from 00H to FFH, the value obtained by subtracting 1 from the RLBR register value is again set (reload) in the counter. The counter continues to count. Also, if a value is written to the RLBR register while the counter is operating, that value becomes valid the next time the value of the RLBR register is reloaded into the counter when the counter value changes from 00H to FFH. Reference: The value to be set in the RLBR register when the interval timer function is selected can be obtained from the following equation. Note that the instruction cycle is 1/4 (4/FCH) of the source oscillation. RLBR register value = interval time/(count clock period x instruction cycle) 237 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) When the pulse width measurement function is selected The RLBR register serves as a measured value storage register. When pulse width measurement ends upon detection of the measurement-end edge, the counter value is transferred to this register. At this time, the buffer full flag bit (PCR1: BF) and the measurement-end interrupt request flag bit (PCR1: IR) are set to "1." The BF bit is cleared to "0" when this register is read. Reference: When the pulse width measurement function is selected, the pulse width can be obtained from the RLBR register value using the following equation. Note that the instruction cycle is 1/4 (4/FCH) of the source oscillation. Pulse width = (256 - RLBR register value) x count clock period x instruction cycles 238 9.5 Pulse Width Count Timer Interrupts 9.5 Pulse Width Count Timer Interrupts A pulse width count timer interrupt can occur for the following two reasons: * The counter value changes from 01H to FFH while the interval timer function is operating. * The measurement ends or the buffer becomes full while the pulse width measurement function is operating. I Interrupts That Occur When the Interval Timer Function Is Selected When the counter value changes from 00H to FFH after the counter starts countdown with the selected internal count clock, the underflow (00H --> FFH) interrupt request flag bit (PCR1: UF) is set to "1." At this time, an interrupt request (IRQ7) is sent to the CPU provided the interrupt request enable bit is "1" (PCR1: IE = 1). To clear the interrupt request, set the UF bit to "0" by using an interrupt processing routine. Reference: The UF bit is not set if a counter stop (PCR1: EN = 0) and a change of the counter value from 00H to FFH occur at the same time. If the IE bit is changed from 0 (disable) to 1 (enable) when the UF bit is set to "1," an interrupt request is generated immediately. I Interrupts That Occur When the Pulse Width Measurement Function Is Selected When the specified measurement-end edge is detected, the measurement-end interrupt request flag bit (PCR1: IR) and the buffer full flag bit (PCR1: BF) are set to "1." When the counter value changes from 00H to FFH because of a long pulse, the UF bit is set to "1." At this time, an interrupt request (IRQ7) is sent to the CPU if the interrupt request enable bit is set to 1 (PCR1: IE = 1). To clear the interrupt request, set the IR and UF bits to "0" by using an interrupt processing routine. Alternatively, read the PWC reload buffer register (RLBR) to clear the BF bit to "0." Reference: * * The IR and BF bits of the PWC pulse width control register 1 are not set if a counter stop (PCR1:EN = 0) and the detection of a measurement-end edge occur at the same time. If the IE bit changes from "disabled" to "enabled (1)" when the IR, BF, or UF bit of PWC pulse width control register 1 is set to 1, an interrupt request is generated immediately. 239 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) I Registers and Vector Tables Related to Pulse Width Count Timer Interrupts Table 9.5-1 Registers and Vector Tables Related to Pulse Width Count Timer Interrupts Interrupt level setting register Interrupt name Register IRQ7 ILR2 (007CH) Setting bit L71 (bit7) L70 (bit6) Upper bits FFECH Lower bits FFEDH Vector table address For information about interrupt processing, see Section 3.4.2 "Interrupt Processing." 240 9.6 Operation of the Interval Timer Function 9.6 Operation of the Interval Timer Function This section describes the interval timer function of the pulse width count timer. I Operation of the Interval Timer Function The interval timer function can operate in two modes. In reload timer mode, the function operates the timer continuously. In one-shot mode, the timer stops when one operation cycle is completed. Reload timer mode To operate the timer in reload timer mode requires the setting shown in Figure 9.6-1 "Setting the Interval Timer Function (in Reload Timer Mode)" Figure 9.6-1 Setting the Interval Timer Function (in Reload Timer Mode) Set the interval time (initial counter value) Used bit Unused bit Set to "1" Set to "0" When the counter is started, the value obtained by subtracting 1 from the RLBR register value is set in the counter. Countdown starts at the rising edge of the selected count clock. When the counter value changes from 01H to 00H, the value of the timer output bit (PCR2: T0) is inverted. After the counter is set again to the value of the RLBR register (the value is reloaded), the underflow (01H --> 00H) interrupt request flag bit is set (PCR1: UF = 1) at the rising edge of the next count clock. Figure 9.6-2 "Timer Operation in Reload Timer Mode" shows the operation of the timer in reload timer mode. 241 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) Figure 9.6-2 Timer Operation in Reload Timer Mode Counter value Reload Time RLBR value Timer period Cleared by the program UF bit EN bit T0E bit WT0 bit (T0 bit) Becomes a general-purpose I/O port when the output pin control bit (T0E) is set to "0." *1: Any change in the value of the PWC reload buffer register (RLBR) during a cycle of timer operation becomes effective in the next cycle. When the initial value is "0" Change the RLBR value (*1) (FFH to 80H) Reference: Setting the value of the RLBR register to 01H causes the T0 bit value to be inverted for one count clock cycle. One-shot timer mode To operate the timer in one-shot timer mode requires the setting shown in Figure 9.6-3 "Setting the Interval Timer Function (One-Shot Timer Mode)". Figure 9.6-3 Setting the Interval Timer Function (One-Shot Timer Mode) Set the interval time (initial counter value) Used bit Unused bit Set to "1" Set to "0" When the counter is started, the value stored in the RLBR register is set in the counter, which then starts countdown at the rising edge of the selected count clock. When the counter value changes from 00H to FFH, the value of the timer output bit (PCR2: T0) is inverted and the counter operation enable bit is automatically cleared (PCR1: EN = 0). After the operation of the counter is stopped, the underflow (00H --> FFH) interrupt request flag bit is set (PCR1: UF = 1) at the rising edge of the next count clock. 242 9.6 Operation of the Interval Timer Function Figure 9.6-4 "Timer Operation in One-Shot Timer Mode" shows the operation of the timer in one-shot timer mode. Figure 9.6-4 Timer Operation in One-Shot Timer Mode Counter value RLBR value Timer period Cleared by the program Time Change the RLBR value (FFH to 80H) (*1) UF bit EN bit Automatic clear T0E bit WT0 bit (T0 bit) When the counter starts with an initial value of "1" Invert Restart Automatic clear Restart Automatic clear Restart with the initial value remaining "0" *1: Any change in the value of the PWC reload buffer register (RLBR) during a cycle of timer operation becomes effective in the next cycle. Note: Do not change the PCR2 data while the counter is operating (PCR1: EN = 1). Reference: * * The UF bit is set to "1" whenever the counter value changes from 00H to FFH, regardless of the value of the interrupt request enable bit (PCR1: IE). If the counter is stopped (PCR1: EN = 0) when the interval timer function is selected, the T0 bit retains the value stored immediately before counter stops. 243 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) 9.7 Operation of the Pulse Width Measurement Function This section describes the operation of the pulse width measurement function of the pulse width count timer. I Operation of the Pulse Width Measurement Function Operation of the pulse width measurement function requires the settings shown in Figure 9.7-1 "Settings for the Pulse Width Measurement Function". Figure 9.7-1 Settings for the Pulse Width Measurement Function The measured pulse width value is retained. Used bit Used to measure long pulse width Unused bit Set to "1" Set to "0" When counter operation has been enabled, the counter starts countdown from FFH when it detects a measurement-start edge in a pulse input to the PWC pin. (If the input is already "H" for measurement of the "H" width, the counter starts the measurement at the next rising edge.) When a measurement-end edge is detected, the value of down counter at that point is transferred to the PWC reload buffer register (RLBR). The measurement-end interrupt request flag bit (PCR1: IR) and the buffer full flag bit (PCR1: BF) are set to "1," and counter operation is enabled again. (Since the pulse width measurement can be performed repeatedly, the counter can be used for input capture.) Figure 9.7-2 "Example of "H"-Width Measurement When the Pulse Width Measurement Function is Selected" shows how the counter operates when the measured pulse selection bits (PCR2: W2, W1, and W0) are set to 000B ("H" width measurement). 244 9.7 Operation of the Pulse Width Measurement Function Figure 9.7-2 Example of "H"-Width Measurement When the Pulse Width Measurement Function is Selected Input pulse (Waveform input to the PWC pin) Counter value "H"-width Time EN bit IR bit BF bit The down counter transfers data to the RLBR. Read the RLBR Cleared by the program Counting Note: * If the previous RLBR register value is not read after the pulse width measurement has been performed repeatedly, the BF bit remains "1," retaining the previous measured value. New measured values are discarded. Do not change data in the PCR2 register while pulse width measurement is in progress (PCR1: EN = 1). * I Measurement of Long Pulse Width To measure a pulse whose width is greater than 28 times the selected count clock period, it is necessary to count either the number of times the value of the WT0 pin (PCR2: T0) is inverted by using an external circuit or the number of times the counter value changes from 00H to FFH by using an interrupt processing routine. Counting the number of times the counter value changes from 00H to FFH by software requires that a buffer (software counter) be allocated in RAM for storing the number of these events. When the software counter has been initialized and counter operation is enabled, the counter starts countdown from FFH when a measurement-start edge is detected in a pulse input to the PWC pin. An interrupt request is generated if a measurement-end edge is detected or if the counter value changes from 00H to FFH. The interrupt processing routine checks the measurement-end interrupt request flag bit (PCR1: IR) and the underflow (00H --> FFH) interrupt request flag bit (PCR1: UF). If the UF bit is "1," the bit is set to "0" by writing to clear the interrupt request and, at the same time, the software counter is incremented (counter operation continues). If the IR bit is set to "1," the pulse width, including the number of times the counter value changes from 00H to FFH, is calculated from the software counter value and the PWC reload buffer register (RLBR) value. When the RLBR register value is 00H, it is assumed to be 256. 245 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) Long pulse width calculation method Pulse width = [(256 - RLBR register value) + (number of times the counter value changes from 00 H to FFH x 256)] x width of 1 cycle of the count clock Calculate the pulse width before the next counter value change from 00H to FFH occurs. If calculated after the next counter value change from 00H to FFH, the pulse width value may not be accurate. Figure 9.7-3 "Long Pulse Width Measurement" shows how the counter operates when the measured pulse selection bits (PCR2: W2, W1, and W0) are set to 011B (falling edge to falling edge). Figure 9.7-3 Long Pulse Width Measurement 1 cycle Input pulse (Waveform input to the PWC pin) EN bit Counter value Software counter value Set to "0" UF bit Cleared by the program Cleared by the program IR bit BF bit The down counter transfers data to the RLBR. Read the RLBR 246 9.8 Status of the Pulse Width Count Timer in Each Mode 9.8 Status of the Pulse Width Count Timer in Each Mode This section describes the operations performed by the pulse width count timer when it enters sleep mode or stop mode, or receives a stop request. I Operation in Standby Mode and for a Stop Request Figure 9.8-1 "Counter Operation in Standby Mode and for a Stop Request" shows how the counter value changes when the counter enters sleep mode or stop mode, or receives a stop request while it is executing the interval timer function or pulse width measurement function. Upon entering stop mode, the counter halts operation and retains its value. When stop mode is canceled by an external interrupt, the counter resumes operation from the retained value. For this reason, the initial interval time and pulse width values are invalid. After canceling stop mode, initialize the pulse width count timer again. Figure 9.8-1 Counter Operation in Standby Mode and for a Stop Request Counter value RLBR value Timer period Time Stop request Oscillator stabilization wait time Interval time after stop mode cancellation (undefined) UF bit Cleared by the program EN bit Resume operation IE bit SLP bit (STBC register) Sleep mode cancellation by IRQ7 SLP bit (STBC register) Stop Sleep Stop mode cancellation by an external interrupt Stop operation Stop operation 247 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) 9.9 Notes on Using the Pulse Width Count Timer This section provides notes on using the pulse width count timer. I Notes on Using the Pulse Width Count Timer Error When the interval timer function is used, the start of the counter by the program is not synchronized with the start of countdown by using the selected internal count clock. For this reason, the time from starting the counter until the counter value changes from 00H to FFH may be as much as one count clock cycle shorter. Figure 9.9-1 "Error Occurring before the Operation of the Counter Starts" shows how an error occurs before the operation of the counter starts. Figure 9.9-1 Error Occurring before the Operation of the Counter Starts Counter value Set value Count clock 1 cycle Error Setting value: n cycle Start of the counter Notes on setting the timer using a program * * Do not change the data of PWC pulse width control register 2 (PCR2) while the interval timer function or pulse width measurement function is operating (PCR1: EN = 1). Before switching from the interval timer function to the pulse width measurement function or vice versa (PCR2: FC), set the value of the PCR1 register in such a way that the counter (PCR1: EN = 0), disable interrupts (PCR1: IE = 0), and clear interrupt requests (UF, IR, and BF = 0) are disabled. The counter cannot recover from an interrupt if the interrupt request flag bits (PCR1: UF, IR, and BF) and the interrupt request enable bit (PCR1: IE = 1) are set to "1." Be sure to clear the interrupt request flag bits. In the case of the pulse width measurement function, if the previous measurement value has not been read out when the next pulse width measurement has been completed, the counter retains the previous value without transferring the new value to the PWC reload buffer register (RLBR). When measuring the long pulse width, read the measured value before the next counter value change from 00H to FFH occurs. The interrupt request flag bits (PCR1: UF, IR, and BF) are not set if a counter stop (PCR1: * * * 248 9.9 Notes on Using the Pulse Width Count Timer EN = 0) and an interrupt occur at the same time. 249 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) 9.10 Program Examples for the Interval Timer Function of the Pulse Width Count Timer This section shows two program examples for the interval timer function of the pulse width count timer. I Program Example 1 for the Interval Timer Function (Reload timer mode) Processing specifications * * * An interval timer interrupt occurs repeatedly at 3 ms intervals (reload timer mode). A square wave is output to the WT0 pin that is initially at the "L" level. This wave is inverted at the end of each interval. The RLBR register value shown below causes the interval time to be about 3 ms when the source oscillation of the main clock is 10 MHz. The count clock is 32 tinst (tinst: 1/4 of the source oscillation of the main clock when the gear is set to the maximum speed). RLBR register value = 3ms/ (32x4/10MHz) = 234.4 (OEAH) 250 9.10 Program Examples for the Interval Timer Function of the Pulse Width Count Timer Coding example PCR1 PCR2 RLBR EN IE UF ILR2 INT_V EQU EQU EQU EQU EQU EQU 002CH 002DH 002EH PCR1:7 PCR1:5 PCR1:2 ;Address of PWC pulse width control register 1 ;Address of PWC pulse width control register 2 ;Address of the PWC reload buffer register ;Definition of the counter operation enable bit ;Definition of the interrupt request enable bit ;Definition of the underflow (00H--> FFH) interrupt request flag bit ;Address of interrupt level setting register 2 ;[DATA SEGMENT] EQU 007CH DSEG ABS ORG 0FFECH IRQ7 DW WARI ;Setting of the interrupt vector INT_V ENDS ;----------Main program---------------------------------------------------------CSEG ;[CODE SEGMENT] ;The stack pointer (SP) and other registers are assumed to have been initialized. : CLRI ;Disable interrupts CLRB EN ;Stop counter operation CLRB IE ;Disable the interrupt request output MOV A,RLBR ;Clear the buffer full flag (PCR1:bit 0). MOV ILR2,#01111111B ;Setting of the interrupt level (level 1) MOV RLBR,#0EAH ;Reloaded counter value (interval time) MOV PCR2,#00010000B ;Interval timer function, reload timer mode, initial value of the WTO pin output, and 32tinst selection MOV PCR1,#11100000B ;Start counter operation, enable WT0 pin output, enable interrupt request output, clear the underflow (00H-->FFH) interrupt request flag, and clear the measurement-end interrupt request flag (bit 1) SETI ;Enable interrupts : ;-----------Interrupt processing routine----------------------------------------WARI CLRB UF ;Clear the underflow (01H-->00H) interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;-------------------------------------------------------------------------------END 251 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) I Program Example 2 for the Interval Timer Function (One-shot Timer Mode) Processing specifications * * * One 3 ms interval timer interrupt occurs (one-shot timer mode). A pulse wave is output to the WT0 pin that is initially at the "H" level. The wave is inverted at the end of each interval. The RLBR register value shown below causes the interval time to be about 3 ms when the source oscillation of the main clock is 10 MHz. The count clock is 32 tinst (tinst: 1/4 of the source oscillation of the main clock when the gear is set to the maximum speed). Coding example PCR1 PCR2 RLBR EN IE UF ILR2 INT_V EQU EQU EQU EQU EQU EQU 002CH 002DH 002EH PCR1:7 PCR1:5 PCR1:2 ;Address of PWC pulse width control register 1 ;Address of PWC pulse width control register 2 ;Address of the PWC reload buffer register ;Definition of the counter operation enable bit ;Definition of the interrupt request enable bit ;Definition of the underflow (00H-->FFH) interrupt request flag bit ;Address of interrupt level setting register 2 ;[DATA SEGMENT] EQU 007CH DSEG ABS ORG 0FFECH IRQ7 DW WARI ;Setting of the interrupt vector INT_V ENDS ;----------Main program--------------------------------------------------------CSEG ;[CODE SEGMENT] ;The stack pointer (SP) and other registers are assumed to have been initialized. : CLRI ;Disable interrupts CLRB EN ;Stop counter operation CLRB IE ;Disable interrupt request output MOV A,RLBR ;Clear the buffer full flag (PCR1: bit 0) MOV ILR2,#01111111B ;Setting of the interrupt level (level 1) MOV RLBR,#0EAH ;Reloaded counter value (interval time) MOV PCR2,#01110000B ;Interval timer function, one-shot timer mode Initial value of WT0 pin output, 32 tinst selection MOV PCR1,#11100000B ;Start counter operation, enable WT0 pin output, enable interrupt request output, clear the underflow (00H-->FFH) interrupt request flag, and clear the measurement-end interrupt request flag (bit 1) SETI ;Enable interrupts : ;---------Interrupt processing routine-----------------------------------------WARI CLRB UF ;Clear the underflow (01H-->00H) interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------------------END 252 9.11 Program Example for the Pulse Width Measurement Function of the Pulse Width Count Timer 9.11 Program Example for the Pulse Width Measurement Function of the Pulse Width Count Timer This section shows a program example for the pulse width measurement function of the pulse width count timer. I Program Example for the Pulse Width Measurement Function Program Processing specifications * * * The "H"-width of pulses input to the PWC pin is measured (pulse width measurement function). When the width measurement of a pulse is completed, an interrupt occurs, allowing measurement to continue. The relationship between the RLBR register value and the measured pulse width shown below is observed when the count clock is 4 tinst (tinst: 1/4 of the source oscillation of the main clock when the gear is set to the maximum speed) and when the source oscillation of the main clock is 10 MHz. Pulse width = (256 - RLBR register value) x 4 x 4/10 MHz (measurement range: 1.6 s to 409.6 s) 253 CHAPTER 9 PULSE WIDTH COUNT TIMER (PWC) Coding example EQU 000FH EQU 002CH ;Address of PWC pulse width control register 1 EQU 002DH ;Address of PWC pulse width control register 2 EQU 002EH ;Address of the PWC reload buffer register EQU PCR1:7 ;Definition of the counter operation enable bit EQU PCR1:5 ;Definition of the interrupt request enable bit EQU PCR1:1 ;Measurement-end interrupt request flag bit EQU PCR1:0 ;Buffer full flag bit EQU 007CH ;Address of interrupt level setting register 2 DSEG ABS ;[DATA SEGMENT] ORG 0FFE6H IRQ7 DW WARI ;Setting of the interrupt vector INT_V ENDS ;----------Main program--------------------------------------------------------CSEG ;[CODE SEGMENT] ;The stack pointer (SP) and other registers are assumed to have been initialized. : MOV DDR3,#00000000B ;Set the P35/PWC pin to input CLRI ;Disable interrupts CLRB EN ;Stop counter operation CLRB IE ;Disable the interrupt request output MOV A,RLBR ;Clear the buffer full flag (PCR1:BF) MOV ILR2,#01111111B ;Setting of the interrupt level (level 1) MOV RLBR,#0E9H ;Counter reload value (interval time) MOV PCR2,#10001000B ;Pulse width measurement function, 4 tinst selection, and "H" pulse selection MOV PCR1,#10100000B ;Enable counter operation, disable WT0 pin output, enable interrupt request output, clear the underflow (00H-->FFH) interrupt request flag, and clear the measurement-end interrupt request flag (IR) SETI ;Enable interrupts ;----------Interrupt processing routine----------------------------------------WARI CLRB IR ;Clear the measurement-end interrupt request flag. PUSHW A XCHW A,T PUSHW A MOV A,RLBR ;Read the pulse width measurement value and clear the BF flag User processing POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------------------END DDR3 PCR1 PCR2 RLBR EN IE IR BF ILR2 INT_V 254 CHAPTER 10 6-BIT PPG TIMER This chapter describes the functions and operations of the 6-bit PPG timer. 10.1 "Overview of the 6-Bit PPG Timer" 10.2 "Configuration of the 6-Bit PPG Timer Circuit" 10.3 "Pins of the 6-Bit PPG Timer" 10.4 "Registers of the 6-Bit PPG Timer" 10.5 "Operation of the 6-Bit PPG Timer" 10.6 "Notes on Using the 6-Bit PPG Timer" 10.7 "Program Example of the 6-Bit PPG Timer Programs" 255 CHAPTER 10 6-BIT PPG TIMER 10.1 Overview of the 6-Bit PPG Timer The 6-bit PPG timer is a 6-bit binary counter that can select one out four types of internal count clocks. Because it can set an output waveform cycle and "H" width, it can also be used as the remote control transmission frequency generator or as buzzer output. I 6-Bit PPG Timer Function * * * * The waveforms generated by the 6-bit PPG timer are output to the PPG3 pin. This timer can set output waveform cycles and "H" widths independently. This timer can select a count clock from among four types of internal clocks. This timer can generate frequencies ranging from 2 to 26-1 count clock cycles. Table 10.1-1 "Output Cycles and Ranges for Adjusting the "H" Width" lists the output cycles and the ranges for adjusting the "H" width. Table 10.1-1 Output Cycles and Ranges for Adjusting the "H" Width Internal count clock cycle 1tinst 2tinst 8tinst 32tinst Output cycle 2tinst to 63tinst 4tinst to 126tinst 16tinst to 504tinst 64tinst to 2016tinst Output "H" width (*1) 1tinst to 62tinst 2tinst to 124tinst 8tinst to 496tinst 32tinst to 1984tinst tinst: Instruction cycle (affected by the clock mode and other factors) [Example] An example of calculating a cycle and "H" width of the 6-bit PPG function is given below. Assume that the count clock cycle is set to 1 tinst for main clock oscillation (FCH) 10 MHz. In this case, if the following is set: Cycle compare value = 011110B (30 clock cycles) "H" width compare value = 001010B (width of 10 clocks) The "H" width and cycle of the output waveform are obtained as shown below. However, they are obtained only if the fastest clock available in main clock mode (SCS = 1) is selected (CS1, CS01 instruction cycle = 4/FCH) with the system clock control register (SYCC). 256 10.1 Overview of the 6-Bit PPG Timer Cycle = Cycle compare value x count clock cycle = "011110B" (30 clock cycles) x 1 x 4/FCH = 30 x 0.4 s = 12 s "H" width = "H" width compare value x count clock cycle = "001010B" (width of 10 clocks) x 1 x 4/FCH = 10 x 0.4 s = 4 s The "H" level is output when an "H" width setting value is equal to or greater than a cycle setting value. I 6-bit PPG Timer Function 2 The controllable duty width is about 1.60% to 100%. The smaller the cycle compare value, the lower the resolution (the larger the minimum step width of the duty ratio). The output cycle and duty ratio can be calculated from the following formulas: Output cycle = cycle compare value x count clock cycle Duty ratio = (compare value for "H" width/cycle compare value) x 100 (%) Table 10.1-2 "Resolutions and Output Cycles for the 6-Bit PPG" lists the minimum steps of the duty ratio and output cycles. 257 CHAPTER 10 6-BIT PPG TIMER Table 10.1-2 Resolutions and Output Cycles for the 6-Bit PPG Cycle compare value 0 1 2 3 4 5 6 7 8 9 10 "H" width compare value setting range 0 Setting impossible 0 to 2 0 to 2 0 to 3 0 to 4 0 to 5 0 to 6 0 to 7 0 to 8 0 to 9 0 to 10 2 tinst 3 tinst 4 tinst 5 tinst 6 tinst 7 tinst 8 tinst 9 tinst 10 tinst 4 tinst 6 tinst 8 tinst 10 tinst 12 tinst 14 tinst 16 tinst 18 tinst 20 tinst : 15 0 to15 15 tinst 30 tinst : 20 0 to 20 20 tinst 40 tinst : 25 0 to 25 25 tinst 50 tinst : 30 0 to 30 30 tinst 60 tinst : 40 0 to 40 40 tinst 80 tinst : 50 0 to 50 50 tinst 100 tinst : 60 0 to 60 60 tinst 120 tinst : 63 0 to 63 63 tinst 126 tinst 504 tinst 2016 tinst 1/63 1.6% 480 tinst 1920 tinst 1/60 1.7% 400 tinst 1600 tinst 1/50 2.0% 320 tinst 1280 tinst 1/40 2.5% 240 tinst 960 tinst 1/30 3.3% 200 tinst 800 tinst 1/25 4.0% 160 tinst 640 tinst 1/20 5.0% 120 tinst 480 tinst 1/15 6.7% 16 tinst 24 tinst 32 tinst 40 tinst 48 tinst 56 tinst 64 tinst 72 tinst 80 tinst 64 tinst 96 tinst 128 tinst 160 tinst 192 tinst 224 tinst 256 tinst 288 tinst 320 tinst 1/2 1/3 1/4 1/5 1/6 1/7 1/8 1/9 1/10 50.0% 33.3% 25.0% 20.0% 16.7% 14.3% 12.5% 11.1% 10.0% Output cycle Count clock = 1 tinst Count clock = 2 tinst Count clock = 8 tinst Count clock = 32 tinst Resolution Minimum step of duty ratio Output "H" tinst: Instruction cycle 258 10.2 Configuration of the 6-Bit PPG Timer Circuit 10.2 Configuration of the 6-Bit PPG Timer Circuit The 6-bit PPG timer consists of the following five blocks: * Count clock selector * 6-bit counter * Comparator * 6-bit PPG control register 1 (RCR1) * 6-bit PPG control register 2 (RCR2) I Block Diagram of the 6-Bit PPG Timer Figure 10.2-1 Block Diagram of the 6-Bit PPG Timer Internal data bus RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 6-bit PPG control register 1 (RCR1) 6 "H" width compare value Count clock selector x1 1 tinst x2 x8 x 32 6-bit counter CLK Clear 6-bit PPG output Comparator Pin P30/30PPG03/MC0 6-bit PPG output enable signal 6 Cycle compare value 6-bit PPG control register 2 (RCR2) RCEN SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 Internal data bus tinst: Instruction cycle 259 CHAPTER 10 6-BIT PPG TIMER Count clock selector The count clock selector selects a 6-bit counter count-up clock from among four types of internal count clocks. 6-bit counter The 6-bit counter counts up using the count clock selected by the count clock selector. This counter is cleared (RCR2:RCEN = 0) with the output enable bit of the RCR2 register. Comparator The comparator retains the output at "H" until the value of the 6-bit counter matches the value of the register for "H" width comparison. Thereafter, the comparator keeps the output at "L" until the counter value matches the cycle compare register value. The 6-bit counter is then cleared and counting continues starting at 00H. 6-bit PPG control register 1 (RCR1) This register selects a count clock of the 6-bit PPG timer and sets a compare value for the "H" width. 6-bit PPG control register 2 (RCR2) This register enables output of the 6-bit PPG timer and sets a cycle compare value. 260 10.3 Pins of the 6-Bit PPG Timer 10.3 Pins of the 6-Bit PPG Timer This section describes 6-bit PPG timer pins and provides a block diagram of the pins. I Pins of the 6-Bit PPG Timer The 6-bit PPG timer pin is P30/PPG03/MCO. P30/PPG03/MCO pin This pin functions as a general-purpose I/O port (P30), 6-bit PPG timer output (PPG03), or main clock output (MCO). PPG03: The cycle that was set and the "H" width PPG waveform are output to this pin. The PPG waveform can be output by setting the output enable bit (RCR2:RCEN) of the 6-bit PPG control register to "1." I Block Diagram of the 6-Bit PPG Timer Pins Figure 10.3-1 Block Diagram of the P23/PPG1 Pins PDR (port data register) Stop and watch mode (SPL = 1) Pull-up resistor About 50 k PDR read Internal data bus PPG03 MCO From resource output enable Pull-up control register Pch PDR read (for bit manipulation instructions) Output latch PDR write Pch Pin DDR (Port data direction register) Nch P30/PPG03/MCO DDR write Stop and watch mode (SPL = 1) DDR read SPL: Pin state setting pin in the standby control register (STBC) Reference: If "pull-up resistor available" is selected with the port 3 pull-up resistor control register, the pins are set to the "H" level (pull-up state) in stop/watch mode (SPL = 1). However, the pullup is disabled during a reset and the pins enter the high-impedance state. 261 CHAPTER 10 6-BIT PPG TIMER 10.4 Registers of the 6-Bit PPG Timer This section describes the 6-bit PPG timer registers. I Registers of the 6-Bit PPG Timer Figure 10.4-1 6-Bit PPG Timer Registers RCR1 (6-bit PPG control register 1) Address 0 0 5 8H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 R/W R/W R/W R/W R/W R/W R/W R/W RCR2 (6-bit PPG control register 2) Address 0 0 5 9H bit7 RCEN R/W bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0-000000B SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 R/W R/W R/W R/W R/W R/W R/W : Can be read and written : Undefined 262 10.4 Registers of the 6-Bit PPG Timer 10.4.1 6-Bit PPG Control Register 1 (RCR1) The 6-bit PPG control register 1 is used to select a 6-bit PPG timer count clock and set the "H" width. I 6-Bit PPG Control Register 1 (RCR1) Figure 10.4-2 6-Bit PPG Control Register 1 (RCR1) Address 0 0 5 8H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 R/W R/W R/W R/W R/W R/W R/W R/W HSC5 to HSC0(*1) "H" width setting bit "H" width compare value of 6-bit PPG output XXXXXX *1 X indicates an optional value. RCK1 RCK0 0 0 0 1 0 1 Count clock selection bit 1 tinst 2 tinst 8 tinst 32 tinst R/W : Can be read and written tinst : Instruction cycle : Initial value 1 1 Table 10.4-1 Functions of the 6-Bit PPG Control Register 1 (RCR1) Bits Bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RCK2, RCK1: Count clock selection bits * Function These bits select a count clock for the 6-bit PPG timer from among the four types of internal count clocks. HSC5 to HSC0: "H" width setting bits These bits are used to set the count of the "H" width of the 6-bit PPG timer output ("H" width compare value). The count is compared with a counter value. Note: Set a value from 01H to 3EH and be sure to make it smaller than the cycle setting value. If a setting value is equal to or greater than the cycle setting value, the "H" level is always output. * 263 CHAPTER 10 6-BIT PPG TIMER 10.4.2 6-Bit PPG Control Register 2 (RCR2) The 6-bit PPG control register 2 is used to enable the output of 6-bit PPG waveforms and to set a cycle. I 6-Bit PPG Control Register 2 (RCR2) Figure 10.4-3 6-Bit PPG Control Register 2 (RCR2) Address Initial value 0-000000B SCL5 to SCL0(*1) Cycle setting bit 6-bit PPG output cycle compare value *1 X indicates an optional value. R/W : Can be read and written X : Undefined : Unused : Initial value Output enable bit Disables the output, clears the counter, and stops the operation. Enables output and starts counting. Table 10.4-2 Functions of the 6-Bit PPG Control Register 2 (RCR2) Bits Bit * bit7 RCEN: Output enable bit Function When this bit is "0," the P30/PPG03/MC0 pin is set as a generalpurpose port (P30). When this bit is "1," this pin is set as a 6-bit PPG output pin (PPG03). Setting this bit to "0" by writing stops and clears the counter. Writing "1" starts the counter operation. In read operations, the value of this bit is undefined. Writing this bit has no effect on operation. * * * * bit6 bit5 bit4 bit3 bit2 bit1 bit0 Unused SCL5 to SCL0: Cycle setting bits These bits set the count for the cycle of the 6-bit PPG output waveform (cycle compare value). This value is compared with the counter value. Note: Set a value from 02H to 3FH. If 00H is set, the state of the preceding pin is retained until the H width compare value is reached. After an H compare match, the H level is always output. 264 10.5 Operation of the 6-Bit PPG Timer 10.5 Operation of the 6-Bit PPG Timer The 6-bit PPG timer can set cycles and "H" widths to generate a remote control transmission frequency. I Operation of the 6-Bit PPG Timer The settings shown in Figure 10.5-1 "6-Bit PPG Timer Settings" are required for the 6-bit PPG timer to operate. Figure 10.5-1 6-Bit PPG Timer Settings 1 0 - : : : : Bit used Bit with 1 Bit with 0 Not used If output from the 6-bit PPG is enabled, the 6-bit counter starts counting from 00H in synchronization with the selected count clock. The PPG1 pin is kept at the "H" level until the counter value becomes an "H" width compare value. Next, the PPG1 pin is kept at the "L" level until the counter value becomes the cycle compare value. When a match occurs, the 6-bit counter is cleared and counting starts again from 00H. The 6-bit PPG timer can be used as a 6bit PPG because the "H" width and cycle can be set independently. Figure 10.5-2 "Operation of the 6-Bit PPG Timer" shows 6-bit PPG timer operation. Figure 10.5-2 Operation of the 6-Bit PPG Timer Counter value Cycle setting value (RCR2: SCL0 to SCL5) Cycle setting value (RCR1: HSC0 to HSC5) Cycle(*1) "H" width(*2) PPG1 output waveform *1 Cycle = count clock cycle x count compare value *2 Cycle = count clock cycle x H width compare value 265 CHAPTER 10 6-BIT PPG TIMER 10.6 Notes on Using the 6-Bit PPG Timer This section provides notes on using the 6-bit PPG timer. I Notes on Using the 6-Bit PPG Timer Limiting the "H" width setting value Always set the "H" width setting bit (RCR1:HSC5 to HSC0) value of 6-bit PPG control register 1 in the range from "000010" to "111111" (02 to 3EH). If 00H is set, the PPG1 pin output becomes "H" level output for 0.5 tinst. Always set an "H" width setting value smaller than value of the cycle setting bits (RCR2:SCL5 to SCL0) of 6-bit PPG control register 2. If the former value is equal to or greater than the latter, the PPG1 pin output is always set to the "H" level. Resolution The maximum resolution of the "H" width is 1/63 of the cycle (when the cycle setting value is 3FH). If however, a small value is set for this cycle setting value, the minimum resolution of the "H" width is restricted to 1/2 of the cycle (when the cycle setting value is 02H). Changing setting values during operation The following are directly compared with each other: the 6-bit PPG waveform frequency generation 6-bit counter and the "H" width setting bits (RCR1:HSC5 to HSC0), and the counter and cycle setting bits (RCR2:SCL5 to SCL0). Therefore, if a setting value is made small during counter operation, the counter overflows and the cycle may lengthen until matching is detected again. In addition, the "H" width may lengthen until matching is detected in the next cycle. Figure 10.6-1 "Setting Value Changes during 6-Bit PPG Timer Operation" shows the changes to setting values during 6-bit PPG timer operation. 266 10.6 Notes on Using the 6-Bit PPG Timer Figure 10.6-1 Setting Value Changes during 6-Bit PPG Timer Operation Counter value 3FH Cycle setting value RCR2 SCL 1 "H" width setting value RCR1 HCL 00H 1 2 Overflow 3 PPG03 output waveform For overflow For one cycle *1 The value of the operating counter is smaller than the changed setting value, so the setting value is valid within the cycle. *2 Because a cycle smaller than the value of the operating counter is set, no matching is detected and the counter overflows. *3 Because an "H" width smaller than the value of the operating counter is set, no matching with the next cycle is detected. Deviation The counter start by the program is asynchronous to the start of incrementing with the selected count clock. For this reason, the deviation that exists until a match of the counter value, "H"width compare value, and cycle compare value is detected may become shorter by up to one count clock cycle. Figure 10.6-2 "Deviation That Remains till the Start of Count Operation" shows the deviation that exists until the start of count operation. Figure 10.6-2 Deviation That Remains till the Start of Count Operation Counter value 0 Count clock 1 2 3 One cycle Deviation Count 0 cycle Counter start 267 CHAPTER 10 6-BIT PPG TIMER 10.7 Program Example of the 6-Bit PPG Timer Programs This section provides program examples of the 6-bit PPG timer. I Program Example of the 6-Bit PPG Timer Processing specifications * * A remote control transmission frequency is generated with a cycle of about 12 s and a duty ratio of about 33%. Shown below is the cycle compare value for which the cycle becomes 12 s at the highest main clock speed for a main clock oscillation of 10 MHz (FCH). The count clock is assumed to be 1 tinst. (Time for processing a single instruction: 4/FCH). Cycle compare value (RCR2:SCL5 to SCL0) = 12 s/ (1 x 4/10MHz) = 30 * The "H" width compare value whose duty ratio is approx. 33% is shown below. In this case, the "H" width is approx. 9.5 s. "H" width compare value (RCR1:HSC5 to HSC0) = 33/100 x Cycle compare value = 0.33 x 30 = 10 Coding example (comply with Softune V1) RCR1 EQU 0058H ;Address of 6-bit PPG control register 1 RCR2 EQU 0059H ;Address of 6-bit PPG control register 2 ;---------Main program---------------------------------------------------------CSEG ; [CODE SEGMENT] : MOV RCR1,#00001010B ;Selects 1 tinst for the count clock; "H" width ;compare value MOV RCR2,#10011110B ;Output is enabled and operation starts, ;cycle compare value : ENDS ;------------------------------------------------------------------------------END 268 CHAPTER 11 12-BIT PPG TIMER This chapter describes the functions and operations of the 12-bit PPG timer. 11.1 "Overview of the 12-Bit PPG Timer" 11.2 "Configuration of the 12-Bit PPG Timer Circuit" 11.3 "Pins of the 12-Bit PPG Timer" 11.4 "Registers of the 12-Bit PPG Timer" 11.5 "Operation of the 12-Bit PPG Timer" 11.6 "Notes on Using the 12-Bit PPG Timer" 11.7 "Program Example of the 12-Bit PPG Timer" 269 CHAPTER 11 12-BIT PPG TIMER 11.1 Overview of the 12-Bit PPG Timer The 12-bit PPG timer is a 12-bit binary counter that can select one of four clocks as its count clock. This timer can set an output waveform cycle and an "H" width and can be used as a remote control transmission frequency generator or a 12-bit PPG. I 12-Bit PPG Timer Function * * * * This timer generates remote control frequencies and outputs signals to PPG01 or 02. This timer can set output waveform cycles and "H" widths independently. This timer can select a count clock from among four types of internal clocks. Frequencies ranging from 2 to 212-1 count clock cycles can be generated. Table 11.1-1 "Output Cycles and Ranges for Adjusting the "H" Width" lists the output cycles and the ranges for adjusting the "H" width. Table 11.1-1 Output Cycles and Ranges for Adjusting the "H" Width Internal count clock cycle 2tinst 4tinst 16tinst 256tinst Output cycle 2tinst to 8190tinst 8tinst to 16380tinst 32tinst to 65520tinst 512tinst to 1048.32ktinst Output "H" width 1tinst to 8188tinst 2tinst to 16376tinst 16tinst to 65504tinst 128tinst to 1048.604ktinst tinst: Instruction cycle (affected by the clock mode and others) Note: A stable "L" or "H" level can also be output (duty cycle of 0% or 100%). See the example of calculating the "H" width, shown below. Reference: Suppose that 12.5 MHz is selected as the main clock oscillation (FCH) and that a 2tinst clock is selected as the count clock cycle. Also suppose that, in main clock mode, the highest clock speed (SYCC:SCS = CS1 = CS0 = 1) is selected from the system clock control register (this causes the instruction cycle time to become 4/FCH). [Example] Cycle = Cycle compare value + count clock cycle = "011110B" (30-clock cycle) x 2 x 4/FCH = 30 x 2 x 0.32 s = 19.2 s "H" width = "H" width compare value x count clock cycle = "001010B" (10-clock width) x 2 x 4/FCH = 10 x 2 x 0.32 s = 6.4 s The "H" level is output when an "H" width setting value is equal to or greater than a cycle 270 11.1 Overview of the 12-Bit PPG Timer setting value. I 12-Bit PPG Function The cycle and "H" width of an output waveform can be set independently, so the 12-bit PPG timer can be used as the remote control transmission output generator. However, the effective range of the "H" width compare setting is a value from "0" (duty ratio of 0%) to the cycle compare setting (duty ratio of 100%). This means that when the cycle compare setting falls (if the cycle of an output waveform is short), the resolution also falls (the step size of the maximum duty ratio becomes large). he controllable duty width is about 0.02% to 100%. The smaller the cycle compare value, the lower the resolution (the larger the minimum step width of the duty ratio). The output cycle and duty ratio can be calculated from the following formulas: Output cycle = cycle compare value x count clock cycle Duty ratio = "H" width compare value/compare value x 100 (%) Table 11.1-2 "Resolutions and Output Cycles for the 12-Bit PPG" lists the minimum steps of the duty ratio and output cycles. 271 CHAPTER 11 12-BIT PPG TIMER Table 11.1-2 Resolutions and Output Cycles for the 12-Bit PPG Output cycle Cycle compare value 0 1 2 3 4 5 6 7 8 9 10 Count clock = 2 tinst 4 tinst 6 tinst 8 tinst 10 tinst 12 tinst 14 tinst 16 tinst 18 tinst 20 tinst Count clock = 4 tinst 8 tinst 12 tinst 16 tinst 20 tinst 24 tinst 28 tinst 32 tinst 36 tinst 40 tinst Count clock = 16 tinst 32 tinst 48 tinst 64 tinst 80 tinst 96 tinst 112 tinst 128 tinst 144 tinst 160 tinst : 20 40 tinst 80 tinst 320 tinst : 100 200 tinst 400 tinst 1600 tinst : 500 1000 tinst 2000 tinst 8000 tinst : 1000 2000 tinst 4000 tinst 16000 tinst : 2000 4000 tinst 8000 tinst 32000 tinst : 3000 6000 tinst 12000 tinst 48000 tinst : 4095 8190 tinst 16380 tinst 65520 tinst 1048320 tinst 0 to 4095 1/4095 0.02% 768000 tinst 0 to 3000 1/3000 0.03% 512000 tinst 0 to 2000 1/2000 0.05% 256000 tinst 0 to 1000 1/1000 0.1% 12800 tinst 0 to 500 1/500 0.2% 25600 tinst 0 to100 1/100 1.0% 5120 tinst 0 to 20 1/20 5.0% Count clock = 256 tinst 512 tinst 768 tinst 1024 tinst 1280 tinst 1536 tinst 1792 tinst 2048 tinst 2304 tinst 2560 tinst "H" width compare value setting range 0 to 1 0 to 2 0 to 3 0 to 4 0 to 5 0 to 6 0 to 7 0 to 8 0 to 9 0 to 10 1/2 1/3 1/4 1/5 1/6 1/7 1/8 1/9 1/10 50.0% 33.3% 25.0% 20.0% 16.7% 14.3% 12.5% 11.1% 10.0% Minimum step of duty ratio Resolution tinst: Instruction cycle 272 11.2 Configuration of the 12-Bit PPG Timer Circuit 11.2 Configuration of the 12-Bit PPG Timer Circuit The 12-bit PPG timer consists of the following seven blocks: * Count clock selector * 12-bit counter * Comparator * PPG1/PPG2 control register (PPGC1/PPGC2) * PPG1/PPG2 reload register 1 (PRL11/PRL21) * PPG1/PPG2 reload register 2 (PRL12/PRL22) * PPG1/PPG2 reload register 3 (PRL13/PRL23) I Block Diagram of the 12-Bit PPG Timer Figure 11.2-1 Block Diagram of the 12-Bit PPG Timer Internal data bus PRL11, PRL21 HSC11 HSC10 HSC9 HSC8 HSC7 HSC6 PPGC1, PPGC2 RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 "H" width compare value 12 Count clock selector X2 1 tinst X4 X16 X256 12-bit counter CLK 12-bit PPG output Comparator P21/PPG01 P22/PPG02 Pin 12-bit PPG output enable signal CLEAR 12 Cycle compare value PRL13, PRL23 SCL11 SCL10 SCL9 SCL8 SCL7 SCL6 PRL12, PRL22 RCEN SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 Internal data bus tinst: Instruction cycle 273 CHAPTER 11 12-BIT PPG TIMER Count clock selector The count clock selector is a circuit that selects four types of internal count clocks and selects a count-up clock for the 12-bit counter. 12-bit counter The 12-bit counter counts up using the count clock selected by the count clock selector. This counter is cleared (RCR23:RCEN = 0) with the output enable bit of the RCR23 register. Comparator The comparator keeps the output at "H" until the 12-bit counter value matches the "H" width compare register value. Thereafter, the comparator keeps the output at "L" until the counter value matches the cycle compare register value that was set. The 12-bit counter is then cleared and counting continues starting at 00H. PPG control register (PPGC1/PPGC2), reload register 1 (PRL11/PRL21) PPGC1/PPGC2 and PRL11/PRL21 are used to select the counter clocks of the 12-bit PPG timer and to set compare values for the output "H" pulse width. PPG reload register 2 (PRL12/PRL22) and PPG reload register 3 (PRL13/PRL23) PRL12/PRL22 and PRL23 are used to enable or disable the 12-bit PPG timer and to set compare values for the output cycles. 274 11.3 Pins of the 12-Bit PPG Timer 11.3 Pins of the 12-Bit PPG Timer This section describes the 12-bit PPG timer pins and provides a block diagram of the pins. I 12-Bit PPG Timer Pins The 12-bit PPG timer pin is either the P21/PPG01 or P22/PPG02 pin. P21/PPG01 pin and P22/PPG02 pin These pins function as the general-purpose CMOS I/O port (P21, P22) or the 12-bit PPG timer output (PPG01, PPG02). PPG01/PPG02: The set cycle and the PPG waveform of the "H" width are output to this pin. Setting the output enable bit (RCEN bit of PRL12 or PRL22 = 1) of the 12-bit PPG control register to "1" enables the output of PPG waveforms. I Block Diagram of the 12-Bit PPG Timer Pins Figure 11.3-1 Block Diagram of the P21/PPG01 Pins PDR (port data register) PDR read PPG01 output PPG01 output enabled Pull-up resistor About 50 k Stop and watch mode (SPL = 1) Pull-up control resistor Internal data bus PDR read (for bit manipulation instructions) Pch Output latch PDR write Pch DDR (Port data direction register) Pin Nch Stop and watch mode (SPL = 1) P21/PPG01 DDR write DDR read SPL: This bit specifies the pin state of the standby control register (STBC). 275 CHAPTER 11 12-BIT PPG TIMER Figure 11.3-2 Block Diagram of P22/PPG02 Pin PDR (port data register) PDR read PPG02 output PPG02 output enabled Pull-up resistor About 50 k Stop and watch mode (SPL = 1) Pull-up control resistor Internal data bus PDR read (for bit manipulation instructions) Pch Output latch PDR write Pch DDR (Port data direction register) Pin Nch Stop and watch mode (SPL = 1) P22/PPG02 DDR write DDR read SPL: This bit specifies the pin state of the standby control register (STBC). Reference: If "pull-up resistor available" is selected in the port 2 pull-up resistor control register, the pins are set to the "H" level (pull-up state) in stop/watch mode (SPL = 1). However, the pull-up is disabled during a reset and the pins enter the high-impedance state. Note: If an RMW instruction for the port 2 data register (PDR2) is executed when the 12-bit PPG timer is operating, only the level of the P22/PPG02 pin is read during a read operation. For this reason, the value of bit 2 in PDR2 may change. 276 11.4 Registers of the 12-Bit PPG Timer 11.4 Registers of the 12-Bit PPG Timer This section describes the 12-bit PPG timer registers. I 12-Bit PPG Timer Registers Figure 11.4-1 12-bit PPG Time Registers PPG2 register PPGC2 (PPG2 control register) Address 0038H bit7 RCK1 R/W bit6 RCK0 R/W bit5 HSC5 R/W bit4 HSC4 R/W bit3 HSC3 R/W bit2 HSC2 R/W bit1 HSC1 R/W bit0 HSC0 R/W Initial value 00000000B PRL21 (PPG2 reload register 1) Address 003AH bit7 bit6 bit5 bit4 HSC11 HSC10 R/W R/W bit3 HSC9 R/W bit2 HSC8 R/W bit1 HSC7 R/W bit0 HSC6 R/W Initial value --000000B PRL22 (PPG2 reload register 2) Address bit7 bit6 bit5 SCL5 0039H RCEN R/W R/W PRL23 (PPG2 reload register 3) Address bit7 bit6 bit5 SCL11 003BH R/W bit4 SCL4 R/W bit3 SCL3 R/W bit2 SCL2 R/W bit1 SCL1 R/W bit0 SCL0 R/W Initial value 0-000000B bit4 SCL10 R/W bit3 SCL9 R/W bit2 SCL8 R/W bit1 SCL7 R/W bit0 SCL6 R/W Initial value --000000B PPG1 register PPGC1 (PPG1 control register) Address bit7 bit6 bit5 004CH RCK1 RCK0 HSC5 R/W R/W R/W PRL11 (PPG1 reload register 1) Address 004EH bit7 bit6 bit5 bit4 HSC11 HSC10 R/W R/W bit3 HSC9 R/W bit2 HSC8 R/W bit1 HSC7 R/W bit0 HSC6 R/W Initial value --000000B bit4 HSC4 R/W bit3 HSC3 R/W bit2 HSC2 R/W bit1 HSC1 R/W bit0 HSC0 R/W Initial value 00000000B PRL12 (PPG1 reload register 2) Address 004DH bit7 RCEN R/W bit6 bit5 SCL5 R/W bit4 SCL4 R/W bit3 SCL3 R/W bit2 SCL R/W bit1 SCL1 R/W bit0 SCL0 R/W Initial value 0-000000B PRL13 (PPG1 reload register 3) Address bit7 bit6 bit5 004FH SCL11 R/W R/W : Can be read and written - : Unused bit4 SCL10 R/W bit3 SCL9 R/W bit2 SCL8 R/W bit1 SCL7 R/W bit0 SCL6 R/W Initial value --000000B 277 CHAPTER 11 12-BIT PPG TIMER 11.4.1 12-Bit PPG Control Register 1 (PPGC1/PPGC2) The 12-bit PPG control register 1 is used to select a 12-bit PPG timer count clock and set the "H" width. I 12-Bit PPG Control Register (PPGC1/PPGC2) Figure 11.4-2 12-bit PPG Control Register 1 (PPGC1/PPGC2) Address 0 0 3 8H 0 0 4 CH Initial value HSC5 to HSC0*1 "H" width setting bit "H" width compare value of the 12-bit PPG output *1 X indicates an optional value. Count clock selection bit Can be read and written Instruction cycle Initial value Table 11.4-1 Functions of the 12-bit PPG Control Register 1 (PPGC1/PPGC2) Bits Bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RCK1, RCK0: Count clock selection bits * Function These bits select a count clock for the 12-bit PPG timer from among four types of internal count clocks. HSC5 to HSC0: "H" width setting bits * These bits and the HCS6 to HSC11 bits of PRL11/PRL21 are used to set the count of the "H" width ("H" width compare value to be compared with the counter value) of the 12-bit PPG timer output. 278 11.4 Registers of the 12-Bit PPG Timer 11.4.2 12-Bit PPG Reload Register 1 (PRL11/PRL21) The 12-bit PPG reload register 1 is used to set the "H" width. I 12-bit PPG Reload Register 1 (PRL11/PRL21) Figure 11.4-3 12-Bit PPG Reload Register 1 (PRL11/PRL21) Address 003AH 004EH bit7 bit6 bit5 bit4 HSC11 HSC10 R/W R/W bit3 HSC9 R/W bit2 HSC8 R/W bit1 HSC7 R/W bit0 HSC6 R/W Initial value --000000B HSC11 to HSC6(*1) R/W : Can be read and written : Unused XXXXXX "H" width setting bit "H" width compare value *1 X indicates an optional value. Table 11.4-2 Functions of the 12-Bit PPG Reload Register 1 (PRL11/PRL21) Bits Bit bit5 bit4 bit3 bit2 bit1 bit0 Function HSC11 to HSC6: "H" width setting bits These bits and the HCS0 to HCS5 bits of PPGC1/PPGC2 are used to set the count of the "H" width ("H" width compare value to be compared with the counter value) of the 12-bit PPG timer output. 279 CHAPTER 11 12-BIT PPG TIMER 11.4.3 12-Bit PPG Reload Register 2 (PRL12/PRL22) The 12-bit PPG reload register 2 is used to enable or disable output and to set an output cycle. I 12-bit PPG Reload Register 2 (PRL12/PRL22) Figure 11.4-4 PPG Reload Register 2 (PRL12/PRL22) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0039H SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 RCEN 004DH R/W R/W R/W R/W R/W R/W R/W Initial value 0X000000B SCL5 to SCL0(*1) XXXXXX Cycle setting bit Cycle compare value of 12-bit PPG output *1 X indicates an optional value. RCEN 0 R/W : Can be read and written : Unused : Initial value 1 Output enable bit Disables output, clears the counter, and stops operation. Enables output and starts counting. Table 11.4-3 Functions of the 12-Bit PPG Reload Register 2 (PRL12/PRL22) Bit RCEN: Output enable bit Function When this bit is "0", the pin serves as a general-purpose port. When this bit is "1", the pin serves as a 12-bit PPG output pin. Writing "0" to this bit clears and stops the counter. Writing "1" to this bit starts the counter. * * The value read from this bit is undefined. Writing to this bit has no effect on the operation. bit7 bit6 Unused bit5 bit4 bit3 bit2 bit1 bit0 SCL5 to SCL0: Cycle setting bits These bits and the SCL6 to SCL11 bits of PRL13/PRL23 are used to set the length of the output cycle (cycle compare value to be compared with the counter value) with a counter value. Note: Set a value from "000000000010" to "111111111111" (002H to FFFH). If 000H is set, output stops in the state existing at setting and that state is retained. 280 11.4 Registers of the 12-Bit PPG Timer 11.4.4 12-Bit PPG Reload Register 3 (PRL13/PRL23) The 12-bit PPG reload register 3 is used to set an output cycle. I 12-bit PPG Reload Register 3 (PRL13/PRL23) Figure 11.4-5 12-Bit PPG Reload Register 3 (PRL13/PRL23) Address 003BH 004FH Initial value SCL11 SCL10 SCL9 SCL8 SCL7 SCL6 --000000B R/W R/W R/W R/W R/W R/W SCL11 to SCL6(*1) XXXXXX Cycle setting bit Cycle compare value of 12-bit PPG output *1 X indicates an optional value. R/W : Can be read and written : Unused Table 11.4-4 Functions of the 12-Bit PPG Reload Register 3 (PRL13/PRL23) Bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Unused * * Function The value read from this bit is undefined. Writing to this bit has no effect on the operation. SCL11 to SCL6: Cycle setting bits These bits and the SCL0 to SCL5 bits of PRL12/PRL22 are used to set the length of the output cycle (cycle compare value to be compared with the counter value) with a counter value. Note: Set a value from "000000000010" to "111111111111" (002H to FFFH). If 000H is set, the output stops in the state existing at setting and that state is retained. 281 CHAPTER 11 12-BIT PPG TIMER 11.5 Operation of the 12-Bit PPG Timer The 12-bit PPG timer generates PPG output that can independently set output cycles and "H" pulse widths. I Operation of the 12-Bit PPG Timer The settings shown in Figure 11.5-1 "12-Bit PPG Timer Settings" are required for operation of the 12-bit PPG timer. Figure 11.5-1 12-Bit PPG Timer Settings bit7 RCK1 bit6 RCK0 bit5 HSC5 bit4 HSC4 bit3 HSC3 bit2 HSC2 bit1 HSC1 bit0 HSC0 PPGC2 PPGC1 bit7 PRL21 PRL11 bit7 RCEN 1 bit7 PRL23 PRL13 bit6 bit5 bit4 HSC11 HSC10 bit3 HSC9 bit2 HSC8 bit1 HSC7 bit0 HSC6 bit6 PRL22 PRL12 bit5 SCL5 bit4 SCL4 bit3 SCL3 bit2 SCL2 bit1 SCL1 bit0 SCL0 : Used 1 : Set to "1." 0 : Set to "0." bit6 bit5 SCL11 bit4 SCL10 bit3 SCL9 bit2 SCL8 bit1 SCL7 bit0 SCL6 If output of a 12-bit PPG timer is enabled, the 12-bit counter starts counting from zero in synchronization with the selected count clock and holds the PPG pin at the "H" level until the counter value reaches the "H" width compare value. Next, the 12-bit counter keeps the PPG pin at the "L" level until the counter value reaches the cycle compare value. When the values match, the 12-bit counter is cleared and starts counting again from zero. Because the "H" width and cycle can be set independently, a remote control transmission frequency can also be set. Figure 11.5-2 Operation of the 12-Bit PPG Timer Cycle setting value Counter value (PRL13/PRL12: SCL11 to SCL6 / SCL5 to SCL0) (PRL23/PRL22: SCL11 to SCL6 / SCL5 to SCL0) "H" width setting value (PRL11/PPG1: HSC11 to HSC6 / HSC5 to HSC0) (PRL21/PPG2: HSC11 to HSC6 / HSC5 to HSC0) 00H Cycle(*1) Pulse width(*2) *1 Cycle = count clock cycle x cycle compare value *2 Pulse width = count clock cycle x "H" width compare value 282 11.6 Notes on Using the 12-Bit PPG Timer 11.6 Notes on Using the 12-Bit PPG Timer This section provides notes on using the 12-bit PPG timer. I Notes on Using the 12-Bit PPG Timer Limiting the "H" width setting value Set the "H" width setting bits (HSC5 to HSC0 bits of PPGC1/PPGC2 and HSC11 to HSC6 bits of PRL11/PRL21) of the PPG control register with a value from "000000000010B" to "111111111111B" ("001H" to "FFFH"). If 00H is set, the PPG pin outputs the "H" level for 0.5tinst. Set a value ("H" width) that is smaller than the values of the cycle setting bits (SCL5 to SCL0 of PRL12/PRL22 and SCL11 to SCL6 of PRL13/PRL23). If the set value is greater than or equal to the values of the cycle setting bits, the PPG pin output is held at the "H" level. Resolution The maximum resolution of the "H" width is 1/4095 of the cycle (when the cycle setting value is "111111111111B"("FFFH")). If, however, the cycle setting value is made small, the minimum resolution of the "H" width is restricted to 1/2 of the cycle (when the cycle setting value is "000000000010B" ("02H")). Changing the setting values during operation The 12-bit PPG timer directly compares the 12-bit counter/"H" width setting bits with the counter/cycle setting bits. For this reason, if a small value is set while the counter is operating, the match detection cycle may lengthen until a match is detected again because the counter will overflow. The "H" width may also lengthen until a match is detected in the next cycle. Figure 11.6-1 "Setting Value Changes during 12-Bit PPG Timer Operation" shows the setting value changes made while the 12-bit PPG timer is operating. 283 CHAPTER 11 12-BIT PPG TIMER Figure 11.6-1 Setting Value Changes during 12-Bit PPG Timer Operation Cycle setting value Counter value Overflow (PRL13/PRL12: SCL11 to SCL6 / SCL5 to SCL0) (PRL23/PRL22: SCL11 to SCL6 / SCL5 to SCL0) 3FH "H" width setting value (PRL11/PPG1: HSC11 to HSC6 / HSC5 to HSC0) (PRL21/PPG2: HSC11 to HSC6 / HSC5 to HSC0) PPG01/PPG02 output waveform For overflow For one cycle *1 Since the counter value during operation is smaller than the changed setting value, the setting value is valid within the cycle. *2 No matching is detected and the counter overflows because the cycle that is set is smaller than the counter value used during operation. *3 No matching is detected until the next cycle because the "H" width that is set is smaller than the counter value used during operation. Deviation The counter start by the program is asynchronous to the start of incrementing with the selected count clock. For this reason, the deviation that exists until a match of the counter value, "H"width compare value, and cycle compare value is detected may become shorter by up to one count clock cycle. Figure 11.6-2 Deviation until Counting Starts Counter value Count clock One cycle Deviation Count 0 cycle Counter start 284 11.7 Program Example of the 12-Bit PPG Timer 11.7 Program Example of the 12-Bit PPG Timer This section provides program examples of the 12-bit PPG timer. I Program Example of the 12-Bit PPG Timer Program specifications * * A remote transmission frequency is set with a cycle of about 12 s and a duty ratio of 33%. When the selected clock is 2tinst at the highest main clock speed for the main clock oscillation of 10 MHz, the cycle compare value when the cycle becomes about 12 s is shown below. Cycle compare value (SCL5 to SCL0 bits of PRL22 and SCL11 to SCL6 bits of PRL23) = 12 s/ (2 x 4/10MHz) = 15 * The "H" width compare value when the duty ratio becomes 33% is shown below. "H" width compare value (HSC5 to HSC0 bits of PPGC2 and HSC11 to HSC6 bits of PRL21) = 33/100 x cycle compare value = 0.33 x 15 = 4.95 Coding example PPGC2 EQU 0038H ; PPG control register PRL21 EQU 003AH ; PPG reload register 1 PRL22 EQU 0039H ; PPG reload register 2 PRL23 EQU 003BH ; PPG reload register 3 ;--------Main program---------------------------------------------------------CSEG ;[CODE SEGMENT] : MOV PPGC2,#01000101B ;Selects 4tinst as the count clock and sets the "H" width compare value. MOV PRL21,#00H ; MOV PRL22,#10001111B ;Enables output, starts operation, and sets a cycle compare value. MOV PRL23,#00H : ENDS ;-----------------------------------------------------------------------------END 285 CHAPTER 11 12-BIT PPG TIMER 286 CHAPTER 12 16-BIT TIMER/COUNTER This chapter describes the functions and operations of the 16-bit timer/counter. 12.1 "Overview of the 16-bit Timer/Counter" 12.2 "Configuration of the16-bit Timer/Counter" 12.3 "Pin of the 16-bit Timer/Counter" 12.4 "Registers of the 16-bit Timer/Counter" 12.5 "16-bit Timer/Counter Interrupts" 12.6 "Operation of the Interval Timer Function" 12.7 "Operation of the Counter Function" 12.8 "Status of the 16-bit Timer/Counter in Each Mode" 12.9 "Notes on Using the 16-bit Timer/Counter" 12.10 "Program Example of the 16-bit Timer/Counter" 287 CHAPTER 12 16-BIT TIMER/COUNTER 12.1 Overview of the 16-bit Timer/Counter The 16-bit timer/counter has an interval timer function and a counter function. The interval timer function counts up in synchronization with the internal count clock (the oscillator frequency divided into four cycles). The counter function counts up by detecting a prespecified edge of a pulse that is input to the external pin. One of these functions can be selected. I Interval Timer Function The interval timer function generates an interrupt at prespecified intervals. The 16-bit counter counts up from a setting value in synchronization with the internal count clock that divides the oscillator frequency into four cycles and generates an interrupt if the counter value overflows. * * Interval timer operation up to an internal count clock times 216 is possible. Use the interrupt processing routine to reset the interval time to generate an interrupt repeatedly. Table 12.1-1 "Range for Interval Time" shows the range for the interval time. Table 12.1-1 Range for Interval Time Internal count clock cycle 1tins Interval time 1tinst to 216tinst tinst: Instruction cycle (the oscillator frequency divided into four cycles) Reference: An example of calculating the interval time is shown below. The interval time at which the main clock oscillation (FCH) is 12.5 MHz and the value of the timer count register (TCR) is "0000H" can be calculated from the following formula: Interval time = (4/FCH) x (216 - TCR register value) = (4/12.5 MHz) x 65536 = 21.0 ms I Counter Function The counter function detects the edge of a pulse that is input to the external pin (EC pin) and counts it. * * * Counts up every time a prespecified edge of the external input is detected and generates an interrupt if the counter value overflows. Can detect the pulse width of the external input at a minimum of two instruction cycles. Can be set to detect both rising and falling edges. 288 12.2 Configuration of the 16-bit Timer/Counter 12.2 Configuration of the 16-bit Timer/Counter The 16-bit timer/counter consists of the following five blocks: * Count clock selector * Edge detection circuit * Timer count register (TCR) * Timer control register (TMCR) * Lower 8-bit latch I Block Diagram of the 16-bit Timer/Counter Figure 12.2-1 Block Diagram of the 16-bit Timer/Counter Section Internal data bus Counter clear Timer control register (TMCR) Overflow TCR TCS Upper 8-bit TCHR Lower 8-bit TCLR TCR TCS1 TCS0 TCEF TCIE IRQ8 Read data 16-bit timer/counter interrupt Select Latching upon reading TCHR Latch Lower 8-bit latch Read data * 1 t inst (Falling) Pin P40/INT20/EC Edge (Rising) Edge detection circuit Edge Count clock selector Count clock *tinst : Instruction cycle Count clock selector Selects the internal count clock (1 tinst) in interval timer function mode. Selects the output of the edge detection circuit in counter function mode. The selected signal will be used as the clock by the 16-bit counter (TCR register) to count up. Edge detection circuit Operates in counter function mode and detects the rising and/or falling edges of a pulse that is input from the EC3 pin. 289 CHAPTER 12 16-BIT TIMER/COUNTER Timer count register (TCR) Stores a value from which the 16-bit counter counts up. If the counter value overflows, the TMCR register interrupt request flag bit is set (TMCR: TCEF=1). Timer control register (TMCR) Selects a function, enables and disables operation, controls interrupts, and checks the status. Lower 8-bit latch Stores the lower 8 bits of the 16-bit counter when the TCR register upper 8-bit value (TCHR) is read. Since the lower 8-bit value of the counter (TCLR) is read from this lower 8-bit latch, a correct 16-bit counter value can be read even while the counter is counting up. If, while the counter is operating, the lower 8-bit value is read before the upper 8-bit value, a correct value may not be read, depending on the counter carry. Therefore, always use a word transfer instruction to read the TCR register. Interrupt related to the timer/counter IRQ8: Generates an interrupt request if interrupt request output is enabled (TMCR: TCE = 1) when the counter value overflows either in interval timer or counter function mode. 290 12.3 Pin of the 16-bit Timer/Counter 12.3 Pin of the 16-bit Timer/Counter This section describes the pin related to the 16-bit timer/counter and shows a block diagram. I Pin Related to the 16-bit Timer/Counter The pin related to the 16-bit timer/counter is the P40/INT20/EC pin. It functions both as a general-purpose input port (P84) and as an external pulse input pin for the counter (EC). EC: Counts a prespecified edge of a pulse that is input to this pin in counter function mode. When using this pin in counter function mode, set the P40/INT20/EC pin as the input port for the port data direction register (bit 0 of DDR4 = 0). I Block Diagram of the Pin Related to the 16-bit Timer/Counter Figure 12.3-1 Block Diagram of 16-Bit Timer/Counter Pins To external interrupt circuit Stop/watch mode External interrupt input enabled Internal data bus PDR (port data register) Stop/watch mode PDR read Port 4 pull-up resistor control register Pull-up resistor About 50 k Pch PDR read (at bit manipulation instruction) Output latch PDR write Pch Pin DDR (Port data direction register) Nch P40/INT20/EC DDR write Stop/watch mode (SPL = 1) DDR read DDR (port data direction register) SPL: Pin state setting pin in the standby control register (STBC) 291 CHAPTER 12 16-BIT TIMER/COUNTER Reference: If "pull-up resistor available" is selected in the port 4 pull-up resistor control register, the pins are set to the "H" level (pull-up state), not the high impedance state, in stop/watch mode (SPL bit of STBC = 1). However, the pull-up is disabled during a reset and the pins enter the Hi-z state. 292 12.4 Registers of the 16-bit Timer/Counter 12.4 Registers of the 16-bit Timer/Counter This section describes the registers related to the 16-bit timer/counter. I Registers Related to the 16-bit Timer/Counter Figure 12.4-1 Registers Related to the 16-bit Timer/Counter TMCR (timer control register) Address 003CH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCS R/W Initial value --000000B TCR TCS1 TCS0 TCEF TCIE W R/W R/W R/W R/W TCR (timer count register) Upper bits (TCHR) Address 003DH R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B ......While the counter is stopped ......While the counter is operating Lower bits (TCLR) Address 003EH R/W R R/W : Read/write enabled R : Read only : Undefined R/W R R/W R R/W R R/W R R/W R R/W R R/W R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B ......While the counter is stopped ......While the counter is operating 293 CHAPTER 12 16-BIT TIMER/COUNTER 12.4.1 Timer Control Register (TMCR) The timer control register (TMCR) selects a 16-bit timer/counter function (either the interval timer or counter function), sets the operating conditions, enables or disables operation, clears the counter, controls interrupts, and checks the status. I Timer Control Register (TMCR) Figure 12.4-2 Timer Control Register (TMCR) Address 003CH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value --000000B TCR TCS1 TCS0 TCEF TCIE TCS W R/W R/W R/W R/W R/W TCS Counter start bit Disables or stops the count operation. Enables or starts the count operation. Interrupt request enable bit Disables interrupt request output. Enables interrupt request output. Interrupt request flag bit 0 1 TCIE 0 1 TCEF 0 1 Read No counter overflow occurs. A counter overflow occurs. Write The bit is cleared. No change and no influence on others TCS1 TCS0 Counter operation mode select bit Interval timer operation Counter operation Detects the falling edge of external input. Detects the rising edge of external input. Detects both edges of external input. 0 0 1 1 TCR 0 1 0 1 Counter clear bit Clears the counter. There is no effect on operation. R/W : Read/write enabled W : Write only - : Unused : Initial value 0 1 294 12.4 Registers of the 16-bit Timer/Counter Table 12.4-1 Functions of the Timer Control Register (TMCR) Bits Bit name Bit 7 Bit 6 Unused bits * * * * Function The read value is undefined. Writing has no effect on operation. Bit 5 TCR: Counter clear bit Clears the timer count register (TCR). Writing 0 to this bit clears the timer count register to 0000B. Writing 1 to this bit has no effect and has no effect on other bits. Reference: If this bit is read, the value is always 1. * Switches the interval timer and counter functions. Setting these bits to 00B selects the interval timer function that results in operation using the internal count clock. * Selecting an edge to be detected (falling, rising, or both) from the external count clock causes operation as a 16-bit counter. Note: When using the counter function (when TCS1 and TCS0 are not 00B), set the P40/INT20/EC pin as an input port. Set to 1 if the counter overflows. Setting this bit and the interrupt request enable bit (TCIE) to 1 outputs an interrupt request. Cleared to 0 for a write. Setting this bit to 1 has no effect and does not affect operation. Enables or disables interrupt request output to the CPU. Setting this bit and the interrupt request flag bit (TCEF) to 1 outputs an interrupt request. Starts and stops the counter. Writing 1 to this bit starts the count operation of the timer count register (TCR), which counts up according to the count clock. Writing 0 to this bit stops the count operation, and the TCR retains the counter value. Bit 4 Bit 3 TCS1, TCS0: Counter operation mode select bits Bit 2 TCEF: Interrupt request flag bit * * * * * * * Bit 1 TCIE: Interrupt request enable bit Bit 0 TCS: Starts or stops the counter. Note: When clearing the interrupt request flag bit (TMCR: TCEF), do not overwrite the interrupt request enable bit (TMCR: TCIE) at the same time. 295 CHAPTER 12 16-BIT TIMER/COUNTER 12.4.2 16-bit Timer Count Register (TCR) The timer count register (TCR) is a 16-bit up counter. The counter counts up from the setting value written in this register. I Timer Count Register (TCR) Figure 12.4-3 "16-bit Timer Count Register (TCR)" shows the bit configuration of the 16-bit timer count register. Figure 12.4-3 16-bit Timer Count Register (TCR) Upper byte (TCHR) Address 003DH R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B ......While the counter is stopped ......While the counter is operating Lower byte (TCLR) Address 003EH R/W R R/W : Read/write enabled R : Read only R/W R R/W R R/W R R/W R R/W R R/W R R/W R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B ......While the counter is stopped ......While the counter is operating Both in the interval timer and counter function modes, set a counter initial value in this register while the counter operation is disabled (TMCR: TCS=0). When the counter operation is enabled (TMCR: TCS=1), the counter counts up from the value written in this register. While the counter is stopped (TMCR: TCS=0), the TCR register maintains its value. If the counter is cleared (TMCR: TCR=0), the TCR register (counter) becomes 0000H. After the counter is cleared, writing a value in the TCR register sets the counter to the value written. You can calculate the value in the TCR register in interval timer mode as follows. Note that the instruction cycle is the oscillator frequency divided into four cycles (4/Fc). TCR register value = 216 - (Interval time/Instruction cycle) Set the upper 8 bits as the TCHR register and the lower 8 bits as the TCLR register. Note: The value that is set in this register is valid only when the counter is started for the first time. The counter, if it overflows, counts up from 0000H. A value must be written in this register while the counter is stopped (TMCR: TCS=0). A value can be read from this register even while the counter is operating. Always use a word transfer instruction (such as MOVW A, 003DH) to read this register. 296 12.5 16-bit Timer/Counter Interrupts 12.5 16-bit Timer/Counter Interrupts A 16-bit timer/counter interrupt is caused by: * An overflow in interval timer function mode (FFFFH --> 0000H) * An overflow in the 16-bit counter function mode (FFFFH --> 0000H) I Interrupts in Interval Timer Function Mode If the counter counts up from the defined counter value according to the internal count clock until it overflows, the interrupt request flag bit (TMCR: TCEF) is set to 1. If, at this time, the interrupt request enable bit is set to Enabled (TMCR: TCIE=1), an interrupt request (IRQ8) occurs in the CPU. Use the interrupt processing routine to write 0 to the TCEF bit and clear the interrupt request. If the counter is cleared (TMCR: TCR=0) and the counter value overflows at the same time, the TCEF bit is not set. While the TCEF bit is 1, setting the TCIE bit from Disabled to Enabled (0 to 1) immediately causes an interrupt request. The TCEF bit is set whenever the counter value overflows regardless of the value in the TCIE bit. I Interrupts in Counter Function Mode If the counter counts up from the defined counter value each time preset edge is detected until it overflows, the interrupt request flag bit (TMCR: TCEF) is set to 1. If, at this time, the interrupt request enable bit is set to Enabled (TMCR: TCIE=1), an interrupt request (IRQ8) occurs in the CPU. Use the interrupt processing routine to write 0 to the TCEF bit and clear the interrupt request. If the counter is cleared (TMCR: TCR=0) and the counter value overflows at the same time, the TCEF bit is not set. While the TCEF bit is 1, setting the TCIE bit from Disabled to Enabled (0 to 1) immediately causes an interrupt request. The TCEF bit is set whenever the counter value overflows regardless of the value in the TCIE bit. I Register Related to the Interrupts of the 16-bit Timer/Counter and the Vector Table Table 12.5-1 Register Related to the Interrupts of the 16-bit Timer/Counter and the Vector Table Interrupt name IRQ8 Interrupt level setting register Register ILR3 (007DH) Bit to be set L81 (bit 1) L80 (bit 0) Vector table address Upper FFEAH Lower FFEBH For the operation of interrupts, see Section 3.4.2 "Interrupt Processing". 297 CHAPTER 12 16-BIT TIMER/COUNTER 12.6 Operation of the Interval Timer Function This section describes the operation of the interval timer function of the 16-bit timer/ counter. I Operation of the Interval Timer Function For interval timer function operation, the setting shown in Figure 12.6-1 "Setting the Interval Timer Function" is necessary. Figure 12.6-1 Setting the Interval Timer Function bit7 TMCR bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCS TCR TCS1 TCS0 TCEF TCIE TCHR Set to the initial value of the counter (upper 8 bits) : Used 1 : Set to 1 0 : Set to 0 TCLR Set to the initial value of the counter (lower 8 bits) If the counter is started (TMCR: TCS=1), the counter starts counting up from the value in the TCR register on every rising edge of the internal count clock (1 tinst: the oscillator frequency divided into four cycles). If the counter overflows (FFFFH --> 0000H), the interrupt request flag bit is set (TMCR: TCEF=1). After an overflow, the counter starts counting up from 0000H. Figure 12.6-2 "Operation of the Interval Timer" shows the operation of the interval timer. 298 12.6 Operation of the Interval Timer Function Figure 12.6-2 Operation of the Interval Timer Counter value FFFFH 0080H 0000H Timer cycle TCR value (0000H) Timer cycle Changing the TCR value *1(0080H) The program clears the counter (TMCR: TCR=0) Overflow *2 Time Cleared by the program TCEF bit TCS bit Start Stop Restart Stop *1: The timer operation is stopped and the TCR value changes (0000H --> 0080H). Timer operation then starts again. *2: The counter, when an overflow occurs, starts counting from 0000H. Note: Do not write a value to the TCR register while the interval timer function is operating (TMCR: TCS=1) 299 CHAPTER 12 16-BIT TIMER/COUNTER 12.7 Operation of the Counter Function This section describes the operation of the counter function of the 16-bit timer/ counter. I Operation of the Counter Function To the counter function operation, the setting shown in Figure 12.7-1 "Setting the Counter Function", "Setting the counter function," is necessary Figure 12.7-1 Setting the Counter Function bit7 DDR8 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TMCR - - TCR TCS1 TCS0 TCEF TCIE 1 Other than 00 TCS TCHR Set to the initial value of the counter (upper 8 bits) : Used x : Not used 1 : Set to 1 0 : Set to 0 TCLR Set to the initial value of the counter (lower 8 bits) If the counter is started (TMCR: TCS=1), the counter starts counting up from the value in the TCR register whenever the prespecified edge of a pulse that is input to the EC pin (the external count clock) is detected. If the counter overflows (FFFFH --> 0000H), the interrupt request flag bit is set (TMCR: TCEF=1). Then, if the next prespecified edge is input, the counter starts counting up from 0000H.Figure 12.7-2 "16-bit Counter Operation" shows the operation when the counter operation mode select bits (TMCR: TCS1, TCS0) are set to 11B (detecting both edges) and the TCR register to 0000H. 300 12.7 Operation of the Counter Function Figure 12.7-2 16-bit Counter Operation External input pulse (EC pin input waveform) Counter value FFFFH Cleared by the program 0000H TCEF bit TCS bit Note: Do not write a value to the TCR register while the counter function is operating (TMCR: TCS=1) 301 CHAPTER 12 16-BIT TIMER/COUNTER 12.8 Status of the 16-bit Timer/Counter in Each Mode This section describes the operations of switching to the sleep and stop modes and of receiving a suspend request while the 16-bit timer/counter is operating. I Operation in Low Power Consumption (Standby) Mode and when the Counter is Suspended Figure 12.8-1 "Operation of the Counter in Low Power Consumption (Standby) Mode and when the Counter is Suspended" shows the status of the counter value upon switching to the sleep and stop modes and upon receiving a suspend request while the interval timer or counter function is operating. In stop mode, the counter stops, retaining the value. If stop mode is cleared by an external interrupt, the counter starts counting from the retained value. Therefore, the initial interval time and the input pulse edge count cannot be correct values. After stop mode is cleared, initialize the 16-bit timer/counter again. The movement for "transition to watch mode (TMD = 1)" and "release of watch mode (TMD = 0)" is the same as that for "transition to stop mode" and "release of stop mode". Watch mode is released by a clock interrupt and external interrupt. Figure 12.8-1 Operation of the Counter in Low Power Consumption (Standby) Mode and when the Counter is Suspended Counter value FFFFH 0000H Timer cycle TCR value (0000H) Stop request Cleared by the program Time Oscillation stabilization wait time TCEF bit Suspend TCS bit SLP bit (STBC register) STP bit (STBC register) Start Sleep cleared by IRQ8 Stop Sleep Stop Restart Stop cleared by an external interrupt The counter value is retained while the counter is stopped (TMCR: TCS=0). 302 12.9 Notes on Using the 16-bit Timer/Counter 12.9 Notes on Using the 16-bit Timer/Counter This section contains notes on using the 16-bit timer/counter. I Notes on Using the 16-bit Timer/Counter Error In interval timer function mode, starting of the counter by the program and starting of count-up by the internal count clock are asynchronous. Thus, an error of one less instruction cycle at the most may exist in the time elapsing until the counter overflows. Figure 12.9-1 "Error Until the Count Operation is Started" shows an error until the count operation is started. Figure 12.9-1 Error Until the Count Operation is Started Timer count register (TCR) value Setting value: n Count clock n+1 n+2 n+3 n+4 One cycle Error Setting value: n cycles Counter started Notes on setting the program * Write a value to the TCR register while the counter operation is stopped (TMCR: TCS=0). A value can be read even while the counter is counting. However, always use a word transfer instruction (such as MOVW A, dir) to read this register. Change the counter operation mode select bits (TMCR: TCS1, TCS0) while the counter is stopped (TMCR: TCS=0), an interrupt is disabled (TMCR: TCIE=0), and the interrupt request is cleared (TCEF=0). If the interrupt request flag bit (TMCR: TCEF) is 1 and the interrupt request is enabled (TMCR: TCIE=1), the counter cannot restored after interrupt processing. Always clear the TCEF bit. If the counter is cleared (TMCR: TCR=0) and the counter value overflows at the same time, the interrupt request flag bit (TMCR: TCEF) is not set. * * * 303 CHAPTER 12 16-BIT TIMER/COUNTER 12.10 Programe Example of the 16-bit Timer/Counter This section contains sample programs for the 16-bit timer/counter. I Program Example of the Interval Timer Function Processing specification * * * * Generate a 20-ms interval timer interrupt. Use the interrupt processing routine to reset the TCR register and generate an interrupt repeatedly. The following shows the TCR register value for an interval time of 20 ms when the oscillator frequency is 12.5 MHz. TCR register value = 216 - (20 ms / (4/12.5 MHz)) = 3036 (0BDCH) Coding example TMCR TCHR TCLR TCEF TCS ILR3 INT_V EQU EQU EQU EQU EQU EQU 003CH 003DH 003EH TMCR:2 TMCR:0 007DH ;Address of the timer control reister ;Upper address of the timer count register ;Lower address of the timer count register ;Definition of the interrupt request flag bit ;Definition of the count start bit ;Address of the interrupt level setting register ; [DATA SEGMENT] DSEG ABS ORG 0FFEAH IRQ8 DW WARI ;Setting interrupt vector INT_V ENDS ;----------Main program---------------------------------------------------------CSEG ; [CODE SEGMENT] ;Stack pointer (SP) and other are assumed to have been initialized : CLRI ;Interrupt disable CLRB TCS ;Count operation stop MOV ILR3,#11111101B ;Setting interrupt level (level 1) MOV TCHR,#0BH ;Set the 25 ms timer data MOV TCLR,#0DCH MOV TMCR,#00100011B ;Retain the counter value, set the interval timer operation, clearing the interrupt request flag, enabling interrupt request output, and start counter operation SETI ;Interrupt enable : ;----------Interrupt program---------------------------------------------------WARI MOV TMCR,#00100000B ;Clearing interrupt request flag and stop counter operatin PUSHW A XCHW A,T PUSHW A MOVW A,TCHR ;Add the time from the overflow to the interrupt acceptance 304 12.10 Programe Example of the 16-bit Timer/Counter MOVW CLRC ADDCW MOVW MOV A,#0BDCH A TCHR,A TMCR,#00100011B ;25 ms timer data (at 10 MHz) ;Here, an overflow during addition is not considered ;Strictly, the time while the counter is stopped must be added ;Enable the interrupt, and start counting : User processing POPW A XCHW A,T POPW A RETI ENDS ; ------------------------------------------------------------------------------END 305 CHAPTER 12 16-BIT TIMER/COUNTER I Program Example of the Counter Function Processing specifications * * * Generate an interrupt whenever the rising edge of a pulse being input to the EC pin is counted 10,000 times. Use the interrupt processing routine to reset the TCR register and generate an interrupt repeatedly. The following shows the TCR register value at which the counter overflows when a rising edge is detected 10,000 times. * TCR register value = 216 - 10000 = 65536 - 10000 = 55536 = D8F0H Coding example DDR4 TMCR TCHR TCLR TCEF TCS ILR3 INT_V EQU EQU EQU EQU EQU EQU EQU 0011H 003CH 003DH 003EH TMCR:2 TMCR:0 007DH ;Address of the timer control reister ;Upper address of the timer count register ;Lower address of the timer count register ;Definition of the interrupt request flag bit ;Definition of the count start bit ;Address of the interrupt level setting register ; [DATA SEGMENT] DSEG ABS ORG 0FFEAH IRQ8 DW WARI ;Setting interrupt vector INT_V ENDS ;----------Main program---------------------------------------------------------CSEG ; [CODE SEGMENT] ;Stack pointer (SP) and other are assumed to have been initialized : MOV DDR8,#00000000B ;P40/INT20/EC CLRI ;Interrupt disable CLRB TCS ;Count operation stop MOV ILR3,#11111101B ;Setting interrupt level (level 1) MOV TCHR,#0D8H ;Initialize the counter value MOV TCLR,#0F0H MOV TMCR,#00110011B ;Retain the counter value, set the counter function (selecting the rising edge of external input), clearing the interrupt request flag, enabling the interrupt request output, and enabling the counter operation SETI ;Interrupt enable ;----------Interrupt program----------------------------------------------------WARI CLRB TCEF ;Clearing interrupt request flag PUSHW A XCHW A,T PUSHW A CLRB TCS ;Stop counter operation MOV A,#0D8H ;Initialize the counter value MOV TCHR,A ;Here, the pulse after overflow is ignored MOV A,#0F0H MOV TCLR,A SETB TCS ;Restart the count operation, and start counting 10,000 pulses from here : User processing : POPW A 306 12.10 Programe Example of the 16-bit Timer/Counter XCHW A,T POPW A RETI ENDS ; ------------------------------------------------------------------------------END 307 CHAPTER 12 16-BIT TIMER/COUNTER 308 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) This chapter describes the functions and operation of external interrupt circuit 1 (edge). 13.1 "Overview of the External Interrupt Circuit 1" 13.2 "Configuration of the External Interrupt Circuit 1" 13.3 "Pins of the External Interrupt Circuit 1" 13.4 "Registers of the External Interrupt Circuit 1" 13.5 "External Interrupt Circuit 1 Interrupts" 13.6 "Operation of the External Interrupt Circuit 1" 13.7 "Program Example of the External Interrupt Circuit 1" 309 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 13.1 Overview of External Interrupt Circuit 1 External interrupt circuit 1 detects the edge of signals that are input from the eight external interrupt pins and outputs an interrupt request to the CPU. I Functions of External Interrupt Circuit 1 External interrupt circuit 1 detects the specified edges of signals that are input to the external interrupt pins and outputs interrupt requests to the CPU. These interrupts can be used to wake up the device from standby mode and restore the normal operating state (the main-RUN state). * * * External interrupt pins: 4 pins (P60/INT10 to P63/INT13/X0A) External interrupt sources: Input of edge signals to the external interrupt pins (rising or falling edge). Interrupt control: Used to enable or disable an interrupt request output according to the interrupt request enable bits (EIE0 to EIE3) of external interrupt 1 control registers 1 and 2 (EIC1, EIC2). Interrupt flag: Used to detect the specified edge according to the external interrupt request flag bits (EIR0 to EIR3) of external interrupt 1 control registers 1 and 2 (EIC1, EIC2). Interrupt requests: Generated according to external interrupt sources (IRQ0, IRQ1). * * 310 13.2 Configuration of the External Interrupt Circuit 1 13.2 Configuration of the External Interrupt Circuit 1 External interrupt circuit 1 consists of the following two blocks: * Edge detection circuits (0 to 7) * External interrupt control registers 1, 2, 3, and 4 (EIC1, EIC2, EIC3, and EIC4) I Block Diagram of External Interrupt Circuit 1 Figure 13.2-1 Block Diagram of External Interrupt Circuit 1 Edge detection circuit 1 Selector 1 Edge detection circuit 0 1 2 3 P61/INT11 Pin P60/INT10 Pin 2 3 Selector EIR1 SEL3 SEL2 EIE1 EIR0 SEL1 SEL0 EIE0 External interrupt control register EIC1 IRQ0 Edge detection circuit 3 Selector 1 Edge detection circuit 2 1 2 3 P63/INT13/X0A Pin P62/INT12 Pin 2 3 Selector EIR3 SEL7 SEL6 EIE3 EIR2 SEL5 SEL4 EIE2 External interrupt control register EIC2 IRQ1 Edge detection circuit When the edge polarity of the signal that is input to external interrupt circuit 1 pins (INT10 to INT13) matches the edge polarity selected by the EIC1 or EIC2 register (specified by the SEL0 to SEL7 bits), the corresponding external interrupt request flag bit (EIC1:EIR0, EIR1/EIC2:EIR2, EIR3) is set to "1". 311 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) External interrupt control registers (EIC1, EIC2) The EIC1 to EIC2 registers are used to select edges, enable and disable interrupt requests, and check for interrupt requests. I Interrupt sources of external interrupt circuit 1 IRQ0: This interrupt request is generated if the edge of the selected polarity is input to external interrupt pin INT0/INT1 when the interrupt request output is enabled. IRQ1: This interrupt request is generated if the edge of the selected polarity is input to external interrupt pin INT2/INT3 when the interrupt request output is enabled. 312 13.3 Pins of the External Interrupt Circuit 1 13.3 Pins of the External Interrupt Circuit 1 This section describes the pins and provides a block diagram of the pins. I Pins for External Interrupt Circuit 1 External interrupt circuit 1 has four external interrupt pins. These pins function as an external interrupt input (hysteresis input) or general-purpose input/ output port 6. Pins P60/INT10 to P63/INT13/X0A continuously function as external interrupt inputs. If, however, an interrupt request output is disabled, no interrupt is output. Pin states can always be read directly from the port data register (PDR6). Table 13.3-1 Pins for External Interrupt Circuit 1 External interrupt pin P60/INT10 P61/INT11 P62/INT12 P63/INT13/X0A Used as an external interrupt input (when interrupt request output is enabled) INT10 (EIC1:EIE0=1) INT11 (EIC1:EIE1=1) INT12 (EIC2:EIE2=1) INT13 (EIC2:EIE3=1) Used as a general-purpose input/output port (when interrupt request output is disabled) P60 (EIC1:EIE0=0) P61 (EIC1:EIE1=0) P62 (EIC2:EIE2=0) P63 (EIC2:EIE3=0) INT10 to INT13: These pins generate the corresponding interrupt when an edge with the selected polarity is input to these pins. 313 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) I Block Diagram of Pins for External Interrupt Circuit 1 Figure 13.3-1 Block Diagram of Pins for External Interrupt Circuit 1 To external interrupt circuit Stop/watch mode (SPL = 1) External interrupt input enabled Pull-up resistor About 50 k Pull-up control register Internal data bus Pch PDR (port data register) Stop/watch mode (SPL = 1) P63 only Pin PDR read To X0A Selecting subclock P60/INT10 P61/INT11 P62/INT12 P63/INT13/X0A SPL: Pin state setting pin in the standby control register (STBC) Reference: If "pull-up resistor available" is selected in the pull-up control resistor, the pins are set to the "H" level (pull-up state), not the high impedance state, in stop/watch mode (SPL bit of STBC = 1). However, the pull-up is disabled during a reset and the pins are set to the Hi-z state. Note: If "rising edge", "falling edge", or "both edges" is selected with the edge polarity selection bit in stop mode (STBC: SPL = 1), input interrupts continue to be input and are not blocked. Fix the pin voltage via the pull-up option setting register, external pull-up resistor, or external pull-down resistor. 314 13.4 Registers of the External Interrupt Circuit 1 13.4 Registers of the External Interrupt Circuit 1 This section describes the registers for external interrupt circuit 1. I External Interrupt Circuit 1 Registers Figure 13.4-1 Registers for External Interrupts EIC1 (External interrupt control register 1) Address 003FH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B EIR1 SEL3 SEL2 EIE1 EIR0 SEL1 SEL0 EIE0 R/W R/W R/W R/W R/W R/W R/W R/W IRQ0/INT11 EIC2 (External interrupt control register 2) Address 0040H bit7 bit6 bit5 bit4 bit3 IRQ0/INT10 bit2 bit1 bit0 Initial value 00000000B EIR3 SEL7 SEL6 EIE3 EIR2 SEL5 SEL4 EIE2 R/W R/W R/W R/W R/W R/W R/W R/W IRQ1/INT13 R/W : Can be read and written X : Undefined IRQ1/INT12 315 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 13.4.1 External Interrupt Control Register 1 (EIC1) External interrupt control register 1 (EIC1) is used to select the edge polarity and control interrupts for external interrupt pins INT10 and INT11. I External Interrupt Control Register 1 (EIC1) Figure 13.4-2 External Interrupt Control Register 1 (EIC1) Address Initial value Interrupt request enable bit Disables interrupt request output Enables interrupt request output Edge polarity selection bit No edge detection Rising edge Falling edge Both edges External interrupt request flag bit Write Read The specified edge has not been input Clears this bit The specified edge has been input Unchanged; no other effect Interrupt request enable bit Disables interrupt request output Enables interrupt request output Edge polarity selection bit No edge detection Rising edge Falling edge Both edges External interrupt request flag bit Write Read The specified edge has not been input Clears this bit Can be read and written Unused The specified edge has been input Unchanged; no other effect 316 13.4 Registers of the External Interrupt Circuit 1 Table 13.4-1 Functions of the External Interrupt Control Register 1 (EIC1) Bits Bit * EIR1: INT11 external interrupt request flag bit Description This bit is set to "1" when the edge selected by the INT11 edge polarity selection bits (SEL3 and SEL2 bits of EIC1) is input to external interrupt pin INT11. When this bit and the INT11 interrupt request enable bit (EIE1 bit of EIC1) are "1", an interrupt request is output. Writing "0" clears this bit. Writing "1" does not change the bit value (has no effect on operation). These bits are used to select the polarity of the edge that becomes the interrupt source of the pulse input to external interrupt pin INT11. When "00" is written to these bits, edge detection is not used. When "01B" is written, rising edge mode is used. When "10" is written, falling edge mode is used. When "11B" is written, both rising and falling modes are used. To change these bits, always write "0" to EIR0. This bit is used to enable or disable interrupt request output to the CPU. When this bit and the INT11 external interrupt request flag bit (EIR1) are "1", an interrupt request is output. This bit is set to "1" when the edge selected by the INT10 edge polarity selection bits (SEL1 and SEL0 bits of EIC1) is input to external interrupt pin INT10. When this bit and the INT10 interrupt request enable bit (EIE0 bit of EIC1) are "1", an interrupt request is output. Writing "0" clears this bit. Writing "1" does not change the bit value (has no effect on operation). These bits are used to select the polarity of the edge that becomes the interrupt source of the pulse input to external interrupt pin INT10. When "00" is written to these bits, edge detection is not used. When "01B" is written, rising edge mode is used. When "10" is written, falling edge mode is used. When "11B" is written, both rising and falling modes are used. To change these bits, always write "0" to EIR0. This bit is used to enable or disable interrupt request output to the CPU. When this bit and the INT10 external interrupt request flag bit (EIR0) are set to "1", an interrupt request is output. bit7 * * * bit6 bit5 SEL3, SEL2: INT11 edge polarity selection bits * * * bit4 EIE1: INT11 interrupt request enable bit * * EIR0: INT10 external interrupt request flag bit bit3 * * * bit2 bit1 SEL1, SEL0: INT10 edge polarity selection bits * * * bit0 EIE0: INT10 interrupt request enable bit * 317 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 13.4.2 External Interrupt Control Register 2 (EIC2) External interrupt control register 2 (EIC2) is used to select the edge polarity and control interrupts for external interrupt pins INT12 and INT13. I External Interrupt Control Register 2 (EIC2) Figure 13.4-3 External Interrupt Control Register 2 (EIC2) Address Initial value Interrupt request enable bit Disables interrupt request output Enables interrupt request output Edge polarity selection bit No edge detection Rising edge Falling edge Both edges External interrupt request flag bit Read The specified edge has not been input Write Clears this bit The specified edge has been input Unchanged; no other effect Interrupt request enable bit Disables interrupt request output Enables interrupt request output Edge polarity selection bit No edge detection Rising edge Falling edge Both edges External interrupt request flag bit Read Write The specified edge has not been input Can be read and written Unused Clears this bit The specified edge has been input Unchanged; no other effect 318 13.4 Registers of the External Interrupt Circuit 1 Table 13.4-2 Functions of the External Interrupt Control Register 2 (EIC2) Bits Bit * EIR3: INT13 external interrupt request flag bit Description This bit is set to "1" when the edge selected by the INT13 edge polarity selection bits (SEL7 and SEL6 bits of EIC2) is input to external interrupt pin INT13. When this bit and the INT13 interrupt request enable bit (EIE3 bit of EIC2) are set to "1", an interrupt request is output. Writing "0" clears this bit. Writing "1" does not change the bit value (has no effect on the operation). These bits are used to control the input edge polarity mode of the INT13 pin. When "00" is written to these bits, edge detection is not used. When "01B" is written, rising edge mode is used. When "10" is written, falling edge mode is used. When "11B" is written, both rising and falling modes are used. To change these bits, always write "0" to EIR3. This bit is used to enable or disable interrupt request output to the CPU. When this bit and the INT13 external interrupt request flag bit (EIR3) are "1", an interrupt request is output. This bit is set to "1" when the edge selected by the edge polarity selection bits (SEL5 and SEL4 bits of EIC2) is input to external interrupt pin INT12. When this bit and the INT12 interrupt request enable bit (EIE2 bit of EIC2) are "1", an interrupt request is output. Writing "0" clears this bit. Writing "1" does not change the bit value (has no effect on operation). These bits are used to control the input edge polarity mode of the INT12 pin. When "00" is written to these bits, edge detection is not used. When "01B" is written, rising edge mode is used. When "10" is written, falling edge mode is used. When "11B" is written, both rising and falling modes are used. To change these bits, always write "0" to EIR2. This bit is used to enable or disable interrupt request output to the CPU. When this bit and the INT12 external interrupt request flag bit (EIR2) are "1", an interrupt request is output. bit7 * * * bit6 bit5 SEL7, SEL6: INT13 edge polarity selection bits * * * bit4 EIE3: INT13 interrupt request enable bit * * EIR2: INT12 external interrupt request flag bit bit3 * * * bit2 bit1 SEL5, SEL4: INT12 edge polarity selection bits * * * bit0 EIE2: INT12 interrupt request enable bit * 319 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 13.5 External Interrupt Circuit 1 Interrupts External interrupt circuit 1 triggers an interrupt when it detects the specified edge in signals that are input to the external interrupt pins. I Interrupts during External Interrupt Circuit 1 Operation When the specified edge of external interrupt input is detected, the corresponding external interrupt request flag bits (EIR0 to EIR3 bits of EIC1 and EIC2) are set to "1". If the corresponding interrupt request enable bits are enabled (EIE0 to EIE3 bits of EIC1 and EIC2 = 1) at this time, an interrupt request (IRQ0 and IRQ1) is output to the CPU. The external interrupt request flag can be cleared by writing "0". Note: To enable interrupts (EIE0 and EIE1 bits of EIC1 = 1, EIE2 and EIE3 bits of EIC2 = 1) after releasing a reset, be sure to clear the external interrupt request flag bits (EIE0 and EIE1 bits of EIC1 = 1, EIE2 and EIE3 bits of EIC2 = 1) at a time. If the external interrupt request flag bit is "1" and the interrupt request enable bit is enabled, the system cannot return from interrupt processing. Always clear the external interrupt request flag bit as part of the interrupt processing routine. Reference: Waking up the device from stop mode with an interrupt can be performed by using only external interrupt circuits. An interrupt request is generated immediately after the interrupt request enable bit is switched from disabled to enabled (0-->1) when the external interrupt request flag bit is "1". I Registers and Vector Tables for External Interrupt Circuit 1 Interrupts Table 13.5-1 Registers and Vector Tables for External Interrupt Circuit 1 Interrupts Interrupt name IRQ0 IRQ1 ILR1 (007BH) Interrupt level setting register Register Setting bit L01 (bit1) L11 (bit3) L00 (bit0) L10 (bit2) Vector table address Upper FFFAH FFF8H Lower FFFBH FFF9H See 3.4.2 "Interrupt Processing", for more information about the operation during interrupts. I Caution When Changing the Edge Polarity Selection When the INT10 to INT13 edge polarity is changed, always set the corresponding EIR bit to "0". This prevents generation of interrupts by mistake. 320 13.6 Operation of the External Interrupt Circuit 1 13.6 Operation of the External Interrupt Circuit 1 External interrupt circuit 1 can be used to detect the specified edges of signals that are input to the external interrupt pins. This section describes the operation using INT10 as an example. I Operation of External Interrupt Circuit 1 To operate INT0 of external interrupt circuit 1, external interrupt circuit 1 must be set as shown in Figure 13.6-1 "Settings of External Interrupt Circuit 1." Figure 13.6-1 Settings of External Interrupt Circuit 1 bit7 EIC1 EIR1 bit6 SEL3 bit5 SEL2 bit4 EIE1 bit3 EIR0 x bit2 SEL1 x bit1 SEL0 x bit0 EIE0 x : Used bit x : Unused bit bit7 EIC2 EIR3 x bit6 SEL7 x bit5 SEL6 x bit4 EIE3 x bit3 EIR2 x bit2 SEL5 x bit1 SEL4 x bit0 EIE2 x If the edge polarity of the signal input from the external interrupt pin (INT11) matches the edge polarity (SEL2 to SEL3) selected by the external interrupt control register, the corresponding external interrupt request flag bit (EIR1) is set to "1". Without referencing the value of the interrupt request enable bit (EIE1), the external interrupt request bit is set to "1" when the edge polarities match. Figure 13.6-2 "External Interrupt 1 (INT11) Operation" shows the operation when the INT11 pin is used as an external interrupt pin. 321 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) Figure 13.6-2 External Interrupt 1 (INT11) Operation Input waveform to the INT11 pin The program sets the EIE1 bit and simultaneously clears the EIR1 bit. The program clears the interrupt request flag bit. EIR1 bit EIE1 bit SEL3 bit SEL2 bit IRQ0 Leading edge Trailing edge Reference: The pin state can be read directly from the port data register (PDR6) even when the pin is used as an external interrupt input. 322 13.7 Program Example of the External Interrupt Circuit 1 13.7 Program Example of the External Interrupt Circuit 1 This section shows a program example for external interrupt circuit 1. I Program Example for External Interrupt Circuit 1 Processing specifications Generates an interrupt upon detection of the rising edge of a pulse that is input to the INT11 pin. Coding example EIC1 EIR1 SEL2 EIE1 ILR0 EQU EQU EQU EQU EQU 003FH EIC1:7 EIC1:5 EIC1:4 007BH ;External interrupt control register 1 ;Definition of the external interrupt request flag bit ;Definition of the edge polarity selection bit ;Definition of the interrupt request enable bit ;Interrupt level setting register 1 setting INT_V DSEG ABS ;[DATA SEGMENT] ORG 0FFFAH IRQ0 DW WARI ;Interrupt vector setting INT_V ENDS ;-----------Main program---------------------------------------------------------CSEG ;[CODE SEGMENT] ;Assume that the stack pointer (SP) and other registers are already initialized. : CLRI ;Interrupts disabled CLRB EIR1 ;External interrupt request flag cleared MOV ILR1,#11111101B ;Interrupt level set to 1 SETB SEL2 ;rising edge selected SETB EIE1 ;Interrupt request output enabled SETI ;Interrupts enabled : ;----------Interrupt processing routine------------------------------------------WARI CLRB EIR1 ;External interrupt request flag cleared PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;--------------------------------------------------------------------------------END 323 CHAPTER 13 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 324 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) This chapter describes the functions and operation of external interrupt circuit 2 (level). 14.1 "Overview of the External Interrupt Circuit 2 (Level)" 14.2 "Configuration of the External Interrupt Circuit 2" 14.3 "Pins of the External Interrupt Circuit 2" 14.4 "Registers of the External Interrupt Circuit 2" 14.5 "External Interrupt Circuit 2 Interrupts" 14.6 "Operation of the External Interrupt Circuit 2" 14.7 "Program Example of the External Interrupt Circuit 2" 325 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 14.1 Overview of the External Interrupt Circuit 2 (Level) External interrupt circuit 2 detects the level of the signals that are input from eight external interrupt pins and outputs an interrupt request to the CPU. I Functions of External Interrupt Circuit 2 (Level Detection) External interrupt circuit 2 detects an "L" level signal that is input from the external interrupt pins and outputs an interrupt request to the CPU. This interrupt can be used to wake up the device from standby mode and restore the normal operating state (the main-RUN or sub-RUN state). * * * * * External interrupt pins: 8 pins (P40/INT20/EC to P47/INT27/ADST) External interrupt source: Input of an "L" level signal to an external interrupt pin Interrupt control: The external interrupt 2 control register (EIE2) can be used to enable or disable external interrupts. Interrupt flag: The external interrupt request flag bit of the external interrupt 2 flag register (EIF2) indicates detection of an "L" level. Interrupt requests: An interrupt occurs when the external interrupt pin is "Low" (IRQ4). 326 14.2 Configuration of the External Interrupt Circuit 2 14.2 Configuration of the External Interrupt Circuit 2 External interrupt circuit 2 consists of the following three blocks: * Interrupt generation circuit * External interrupt 2 control register (EIE2) * External interrupt 2 flag register (EIF2) I Block Diagram of External Interrupt Circuit 2 Figure 14.2-1 Block Diagram of External Interrupt Circuit 2 External interrupt 2 control register (EIE2) External interrupt 2 flag register (EIF2) IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 IF20 Interrupt generation circuit P40/INT20/EC P41/INT21 /SCK2 P42/INT22 /SO2/SDA P43/INT23 /SI2/SCL P44/INT24 /UCK2 P45/INT25/UO2 P46/INT26/UI2 P47/INT27 /ADST Pin Pin Pin Pin Pin Pin Pin Pin External interrupt 2 request IRQ4 Interrupt generation circuit The interrupt request generation circuit generates an interrupt request signal based on the input signals from the external interrupt pins (INT20 to INT27) and the external interrupt input enable bits. External interrupt 2 control register (EIE2) The external interrupt input enable bits (EIE2: IE20 to IE27) enable or disable "L" level inputs from the corresponding external interrupt pins. External interrupt 2 flag register (EIF2) The external interrupt flag bit (EIF2: IF20) is used to store or clear interrupt request signals. 327 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) External interrupt circuit 2 interrupt sources IRQ4: IRQ4 generates an interrupt to the CPU when an "L" level signal is input to any of the external interrupt pins INT20 to INT27 (pins whose interrupt inputs are enabled). 328 14.3 Pins of the External Interrupt Circuit 2 14.3 Pins of the External Interrupt Circuit 2 This section describes the pins, registers, and interrupt sources for external interrupt circuit 2, and provides a block diagram of the pins. I Pins for External Interrupt Circuit 2 Eight external interrupt pins are used for external interrupt circuit 2. These external interrupt pins function as external interrupt inputs (hysteresis inputs), generalpurpose input/output ports, or resource pins. The P40/INT20/EC to P47/INT27/ADST pins function as external interrupt input pins (INT20 to INT27) when the corresponding pin is set as an input port by the port 4 data direction register (DDR4) and the corresponding external interrupt input is enabled by the external interrupt 2 control register (EIE2). If pins are set as input ports, the pin states can always be read from the port data register (PDR4). Table 14.3-1 "Pins for External Interrupt Circuit 2" shows the pins for external interrupt circuit 2. Table 14.3-1 Pins for External Interrupt Circuit 2 External interrupt pin P40/INT20/EC P41/INT21/SCK2 P42/INT22/SO2/SDA P43/INT23/S12/SCL P44/INT24/UCK2 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST Used as external interrupt input (interrupt input enabled) INT20(EIE2:IE20=1) INT21(EIE2:IE21=1) INT22(EIE2:IE22=1) INT23(EIE2:IE23=1) INT24(EIE2:IE24=1) INT25(EIE2:IE25=1) INT26(EIE2:IE26=1) INT27(EIE2:IE27=1) Used as general-purpose input/ output port (interrupt input disabled) P40(EIE2:IE20=0) P41(EIE2:IE21=0) P42(EIE2:IE22=0) P43(EIE2:IE23=0) P44(EIE2:IE24=0) P45(EIE2:IE25=0) P46(EIE2:IE26=0) P47(EIE2:IE27=0) 329 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) I Block Diagram of Pins for External Interrupt Circuit 2 Figure 14.3-1 Block Diagram of External Interrupt Circuit 2 Pins (INT22 and INT23 Only) To external interrupt circuit Stop/watch mode (SPL = 1) External interrupt input enabled P40, P41, P44, P46, and P47 only To peripheral resource input Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) Pull-up resistor About 50 k PDR read Peripheral resource output P41, P44, and P45 only Port 4 pull-up resistor control register Peripheral resource output enabled Pch PDR read (at bit manipulation instruction) Output latch PDR write Pch Pin DDR (Port data direction register) Nch DDR write Stop/watch mode (SPL = 1) P40/INT20/EC P41/INT21/SCK2 P44/INT24/UCK2 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST DDR read SPL: Pin state setting pin in the standby control register (STBC) Reference: If "pull-up resistor available" is selected in the port 4 pull-up resistor control register, the pins are set to the "H" level (pull-up state), not the high impedance state, in stop/watch mode (SPL bit of STBC = 1). However, the pull-up is disabled during a reset and the pins enter the Hi-z state. 330 14.3 Pins of the External Interrupt Circuit 2 Figure 14.3-2 Block Diagram of External Interrupt Circuit 2 Pins (INT22 and INT23 Only) To external interrupt circuit Stop/watch mode (SPL = 1) External interrupt input enabled To peripheral resource input Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) PDR read Peripheral resource output(*1) PDR read (at bit manipulation instruction) Output latch PDR write Pin Nch P42/INT22/SO2/SDA P43/INT23/SI2/SCL Stop/watch mode (SPL = 1) SPL : Pin state setting pin in the standby control register (STBC) *1 Two peripheral resources outputs are connected to P42. One peripheral resource output is connected to P43. Reference: When a pin is set as an input pin (bits 2 and 3 of DDR4 = 0), the pin enters the high impedance state. If a high-level input state is initially necessary, an external pull-up resistor must be connected. 331 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 14.4 Registers of the External Interrupt Circuit 2 The external interrupt circuit 2 control register (EIE2) is used to enable or disable external interrupt pins. I Registers for External Interrupt Circuit 2 Figure 14.4-1 Registers for External Interrupt 2 EIE2 (External interrupt 2 control register) Address 0 0 5 6H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 R/W R/W R/W R/W R/W R/W R/W R/W EIF2 (External interrupt 2 flag register) Address 0 0 5 7H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IF20 R/W R/W : Can be read and written : Unused Initial value -------0B 332 14.4 Registers of the External Interrupt Circuit 2 14.4.1 External Interrupt 2 Control Register (EIE2) The external interrupt 2 control register (EIE2) is used to enable or disable interrupt inputs to external interrupt pins INT20 to INT27. I External Interrupt 2 Control Register (EIE2) Figure 14.4-2 External Interrupt 2 Control Register (EIE2) Address Initial value 00000000B bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 6H IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Can be read and written : Initial value IE20 to IE27 0 1 External interrupt input enable bit Disables external interrupt input. Enables external interrupt input. Table 14.4-1 Correspondence between the Bits of the External Interrupt 2 Control Register (EIE2) and the External Interrupt Pins Bit name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 External interrupt pin INT27 INT26 INT25 INT24 INT23 INT22 INT21 INT20 333 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) Table 14.4-2 Functions of the External Interrupt 2 Control Register (EIE2) Bits Bit name * Function These bits enable or disable interrupt inputs from external interrupt pins INT20 to INT27. * Setting these bits to "1" sets the corresponding external interrupt pin to function as an external interrupt input pin and to accept external interrupt inputs. * Setting these bits to "0" sets the corresponding external interrupt pin to function as a general-purpose port and not to accept external interrupt inputs. Reference: * If external interrupt pins are used, set the corresponding bit of the port data direction register (DDR4) to "0" to specify that this pin becomes an input. * The state of external interrupt pins can be read directly from the port data register (PDR4) regardless of the state of the external interrupt input enable bits. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IE20 to IE27: External interrupt input enable bits 334 14.4 Registers of the External Interrupt Circuit 2 14.4.2 External Interrupt 2 Flag Register (EIF2) The external interrupt 2 flag register (EIF2) is used to indicate detection of a level interrupt, to clear the interrupt request flag, and to store the interrupt state. I External Interrupt 2 Flag Register (EIF2) Figure 14.4-3 External Interrupt 2 Flag Register (EIF2) Address 0 0 5 7H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IF20 R/W Initial value -------0B IF20 0 External interrupt request flag bit Write Read Interrupt request not detected (an "L" level not detected) Interrupt request detected (an "L" level detected) Clears this bit. Unchanged; no other effect R/W : Can be read and written : Unused : Initial value 1 Table 14.4-3 Functions of the External Interrupt 2 Flag Register (EIF2) Bits Bit name bit7 bit6 bit5 bit4 bit3 bit2 bit1 * * Unused Function During read operations, the values of these bits are undefined. Writing these bits has no effect on operation. * bit0 IF20: External interrupt request flag bit This bit is set to "1" if an "L" level signal is input to the external interrupt pins (INT20 to INT27) for which external interrupt input is enabled. * Writing "0" clears this bit. Writing "1" does not change the bit and has no other effect. Note: Setting the external interrupt input enable bits (EIE2: IE20 to IE27) of the external interrupt 2 control register to "0" only disables external interrupt input. Interrupt requests are output continuously until the IF20 bit is cleared to "0". 335 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 14.5 External Interrupt Circuit 2 Interrupts Input of an "L" level signal to an external interrupt pin triggers an interrupt from external interrupt circuit 2. I Interrupts during External Interrupt Circuit 2 Operation Input of an "L" level to an external interrupt pin for which interrupt input has been enabled sets the external interrupt request flag bit (EIF2: IF20) to "1" and outputs an interrupt request (IRQ4) to the CPU. Write "0" to the IF20 bit in the interrupt handling routine to clear the interrupt request. If the external interrupt request flag bit (EIF2) is set to "1", interrupt requests are output continuously until the IF20 bit is cleared to "0". Output of the interrupt request continues even if input of external interrupts is disabled by the interrupt enable bits (IE20 to IE27) of the external interrupt 2 control register (EIE2). Therefore, always clear the IF20 bit. Also, if an external interrupt pin is still at the "L" level when the IF20 bit is cleared with no external interrupt input disabled, the IF20 bit is immediately set again. If necessary, disable external interrupt input or clear the external interrupt source itself. Reference: Always clear the IF20 bit before enabling CPU interrupts after a reset. The use of external interrupt circuits 1 and 2 enables return from standby mode. Note: An "L" level input to any of the external interrupt pins (INT20 to INT27) generates the same interrupt request (IRQ4). To determine which external interrupt input triggered the interrupt, you must read the port data register (PDR4) before the input changes to an "H" level. Waking up the device from stop mode with in interrupt can be done using only external interrupt circuits 1 and 2. I Register and Vector Table for the External Interrupt Circuit 2 Interrupt Table 14.5-1 Register and Vector Table for the External Interrupt Circuit 2 Interrupt Interrupt name Interrupt level setting register Register ILR2 (007CH) Setting bit L41 (bit1) L40 (bit0) Vector table address Upper part of the address FFF2H Lower part of the address FFF3H IRQ4 See 3.4.2 "Interrupt Processing", for more information about the operation of interrupts. 336 14.6 Operation of the External Interrupt Circuit 2 14.6 Operation of the External Interrupt Circuit 2 External interrupt circuit 2 can be used to detect an "L" level on the external interrupt pin and output an interrupt request to the CPU. I Operation of External Interrupt Circuit 2 Figure 14.6-1 "External Interrupt Circuit 2 Settings" shows the settings required for operation of the external interrupt circuit. Figure 14.6-1 External Interrupt Circuit 2 Settings bit7 EIE2 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 EIF2 IF20 DDR4 : Used : Set to "0" when the corresponding pin is used : Unused Input of an "L" level signal to the corresponding external interrupt pins of INT20 to INT27 for which any of the external interrupt inputs IE20 to IE23 has been enabled outputs an IRQ4 interrupt request to the CPU. Figure 14.6-2 "Operation of External Interrupt 2 (INT20)" shows the operation of external interrupt circuit 2 (with the INT20 pin used). 337 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) Figure 14.6-2 Operation of External Interrupt 2 (INT20) Input waveform to the INT20 pin (an "L" level is detected) External interrupt input enabled Cleared by the interrupt handling routine (Same as IRQ4 state) Operation of interrupt handling routine in response to IRQ4 Can be read at any time Interrupt handling Interrupt handling Reference: The pin state can be read directly from the port data register (PDR4) even when the external interrupt pins are used as external interrupt inputs. 338 14.7 Program Example of the External Interrupt Circuit 2 14.7 Program Example of the External Interrupt Circuit 2 This section shows a program example for external interrupt circuit 2. I Program Example for External Interrupt Circuit 2 Processing specifications Generates an interrupt upon detection of an "L" level signal that is input to the INT40 pin. Coding example DDR4 EIE2 EIF2 EQU EQU EQU 0011H 0056H 0057H ;Address of the port 4 direction register ;Address of the external interrupt 2 control register ;Address of the external interrupt 2 flag register ;Definition of the external interrupt request flag bit ;Address of the interrupt level setting register IF20 EQU EIF2:0 ILR2 EQU 007CH INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFF2H IRQ4 DW WARI ;Interrupt vector setting INT_V ENDS ;----------Main program---------------------------------------------------------CSEG ; [CODE SEGMENT] ;Assume that the stack pointer (SP) and other registers are already initialized. : CLRI ;Interrupts disabled CLRB IF20 ;External interrupt request flag cleared MOV ILR2,#11111110B ;Interrupt level set to 2 MOV DDR4,#00000000B ;The P40/INT20 pin set to input MOV EIE2,#00000001B ;External interrupt input of the P40/INT20 pin is enabled SETI ;Interrupts enabled : ;----------Interrupt handling routine-------------------------------------------WARI MOV EIE2,#00000000B ;External interrupt input of the INT20 pin is disabled CLRB IF20 ;External interrupt request flag cleared PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;-------------------------------------------------------------------------------END 339 CHAPTER 14 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 340 CHAPTER 15 A/D CONVERTER This chapter describes the functions and operations of the A/D converter. 15.1 "Overview of the A/D Converter" 15.2 "Configuration of the A/D Converter" 15.3 "Pins of the A/D Converter" 15.4 "Registers of the A/D Converter" 15.5 "A/D Converter Interrupt" 15.6 "Operation of the A/D Converter" 15.7 "Notes on Using the A/D Converter" 15.8 "Program Example of the A/D Converter" 341 CHAPTER 15 A/D CONVERTER 15.1 Overview of the A/D Converter The 10-bit sequential comparison type A/D converter selects one input signal from the 8-channel analog input pins. It can be activated by software, internal clocks, or an input from the ADST pin. However, the MB89F538/F538L cannot use an input (external clock) from the ADST pin. I A/D Conversion Function The A/D conversion function converts the analog voltage (input voltage) input to an analog input pin to an 10-bit digital value. * * * * One signal can be selected from 8 analog input pins. Conversion speed is 60 instruction cycles (24 s at 10 MHz main clock oscillation). Generates an interrupt when A/D conversion completes. Conversion completion can also be determined by software. The following methods are available to activate A/D conversion: * * * Software activation Continuous activation by a timebase timer output (divide-by-28 main clock oscillation) Continuous activation (ADST) in synchronization with an external clock 342 15.2 Configuration of the A/D Converter 15.2 Configuration of the A/D Converter The A/D converter consists of the following nine blocks: * Clock selector (selects the input clock for activating A/D conversion) * Analog channel selector * Sample and hold circuit * D/A converter * Comparator * Control circuit * A/D data registers (ADDH, ADDL) * A/D control register 1 (ADC1) * A/D control register 2 (ADC2) I Block Diagram of the A/D Converter Figure 15.2-1 A/D Converter Block Diagram A/D control register 2 (ADC2) P47/INT27/ADST (External clock) 28/FCH (Timebase timer output) P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 RESV RESV ADCK ADIE ADMD EXT RESV Clock selector Analog channel selector A/D data registers (ADDH, ADDL) AVR AVcc AVss D/A converter ANS3 ANS2 ANS1 ANS0 ADI ADMV AD A/D control register (ADC1) FCH: Main clock oscillation IRQD Internal data bus Sample hold circuit Comparator Control circuit 343 CHAPTER 15 A/D CONVERTER Clock selector Selects the clock used to activate A/D conversion when continuous activation is enabled (ADC2: EXT = "1"). Analog channel selector This circuit selects one signal from 8 analog input pins. Sample and hold circuit This circuit holds the input voltage of the channel selected by the analog channel selector. The circuit samples and holds the input voltage immediately after the A/D conversion is activated. This allows A/D conversion to proceed without being affected by input voltage variation. D/A converter Generates the voltage corresponding to the value set in the ADDH and ADDL registers. Comparator Compares the sampled and held input voltage with the output voltage of the D/A converter, and determines which voltage is higher or lower. Control circuit The control circuit successively determines the value of each bit of the 10-bit A/D data register, starting from the most significant bit and proceeding to the least significant bit, based on the greater-than/less-than signal from the comparator. When conversion is complete, the circuit sets the interrupt request flag bit (ADC1: ADI). A/D data registers (ADDH/ADDL) The upper two bits of the 10-bit A/D data are stored in the ADDH register, and the lower eight bits are stored in the ADDL register. The result of A/D conversion is stored in the ADDH/ADDL registers. A/D control register 1 (ADC1) Enables and disables the functions of the A/D converter, selects an analog input pin, checks the state, and controls interrupt. A/D control register 2 (ADC2) Selects the input clock, enables or disables interrupts, and selects the function. AD converter interrupts IRQB: When A/D conversion is complete, an interrupt request is issued if interrupt request output is enabled (ADC2: ADIE = 1). 344 15.2 Configuration of the A/D Converter I A/D Converter Power Supply Voltage AVcc Power supply pin for the A/D converter. Use the same potential that is used for Vcc. If extreme A/D conversion accuracy is required, make sure that AVcc is free of Vcc noise or use another power supply. If the A/D converter is not used, still connect this pin to the power supply. AVss Ground pin for the A/D converter. Use same potential as that is used for Vss. If extreme A/D conversion accuracy is required, make sure that AVss is free of Vss noise or use another power supply. If the A/D converter is not used, still connect this pin to ground (GND). AVR Pin to inputting the reference voltage for the A/D converter. 10-bit A/D conversion is performed between AVR and AVss. If the A/D converter is not used, connect it to AVss. 345 CHAPTER 15 A/D CONVERTER 15.3 Pins of the A/D Converter This section describes the pins related to the A/D converter and shows a block diagram. I Pins Related to A/D Converter The pins related to the A/D converter are P47/INT27/ADST and P50/AN0 to P57/AN7. P47/INT27/ADST The P47/INT27/ADST pin functions as a general-purpose input/output port (P47), the external clock input pin for A/D conversion activation (ADST), or an external interrupt pin. To enable the P47/INT27/ADST pin to function as the ADST pin, set this pin as an input port (bit 7 = 0), enable continuous activation (EXT bit of ADC2 = 1), and set the input clock selection bit as external clock input (ADCK bit of ADC2 = 1). ADST: When performing continuous activation in synchronization with external clock input, input an external clock to this pin. P50/AN0 to P57/AN7 The P50/AN0 to P57/AN7 pins function as the output-only port for N-ch open-drain output (P50 to P57) or analog input pins (AN0 to AN7). AN0 to AN7: When using the A/D conversion function, input the analog voltage to be converted to these pins. To enable these pins to function as analog input pins, set "1" in the corresponding bits in the port data register (PDR5), turn off the output transistor, and then select these pins with the analog input channel selection bits (ANS0 to ANS3 of ADC1). Even if the A/D converter is used, those pins that are not used as analog inputs can be used as general-purpose input/ output ports. 346 15.3 Pins of the A/D Converter I Block Diagram of P50/AN0 to P57/AN7 Pins Figure 15.3-1 Block Diagram of Pins P50/AN0 to P57/AN7 A/D converter channel selector Internal data bus A/D converter analog input PDR (port data register) PDR read (for bit manipulation instructions) Output latch PDR write Pch Pin Nch Stop/watch mode (SPL = 1) SPL: Pin state designate bit of the standby control register (STBC) P50/AN0,P51/AN1 P52/AN2,P53/AN3 P54/AN4,P55/AN5 P56/AN6,P57/AN7 347 CHAPTER 15 A/D CONVERTER 15.4 Registers of the A/D Converter This section shows the registers related to the A/D converter. I Registers Related to A/D Converter Figure 15.4-1 Registers Related to the A/D Converter ADC1 (A/D control register 1) Address bit7 bit6 0 0 3 4H bit5 bit4 bit3 bit2 bit1 bit0 AD R/W Initial value ANS2 ANS1 ANS0 ADI ADMV R/W R/W R/W R/W R X00000X0B ADC2 (A/D control register 2) Address 0 0 3 5H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value RESV RESV ADCK ADIE ADMD EXT RESV -0000001B R/W R/W R/W R/W R/W R/W R/W ADDL (A/D data register L) Address bit7 0 0 3 6H D7 bit6 D6 bit5 D5 bit4 D4 bit3 D3 bit2 D2 bit1 D1 bit0 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W ADDH (A/D data register H) Address 0 0 3 7H R/W : Read/write enabled R : Read only : Not used X : Undefined bit7 bit6 bit5 bit4 bit3 bit2 bit1 D9 bit0 D8 Initial value ------XXB R/W R/W 348 15.4 Registers of the A/D Converter 15.4.1 A/D Control Register 1 (ADC1) A/D control register 1 (ADC 1) enables and disables the functions of the A/D converter, selects analog input pins, and checks the operation state. I A/D Control Register 1 (ADC1) Figure 15.4-2 A/D Control Register 1 (ADC1) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AD R/W Initial value 0 0 3 4H ANS2 ANS1 ANS0 ADI ADMV R/W R/W R/W R/W R X00000X0B AD 0 1 ADMV 0 1 A/D conversion activation bit Valid only when this function is activated by software (ADC2:EXT = 0) A/D conversion function has not activated. A/D conversion function has activated. Conversion flag bit Conversion is not in progress. Conversion is in progress. Interrupt request flag bit ADI 0 1 During a read Conversion has not been completed. During a write The bit is cleared. There is no change, and there is no effect on other bits. Conversion is complete. ANS2 ANS1 ANS0 0 0 0 0 1 1 R/W : Read/write enabled R : Read only : Initial value 1 1 x 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 x Analog input channel select bit P50/AN0 Pin P51/AN1 Pin P52/AN2 Pin P53/AN3 Pin P54/AN4 Pin P55/AN5 Pin P56/AN6 Pin P57/AN7 Pin Setting prohibited 349 CHAPTER 15 A/D CONVERTER Table 15.4-1 Functions of the A/D Control Register 1 (ADC1) bits Bit name * Function These bits select a pin to be used as an analog input pin from AN0 to AN7. * When this function is activated by software (ADC2:EXT = 0), these bits can be rewritten when A/D conversion is activated (AD = 1). Note: If the ADMV bit is "1", do not rewrite these bits. Reference: The pins that are not used as analog input pins can be used as general-purpose ports. * Bit 3 ADI: Interrupt request flag bit * * * Bit 2 ADMV: Conversion flag bit In A/D conversion function operation, this bit is set to 1 when A/D conversion is completed. When this bit and the interrupt request enable bit (ADC2:ADIE) are 1, an interrupt request is issued. For a write operation, writing 0 clears this bit. Writing 1 has no effect and no effects on other bits. Bit 7 Bit 6 Bit 5 Bit 4 ANS2, ANS1, ANS0: Analog input channel select bits In the A/D conversion function operation, this bit indicates that conversion is being performed. * During conversion, this bit is set to 1. Reference: This bit is read only. Writing to this bit has no meaning and has no effect on operation. * * * The read value is undefined. Writing has no effect on operation. Bit 1 Unused bit Bit 0 AD: A/D conversion activation bit This bit activates the A/D conversion function from software. * When continuous activation is disabled (ADC2:EXT = 0), setting this bit to 1 activates the A/D conversion function. Note: * Even though 0 is written to this bit, the operation of the A/ D conversion function cannot be stopped. The read value is always 0. * During continuous activation, this bit is ignored. 350 15.4 Registers of the A/D Converter 15.4.2 A/D Control Register 2 (ADC2) The A/D control register 2 (ADC 2) selects the functions of the A/D converter, selects the input clock, enables and disables interrupts and continuous activation, and checks the state. I A/D Control Register 2 (ADC2) Figure 15.4-3 A/D Control Register 2 (ADC2) Address 0 0 3 5H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value -0000001B RESV RESV ADCK ADIE ADMD EXT RESV R/W R/W R/W R/W R/W R/W R/W RESV Reserved bit Be sure to write 1 to this bit. Continuous activation enable bit Activating with the AD bit of the ADC1 register Continuous activation with the clock selected by the ADCK bit Function selection bit A/D conversion function Setting prohibited EXT 0 1 ADMD 0 1 ADIE 0 1 ADCK 0 1 RESV Interrupt request enable bit Disables interrupt request output. Enables interrupt request output. Input clock selection bit Valid only when continuous start is selected (EXT = 1) Timebase timer output (main clock oscillation divided by 28) External clock (P47/INT27/ADST) Reserved bit Be sure to write 00 to this bit. R/W : Read/write enabled : Unused : Initial value 351 CHAPTER 15 A/D CONVERTER Table 15.4-2 Functions the A/D Control Register 2 (ADC2) bits Bit name Bit 7 Bit 6 Bit 5 Unused bit TIM1, TIM0: Reserved bit * * * * Function The read value is undefined. Writing has no effect on operation. Be sure to write 00 to this bit. Bit 4 ADCK: Input clock selection bit When continuous activation is enabled (EXT = 1), this bit selects the input clock that activates the A/D conversion function. When this bit is "0", the timerbase timer (divideby-28 output of main clock oscillation) is selected. When this bit is "1", the P47/INT27/ADST pin is selected. Note: If the main clock oscillation is stopped in subclock mode, the timerbase timer cannot be used to activate continuous mode conversion. * * * * * This bit enables and disables interrupt output to the CPU. When this bit and the interrupt request flag bit (ADC1: ADI) are 1, an interrupt request is output. Reserved bit Be sure to write 0 to this bit. This bit determines whether the A/D conversion function is activated by software or whether it is continuously activated in sync with the input clock. When this bit is set to 0, activating by software using the A/D conversion activation bit is enabled. When this bit is set to 1, continuous activation synchronized with the rising edge of the clock selected by the input clock selection bit (ADC2:ADCK) is enabled. Bit 3 ADIE: Interrupt request enable bit ADMD: Operation selection bit Bit 2 Bit 1 EXT: Continuous activation enable bit * Bit 0 RESV: Reserved bit Note: * Be sure to write 1 to this bit. * The read value is always 1. 352 15.4 Registers of the A/D Converter 15.4.3 A/D Data Registers (ADDH, ADDL) These data registers store the result of A/D conversion. The upper two bits of the 10-bit data correspond to the ADDH register, and the lower eight bits correspond to the ADDL register. I A/D Data Registers (ADDH, ADDL) Figure 15.4-4 "A/D Data Registers (ADDH, ADDL)" shows the bit configuration of the A/D data register. Figure 15.4-4 A/D Data Registers (ADDH, ADDL) ADDH Address 0037H bit7 bit6 bit5 bit4 bit3 bit2 bit1 D9 R/W ADDL Address 0036H bit7 D7 R/W R/W : Read/write enabled : Unused X : Undefined bit6 D6 R/W bit5 D5 R/W bit4 D4 R/W bit3 D3 R/W bit2 D2 R/W bit1 D1 R/W bit0 D0 R/W Initial value XXXXXXXXB bit0 D8 R/W Initial value ------XXB The upper two bits of the 10-bit A/D data correspond to bits 1 and 0 of the ADDH register, and the lower eight bits correspond to bits 7 to 0 of the ADDL register. When A/D conversion function When A/D conversion is activated, the conversion result data is determined after about 60 instruction cycles and is stored in these registers. Between the completion of A/D conversion and the start of the next A/D conversion cycle, read the contents of these registers (conversion result), write 0 to ADI (bit 3) of the ADC1 register, and clear the flag when conversion is complete. 353 CHAPTER 15 A/D CONVERTER 15.5 A/D Converter Interrupt The following function is provided as the A/D converter. * Completion of conversion in A/D conversion function operation I Interrupt for A/D Conversion Function When A/D conversion is completed, the interrupt request flag bit (ADC: ADI) is set to 1. If the interrupt request enable bit is then set to enable (ADC2: ADIE=1), an interrupt request to the CPU (IRQD) occurs. Clear the interrupt request by writing 0 to the ADI bit with the interrupt processing routine. The ADI bit is set when A/D conversion is completed irrespective of the value of the ADIE bit. Reference: If the ADIE bit is changed from "disable" to "enable" (0 --> 1) when the ADI bit is set to 1, an interrupt request occurs immediately. I Register and Vector Table Related to A/D Converter Interrupt Table 15.5-1 Register and Vector Table Related to the A/D Converter Interrupt Interrupt name IRQD Interrupt level setting register Register ILR4 (007EH) Bit to be set LD1 (bit 3) LD0 (bit 2) Vector table address Higher FFE0H Lower FFE1H For the operation of interrupts, see Section 3.4.2 "Interrupt Processing". 354 15.6 Operation of the A/D Converter 15.6 Operation of the A/D Converter The A/D converter is activated by software. I Activating the A/D Conversion Function Activating software Activating of the software for the A/D conversion function requires the setting shown in Figure 15.6-1 "Setting the A/D Conversion Function (When Software Activation)". Figure 15.6-1 Setting the A/D Conversion Function (When Software Activation) bit7 ADC1 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ANS3 ANS2 ANS1 ANS0 ADI ADMV 0 AD 1 ADC2 RESV RESV ADCK ADIE ADMD EXT RESV 0 0 x 0 0 1 ADDH The comparison voltage value is held. ADDL The comparison voltage value is held. : : x: 1: 0: Unused Used bit Unused bit Set 1 Set 0 When A/D conversion is activated, the A/D conversion function starts operation. conversion function can be restarted even during conversion. Continuous activation The A/D For continuous activating of the A/D conversion function, the settings shown in Figure 15.6-2 "Settings for the A/D Conversion Function (Continuous Activation)" are required. Figure 15.6-2 Settings for the A/D Conversion Function (Continuous Activation) bit7 ADC1 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ANS3 ANS2 ANS1 ANS0 ADI ADMV 0 AD x ADC2 RESV RESV ADCK ADIE ADMD EXT RESV 0 0 0 1 1 ADDH The comparison voltage value is held. ADDL The comparison voltage value is held. : : x: 1: 0: Unused Used bit Unused bit Set 1 Set 0 355 CHAPTER 15 A/D CONVERTER When continuous activation is allowed, A/D conversion starts in sync with the rising edge of the selected input clock and the A/D conversion function starts operating. To disable continuous activation, set the EXT bit of ADC2 to 0. Activating by software is enabled. I Operation of A/D Conversion Function A/D converter operation is described in the following. The time from activation to completion of the A/D conversion is about 60 instruction cycles. 1. When A/D conversion is activated, the conversion flag bit is set (ADC1: ADMV = 1) and the set analog input pin is connected to the sample hold circuit. 2. The voltage on the analog input pin is added to the internal sample hold capacitor for about 16 instruction cycles. This voltage is held until A/D conversion is complete. 3. The comparator compares the voltage added to the sample hold capacitor with the reference voltage for A/D conversion in order from the most significant bit (MSB) to the least significant bit (LSB), and each comparison result is transferred on at a time to the ADDH and ADDL registers. 4. When result transfer ends, the conversion flag bit is cleared (ADMV bit of ADC1 = 0) and the interrupt request flag bit is set (ADI bit of ADC1 = 1). 356 15.7 Notes on Using the A/D Converter 15.7 Notes on Using the A/D Converter This section contains notes on using the A/D converter. I Notes on Using the A/D Converter Input impedance of the analog input pins The A/D converter contains the sample hold circuit shown in Figure 15.7-1 "Equivalent Circuit for Analog Input" and adds the voltage of the analog input pin to the sample hold capacitor in about 15 instruction cycles after A/D conversion starts. Therefore, if the output impedance of the external circuit for analog input is high, the analog input voltage may not be stabilized within the analog input sampling period. To avoid this problem, keep the output impedance of the external circuit low enough to stabilize the voltage (less than 10 k). If the output impedance of the external circuit cannot be kept low, it is recommended that an external capacitor of about 0.1 F be added to the analog input pin. Figure 15.7-1 Equivalent Circuit for Analog Input MB89530/530H/530A series Sample & hold circuit R C Comparator controller Analog channel selector Close for 16 instruction cycles after activating A/D conversion Notes on setting with a program * In A/D conversion function operations, the ADDH and ADDL registers hold the previous values until A/D conversion is activated. As soon as A/D conversion is activated, the contents of the ADDH and ADDL registers become undefined. During operation of the A/D conversion function, do not reselect an analog input channel (ADC1: ANS2 to ANS0). In particular, while continuous activation is in operation, disable continuous activation (ADC2:EXT = 0) and wait for the flag bit (ADC1:ADMV) to change to 0 during conversion. The A/D converter is stopped via a reset and activation of the stop mode and watch mode. If the interrupt request flag bit (ADC1: ADI) is set to 1 and the interrupt request is enabled (ADC2: ADIE = 1), it is not possible to return from interrupt processing. Be sure to clear the ADI bit. For continuous activation by external clocks, input clocks according to the conversion/ comparison time and result read time. * * * * 357 CHAPTER 15 A/D CONVERTER Notes on interrupt requests If A/D conversion is reactivated (ADC1: AD = 1) and terminated at the same time, the interrupt request flag bit (ADC1: ADI) is not set. About errors As |AVR-AVss| decreases, errors become relatively larger. Order of applying A/D converter power and analog input Power on the A/D converter (AVcc, AVss) and apply an analog input (AN0 to AN7) at the same time as, or after turning on the digital power supply (Vcc). To turn off the power, turn off the digital power supply (Vcc) concurrently with or after turning off the power supply of the A/D converter (AVcc, AVss) and the analog input (AN0 to AN7). When the A/D converter is turned on or off, prevent an analog input from exceeding the voltage of the digital power supply. Conversion time The conversion speed of the A/D conversion function is affected by the clock mode, main clock oscillation frequency, or speed switching of main clock (gear function). Input clock for continuous activation Although the timebase timer output is not affected by the gear function, this output cannot be used because the oscillation of the main clock stops in subclock mode. In addition, when the timebase timer is cleared, the clock period (one cycle) is affected. 358 15.8 Program Example of the A/D Converter 15.8 Program Example of the A/D Converter This section contains a sample program for the 10-bit A/D converter. I Program Example of the A/D Conversion Function Processing specification The analog voltage input to the AN0 pin is digitized by activating of the software. An interrupt is not used, and the completion of conversion is detected by the loop in the program. Coding example DDR5 ADC1 ADC2 ADDH ADDL AN0 ADI ADMV AD EQU EQU EQU EQU EQU EQU EQU EQU EQU 0012H 0034H 0035H 0037H 0036H DDR5:0 ADC1:3 ADC1:2 ADC1:0 ;Address of the Port 5 direction register ;Address ;Address ;Address ;Address of of of of the the the the A/D A/D A/D A/D control register 1 control register 2 data register H data register L ;Definition of the AN0 analog input pin ;Definition of the interrupt request flag bit ;Definition of the conversion flag bit ;Definition of the A/D conversion activation bit (software activation) EXT EQU ADC2:1 ;Definition for the continuous activation enable bit ;----------Main program---------------------------------------------------------CSEG ; [CODE SEGMENT] : CLRI ;Interrupt disable SETB AN0 ;Specify the P00/AN0 pin as an analog input pin CLRB EXT ;Continuous activation disabled AD_WAIT BBS ADMV,AD_WAIT ;A/D converter stop check loop MOV ADC1, #00000000B ;Select analog input channel 0 (AN0), clearing the interrupt request flag, and set that software activating is not used MOV ADC2, #00000001B ;Disable interrupt request output, and select the A/D conversion function. Select activation by software. SETI ;Interrupt enable SETB AD ;Activate the software AD_CONV BBS ADMV, AD_CONV ;A/D conversion completion wait loop [Approx. 24s (at 10 MHz)] CLRB ADI ;clearing the interrupt request flag MOVW A,ADDL ;Read the A/D conversion data (lower 8 bits) MOV A,ADDH ;Read the A/D conversion data (upper 2 bits) : ENDS ;-------------------------------------------------------------------------------END 359 CHAPTER 15 A/D CONVERTER 360 CHAPTER 16 UART/SIO This chapter describes the functions and operations of the UART/SIO. 16.1 "Overview of the UART/SIO" 16.2 "Configuration of the UART/SIO" 16.3 "Pins of the UART/SIO" 16.4 "Registers of the UART/SIO" 16.5 "UART/SIO Interrupt" 16.6 "Operation of the UART/SIO" 16.7 "Operation of the Operation Mode 0" 16.8 "Operation of the Operation Mode 1" 361 CHAPTER 16 UART/SIO 16.1 Overview of the UART/SIO The UART/SIO is a general-purpose serial data communication interface. Variablelength serial data can be transferred in clock synchronous or asynchronous mode. The NRZ transfer format is adopted and the transfer rate can be set with the dedicated baud rate generator, the external clock, or the internal timer. I Functions of UART/SIO The UART/SIO functions to transmit/receive serial data (serial I/O) to/from other CPUs and peripheral devices. * * * * Its full-duplex double buffer allows bidirectional transmission in full-duplex mode. A synchronous transfer mode or asynchronous transfer mode can be selected. With the built-in baud rate generator, 14 types of baud rates can be selected. In addition, free baud rates can be set using the externally input clock. The data length is variable. 7-bits to 8-bits can be set when a parity bit is not attached, and 8-bits to 9-bits can be set when a parity bit is attached (See Table 16.1-1 "Operation Mode of UART/SIO"). The NRZ (Non Return to Zero) method is adopted as the data transfer format. * Table 16.1-1 Operation Mode of UART/SIO Operation mode 0 8 1 8 9 Synchronous -Data length No parity 7 With parity 8 Asynchronous 1 bit or 2 bits Synchronous mode Stop bit length 362 16.2 Configuration of the UART/SIO 16.2 Configuration of the UART/SIO The UART/SIO consists of the following six blocks. * Serial mode control register 1 (SMC21) * Serial mode control register 2 (SMC22) * Serial rate control register (SRC2) * Serial status/data register (SSD2) * Serial input data register (SIDR2) * Serial output data register (SODR2) I Block Diagram of UART/SIO Figure 16.2-1 UART/SIO Block Diagram Internal data bus Registers Port generator reload register (SRC2) SMC21 MD PEN TDP SBL CL CLK2 CLK1 CLK0 TIE CLK2 to CLK0 SMC22 RERC RXE TXE BRGE TXOE SCKE RIE SSD2 SODR2 PER OVE FER RDRF TDRE Reload 8-bit counter Selector 0.8 s 3.2 s 0.4 s BRGE 12.8 s (During 10 MHz) P31/SCK1(UCK1)/LMC0 Divide by 8 SIDR2 MD = 1 MD = 0 MD bit Start bit detection Reception counter Parity generator Reception state evaluating circuit PER OVF FER RDRF RIE TDRE TIE Received data register IRQA Pin P33/SI1 (UI1) CL SBL MD Shifter SCKE P31/SCK1(UCK1)/LMCO TXOE Transmission start circuit Transmission counter Shifter Parity generator P32/SO1(UO1) TXE TDRE Transmission data register TDP,PEN 363 CHAPTER 16 UART/SIO Serial mode control register 1 (SMC21) A register to control the operation mode of the UART/SIO. This bit is used to select a serial clock and to set a character bit length, stop bit length, parity polarity, parity presence/absence, and clock synchronization/asynchronization. Serial mode control register 2 (SMC22) A register to control the operation mode of the UART/SIO. This register sets the permission/ prohibition of serial clock output, permission/prohibition of serial data output, switching between the serial port and the general-purpose port, and permission/prohibition of interrupts. Serial status/data register (SSD2) A register that indicates the state of transmission/reception of the UART/SIO and errors. Serial input data register (SIDR2) A register that holds received data. Serial input is converted and stored in this register. Serial output data register (SODR2) A register that sets transmission data. The data written to this register is converted into serial data and output. When the data length is set to 7-bits, bit 7 is ignored. Port generator reload register (SRC2) A register that controls the UART/SIO data transfer speed (baud rate). 364 16.3 Pins of the UART/SIO 16.3 Pins of the UART/SIO This section shows the pins related to the UART/SIO and shows a block diagram of the pins. I Pins Related to the UART/SIO The pins related to the UART/SIO are the clock I/O pin (P31/SCK1(UCK1)/LMC0), serial data output pin (P32/SO1(UO1)), and serial data input pin (P33/SI1(UI1)). P31/SCK1(UCK1)/LMC0 This pin functions as a general-purpose I/O port (P31) or UART/SIO clock I/O pin (hysteresis input). When clock output is enabled (SCKE bit of SMC22 = 1), this pin functions as a UART/SIO clock output pin (SCK1(UCK1)) regardless of the value of the corresponding port data direction register. In this case, do not select an external clock (other than CLK2, CLK1, and CLK0 bits of SMC21 = 100B). To use this pin as a UART/SIO clock input pin, disable clock output (SCKE bit of SMC22 = 0) and then set this bit as an input port with the corresponding port data direction register (bit 1 of DDR3 = 0). In this case, select an external clock (CLK2, CLK1, and CLK0 bits of SMC21 = 100B). P32/SO1(UO1) This pin functions as a general-purpose I/O port (P32) or a UART/SIO serial data output pin (S01/U01). When serial data output is enabled (TXOE bit of SMC22 = 1), this pin functions as the UART/SIO serial data output pin (S01/U01) without reference to the value of the corresponding port data direction register. P33/SI1(UI1) This pin functions as a general-purpose I/O port (P33) or a UART/SIO serial data input pin (hysteresis input) (SI1/UI1). To use this pin as the UART/SIO serial data input pin, set it as an input port (bit 3 of DDR3 = 0) with the corresponding port data direction register. 365 CHAPTER 16 UART/SIO I Block Diagram of Pins Related to UART/SIO Figure 16.3-1 Block Diagram of Pins Related to UART/SIO P33/SI1(UI1) and P31/SCK1(UCK1)/LMC0 only To external interrupt circuit Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) Pull-up resistor About 50 k PDR read Peripheral resource Port 3 pull-up output(*1) resistor control Peripheral resource register output enabled Pch PDR read (at bit manipulation instruction) Output latch PDR write Pch Pin DDR (Port data direction register) Nch P31/SCK1(UCK1)/LMC0 P32/SO1 (UO1) P33/SI1 (UI1) DDR write Stop/watch mode (SPL = 1) DDR read SPL: Pin state setting pin in the standby control register (STBC) *1 Two peripheral resources outputs are connected to P31/SCK1(UCK1)/LMC0. One peripheral resource output is connected to P32/SO1(UO1). Reference: If "pull-up resistor available" is selected in the port 3 pull-up resistor control register, the pins are set to the "H" level (pull-up state), not the Hi-z level, in stop/watch mode (SPL bit of STBC = 1). However, the pull-up is disabled during a reset and the pins are set to the Hi-z level. 366 16.4 Registers of the UART/SIO 16.4 Registers of the UART/SIO This section shows the registers related to the UART/SIO. I Registers Related to UART/SIO Figure 16.4-1 Registers Related to UART/SIO SMC21 (Serial mode control register 1) Address 002FH bit7 MD R/W bit6 PEN R/W bit5 TDP R/W bit4 SBL R/W bit3 CL R/W bit2 CLK2 R/W bit1 CLK1 R/W bit0 CLK0 R/W Initial value 00000000B SMC22 (Serial mode control register 2) Address 0030H bit7 RERC W bit6 RXE R/W bit5 TXE R/W bit4 bit3 bit2 bit1 RIE R/W bit0 TIE R/W Initial value 00000000B BRGE TXOE SCKE W R/W R/W SSD2 (Serial status/data register) Address 0 0 31 H bit7 PER R bit6 OVE R bit5 FER R bit4 bit3 bit2 bit1 bit0 Initial value 00001---B RDRF TDRE R R SIDR2 (Serial input data register) Address 0032H R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB SODR2 (Serial output data register) Address 0032H W W W W W W W W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB SRC2 (Baud rate generator reload register) Address 0033H R/W R/W : Read/write enabled R : Read only W : Write only : Not used X : Undefined R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB 367 CHAPTER 16 UART/SIO 16.4.1 Serial Mode Control Register 1 (SMC21) The serial mode control register 1 (SMC21) controls the operation mode of the UART/ SIO. This register sets the presence/absence of parity, stop bit length, operation mode (data length), synchronous/asynchronous mode, and serial clock. I Serial Mode Control Register 1 (SMC21) Figure 16.4-2 Serial Mode Control Register 1 (SMC1) Address 002FH bit7 MD R/W bit6 PEN R/W bit5 TDP R/W bit4 SBL R/W bit3 CL R/W bit2 CLK2 R/W bit1 CLK1 R/W bit0 CLK0 R/W Initial value 00000000B Clock selection bit CLK2 CLK1 CLK0 0 0 0 2-instruction cycle (0.64 s)(*1) 0 0 0 1 CL 0 1 SBL 0 1 0 1 1 0 1 0 1 0 8-instruction cycle (2.5 s)(*1) 32-instruction cycle (10.24 s)(*1) Dedicated baud rate generator External clock Character bit length control bit 7-bit length 8-bit length Stop bit length control bit 1-bit length 2-bit length Parity polarity bit TDP 0 Even parity 1 Odd parity Parity control bit PEN 0 No parity 1 With parity (Even or odd parity is selected based on the TDP bit.) MD 0 1 Mode control bit Clock asynchronous mode (UART) Clock synchronous mode (SIO) R/W : Read/write enabled : Unused X : Undefined : Initial value *1 This cycle is calculated assuming that FCH is 12.5 MHz. 368 16.4 Registers of the UART/SIO Table 16.4-1 Functions of Each Bit in Serial Mode Control Register 1 (SMC21) Bit name * Bit 7 MD: Mode control bit PEN: Parity control bit TDP: Parity polarity bit * * Function This bit specifies the operation mode of the UART/SIO. In asynchronous mode, the UART/SIO operates with the serial clock divided by 8. In clock synchronous mode, the UART/SIO operates with the selected serial clock. This bit specifies whether there is parity in clock asynchronous mode. This bit specifies the parity data attached at the time of serial transmission in clock asynchronous mode. At the time of serial reception, this bit checks the parity data. This bit specifies the stop bit length in clock asynchronous mode. At the time of serial transmission, this bit attaches a stop bit of the specified bit length. At the time of serial reception, this bit evaluates the stop bit with one bit length irrespective of the set value. This bit specifies the character bit length in clock asynchronous mode. In clock synchronous mode, set this bit to "1". These bits select a serial clock. Bit 6 Bit 5 * Bit 4 SBL: Stop bit length control bit Bit 3 Bit 2 Bit 1 Bit 0 CL: Character bit length control bit CLK2 CLK1 CLK0: Clock selection bits * * * 369 CHAPTER 16 UART/SIO 16.4.2 Serial Mode Control Register 2 (SMC22) The serial mode control register 2 (SMC22) controls the operation mode of the UART/ SIO. This register also enables or disables serial clock output, serial data output, interrupts during data transfer, and the baud rate generator. I Serial Mode Control Register 2 (SMC22) Figure 16.4-3 Serial Mode Control Register 2 (SMC22) Address 0030H bit7 RERC W bit6 RXE R/W bit5 TXE R/W bit4 bit3 bit2 bit1 RIE R/W bit0 TIE R/W Initial value 00000000B BRGE TXOE SCKE W R/W R/W TIE 0 1 RIE 0 1 Transmission interrupt enable bit Disables transmission interrupts Enables transmission interrupts Reception interrupt enable bit Disables reception interrupts Enables reception interrupts Serial clock output bit SCKE 0 Clock input (available as a port) 1 Permits clock output Serial data output bit TXOE 0 Serial data input (I/O setting enabled) 1 Permits serial data output Baud rate generator start bit BRGE 0 Stops baud rate generator 1 Starts baud rate generator TXE 0 1 RXE 0 1 Transmission operation enable bit Prohibits transmitting operation Permits transmitting operation Reception operation enable bit Prohibits receiving operation Permitsreceiving operation Received error flag clear bit RERC 0 Clears each error flag 1 No change and no effect on others R/W : Read/write enabled W : Write only : Initial value 370 16.4 Registers of the UART/SIO Table 16.4-2 Functions of Each Bit in Serial Mode Control Register 2 (SMC2) Bit name * Bit 7 RERC: Received error flag clear bit * RXE: Receiving operation enable bit TXE: Transmitting operation enable bit BRGE: Baud rate generator start bit TXOE: Serial data output bit SCKE: Serial clock output bit * * Function When "0" is written to this bit, each error flag (PER/OVR/ FER) in the SSD2 register is cleared. In read cycle, the value is always "1". Writing "1" has no effect on operation. This bit permits the reception of serial data. When "0" is written to this bit during a receiving operation, the operation stops after data reception is completed and the receiving operation is prohibited. This bit permits the transmission of serial data. When "0" is written to this bit during a transmitting operation, the operation stops after data transmission is completed and the transmitting operation is prohibited. This bit starts the baud rate generator. This bit controls the permission/prohibition of serial data output. This bit controls the I/O of the serial clock in clock synchronous mode. To input an external clock to the P31/SCK1(UCK1)/LMC0 pin, set the port 3 data direction register to input (bit 1 of DDR3 = 0). This bit enables reception interrupts. If reception interrupts are enabled when the RDRF bit is "1" or when each error flag is "1", a reception interrupt occurs immediately. This bit enables transmission interrupts. If transmission interrupts are enabled when the TDRE bit is "1", a transmission interrupt occurs immediately. Bit 6 * Bit 5 Bit 4 Bit 3 * * * Bit 2 Bit 1 RIE: Reception interrupt enable bit TIE: Transmission interrupt enable bit * Bit 0 371 CHAPTER 16 UART/SIO 16.4.3 Serial Status/Data Register (SSD2) The serial status/data register (SSD2) indicate the state of transmission/reception of the UART/SIO and errors. I Serial Status/Data Register (SSD2) Figure 16.4-4 Serial Status/Data Register (SSD2) Address 0031H bit7 PER R bit6 OVE R bit5 FER R bit4 bit3 bit2 bit1 bit0 Initial value 00001---B RDRF TDRE R R TDRE 0 1 RDRF 0 1 FER 0 1 OVE 0 1 PER 0 1 Transmission data register empty Transmission data present Transmission data absent Received data register full Received data absent Received data present Framing error flag Framing error absent Framing error present Overrun error flag Overrun error absent Overrun error present Parity error flag Parity error absent Parity error present R : Read only : Unused : Initial value 372 16.4 Registers of the UART/SIO Table 16.4-3 Functions of Each Bit in Serial Status/Data Register (SSD2) Bit name * Bit 7 PER: Parity error flag Function This bit is set if a parity error occurs during reception and is cleared when "0" is written to the RERC bit in the SMC22 register. When this flag is set, the data in SIDR2 becomes invalid. If the PER bit is set when the RIE bit is set to "1", an interrupt occurs. This bit is set if an overrun error occurs during reception and is cleared when "0" is written to the RERC bit in the SMC22 register. When this flag is set, the data in SIDR2 becomes invalid. If the OVE bit is set when the RIE bit is set to "1", an interrupt occurs. This bit is set if an framing error occurs during reception and is cleared when "0" is written to the RERC bit in the SMC22 register. When this flag is set, the data in SIDR2 becomes invalid. If the FER bit is set when the RIE bit is set to "1", an interrupt occurs. This bit is a flag indicating the state of the received data register (SIDR2). This bit is set when the received data is loaded to the SIDR register and is cleared when the SIDR2 register is read. If the RDRF bit is set when the RIE bit is set to "1", an interrupt occurs. This bit is a flag indicating the state of the serial transmission data register (SODR2). This bit is cleared when the transmission data is written to the SODR register and is set when the data is loaded to the shifter for transmission and transmission of the data starts. If the TDRE bit is set when the TIE bit is set to "1", an interrupt occurs. The read value is undefined. Writing has no effect on operation. * Bit 6 OVE: Overrun error flag * Bit 5 FER: Framing error flag * Bit 4 RDRF: Received data register full * TDRE: Transmission data register empty Bit 3 Bit2 Bit1 Bit0 Unused bits * * 373 CHAPTER 16 UART/SIO 16.4.4 Serial Input Data Register (SIDR2) The serial input data register (SIDR2) is a register for inputting (receiving) serial data. I Serial Input Data Register (SIDR2) Figure 16.4-5 "Serial Input Data Register (SIDR2)" shows the bit configuration of the serial input data register. Figure 16.4-5 Serial Input Data Register (SIDR2) Address 0032H R R : Read only X : Undefined R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB The SIDR is a register for storing the received data. The serial data signal sent to the serial input pin (SI1(UI1) pin) is converted in the shift register and stored in this register. Operation in mode 0 and mode 1 When the received data is set to this register successfully, the received data flag bit (SSD2: RDRF) is set to "1". If the reception interrupt request is enabled, an interrupt occurs. When the received data is stored in this register in an interrupt or when checking the RDRF bit with the program, the RDRF flag is cleared by reading the description in this register. 374 16.4 Registers of the UART/SIO 16.4.5 Serial Output Data Register (SODR2) The serial output data register (SODR2) is a register for outputting (transmitting) serial data. I Serial Output Data Register (SODR2) Figure 16.4-6 "Serial Output Data Register (SODR2)" shows the bit configuration of the serial output data register. Figure 16.4-6 Serial Output Data Register (SODR2) Address 0032H W R : Write only X : Undefined W W W W W W W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB If the SSD2 register is read and the data to be transmitted is written to this register when transmission is permitted, transmission data is transferred to the sift register for transmission and converted to serial data. The converted data is then transmitted from the serial data output pin (SO1(UO1) pin). When the transmission data is written to the SODR2 register, the transmission data flag bit is set to "0". After the transmission data is transferred to the shift register for transmission, the transmission data flag bit is set to "1" so that the next transmission data can be written in the register. If the interrupt request is enabled at this time, an interrupt occurs. The next transmission data can be written by generating an interrupt or when the transmission data flag bit is set to "1". 375 CHAPTER 16 UART/SIO 16.4.6 Baud Rate Generator Reload Register (SRC2) The baud rate generator reload register (SRC2) controls the UART/SIO data transmission speed (baud rate). I Baud Rate Generator Reload Register (SRC2) Figure 16.4-7 "Baud Rate Generator Reload Register (SRC2)" shows the bit configuration of the baud rate generator reload register (SRC2). Figure 16.4-7 Baud Rate Generator Reload Register (SRC2) Address 0033H R/W R/W : Read/write enabled X : Undefined R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB When CLK2 to CLK0 (clock selection bits) are "011B", the dedicated baud rate generator is selected as a serial clock. This register can be used to set an optional baud rate. Write data to this register when UART operation is stopped. 376 16.5 UART/SIO Interrupt 16.5 UART/SIO Interrupt The UART/SIO has three flags related to interrupts, the error flag bits (PER, OVE, FER), the received data flag bit (RDRF), and the transmission data flag bit (TDRE), as well as the following two interrupt sources. * When the received data is transferred from the shift register for reception to the serial input data register (SIDR2) (reception interrupt) * When the transmission data is transferred from the serial output data register (SODR2) to the shift register for transmission. (transmission interrupt) I Transmission Interrupt Output data is written to the SODR2 register and then transferred to the shift register for internal transmission. When the register is ready to accept the next data, the TDRE bit is set to "1". If the transmission interrupt is enabled (SMC22: TIE = 1), an interrupt request to the CPU (IRQA) occurs. I Reception Interrupt After data is input up to the stop bit successfully, the RDRF bit is set to "1". If an overrun, parity, or error framing error has occurred, the bit of the corresponding error flag is set to "1". These bits are set when the stop bit is detected. If the reception interrupt is enabled (SMC22: RIE = 1), an interrupt request to the CPU (IRQA) occurs. I Register and Vector Table Address Related to Interrupt of UART/SIO Table 16.5-1 Register and Vector Table Address Related to Interrupt of UART/SIO Interrupt name IRQA Interrupt level setting register Register ILR3 (007DH) Bit to be set LA1 (bit 5) LA0 (bit 4) Vector table address Upper FFE6H Lower FFE7H For interrupt operation, see Section 3.4.2 "Interrupt Processing". 377 CHAPTER 16 UART/SIO 16.6 Operation of the UART/SIO This section describes the operation of the UART/SIO. The UART/SIO has ordinary serial communication functions (operation modes 0 and 1). I Operation of UART/SIO Operation modes The UART/SIO has two operation modes: clock synchronous mode (SIO) and clock asynchronous mode (UART). (See Table 16.1-1 "Operation Mode of UART/SIO".) 378 16.7 Operation of the Operation Mode 0 16.7 Operation of the Operation Mode 0 Operation mode 0 operates in clock asynchronous mode. I Explanation of Operation Mode 0 of UART/SIO The serial clock is selected, with bits CLK21 to CLK0 in the SMC1 register, from among three types of internal clocks, an external clock, and a baud rate generator output. When the external clock is selected, the clock must be entered. In CLK asynchronous mode, the shift clock selected with bits CLK2 to CLK0 is divided by 8 and data can be transferred in the range between -2% and +2% of the selected baud rate. The baud rate calculation expressions for the internal and external clocks and the baud rate generator are shown in the following. Figure 16.7-1 Baud Rate Calculation Expression when Dedicated Baud Rate Generator is Used Baud rate value = 8x2x 1 64/FCH 16/FCH 8/FCH 4/FCH x SRC2 register value (SRC2) [bps] Clock gear selection FCH: Frequency used Figure 16.7-2 Expression for Baud Rate Calculation with Internal and External Clocks 1 Baud rate value = 8x Clock selected according to CLK2 to CLK0 [bps] 379 CHAPTER 16 UART/SIO Table 16.7-1 Example of the Asynchronous Transfer Rate with the Baud Rate Generator Operating frequency Instruction cycle 10 MHz 4/FCH 0.4 s 78125(n=2) 39062(n=4) 19531(n=8) Baud rate 9765(n=16) Values in parentheses indicate SRC2 register set values 4882(n=32) 2403(n=65) 1201(n=130) --I Transfer Data Format The UART/SIO can only use the NRZ (Non Return to Zero) format data. Figure 16.7-3 "Transfer Data Format" shows the data format. In the following example, the stop bit length is two bits. As shown in Figure 16.7-3 "Transfer Data Format", data transfer always starts with the start bit ("L" level), followed by the data bit length specified as the LSB first, and ends with the stop bit ("H" level). In an idle state, it is at the "H" level. Figure 16.7-3 Transfer Data Format 7-bit length No parity Stop bits: 2 bits 7-bit length With parity Stop bits: 2 bits 8-bit length No parity Stop bits: 2 bits 8-bit length With parity Stop bits: 2 bits 8 MHz 4/FCH 0.5 s 62500(n=2) 31250(n=4) 17857(n=7) 9615(n=13) 4807(n=26) 2403(n=52) 1201(n=104) 600(n=208) -- 7.3728 MHz 4/FCH 0.54 s -38400(n=3) 19200(n=6) 9600(n=12) 4800(n=24) 2400(n=48) 1200(n=96) 600(n=192) -- 4.9152 MHz 4/FCH 0.81 s 76800(n=1) 38400(n=2) 19200(n=4) 9600(n=8) 4800(n=16) 2400(n=32) 1200(n=64) 600(n=128) 300(n=0) St D0 D1 D2 D3 D4 D5 D6 Sp Sp St D0 D1 D2 D3 D4 D5 D6 P Sp Sp St D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp St D0 D1 D2 D3 D4 D5 D6 D7 P Sp Sp : Start bit : Data bit : Parity bit : Stop bit St D0 to D7 P Sp 380 16.7 Operation of the Operation Mode 0 I Receiving Operation in CLK Asynchronous Mode Select the baud rate clock with bits CLK2 to CLK0 in the SMC21 register. For the baud rate clock, see the section about clock selection. In a receiving operation, reception is permitted when the RXE bit in the SMC1 register is "1" and the receiving operation starts at the first falling edge of the input data (detection of the start bit). When the receiving operation is completed, the RDRF bit in the SSD register is set to "1" and the received data is loaded to the SIDR register. If the RDRF bit is set to "1" when the RIE bit is "1", a reception interrupt to the CPU is generated. If any of the three errors (PER/OVE/FER) is detected when reception is completed, the RDRF bit is not set to "1" and the received data is not loaded to the SIDR register. Therefore, the value in the SIDR register is the previously received data. Unless the RXE bit is set to "0", the receiving operation is continued whenever a start bit is detected even if an error flag is set. If "0" is written to the RXE bit of the SMC22 register during a receiving operation, the receiving operation is prohibited after data reception is completed. Figure 16.7-4 Receiving Operation of CLK Asynchronous Mode RXE UI1 St D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp St D0 D1 D2 Load to SIDR2 RDRF 381 CHAPTER 16 UART/SIO I Reception Error in CLK Asynchronous Mode In CLK asynchronous mode, three types of errors are detected. When a parity error, overrun error, or framing error is detected, the PER, OVE, or FER bit in the SSD2 register is set to "1", respectively. The detection of these errors are performed at the end of reception as shown in the following. When any of these errors is detected, RDRF is not set and the received data is not loaded to the SIDR2 register. Therefore, the value in the SIDR2 register is the previously received data. By writing "0" to the RERC bit in the SCM22 register, all of the three error flags are cleared. Figure 16.7-5 Reception Error Setting Timing UI1 D5 D6 D7/P Sp Sp PER OVE FER Error interrupt I Detecting the Start Bit At Receiving Operation When the "L" level remains for four clocks with the selected serial clock (generator output, etc.) after the first falling edge of the input data, the UART/SIO regards it as a start bit. After the start bit is detected, data is sampled at the rising edge of the fifth clock of the serial clock after the start bit is detected. Figure 16.7-6 Detecting a Start Bit Serial clock 1 UI1 4 clocks Data is sampled. St : Start bit D0 to D7 : Data bit 2 3 4 5 6 7 8 1 2 3 4 5 D0 6 7 8 A start bit is detected. 382 16.7 Operation of the Operation Mode 0 I Transmitting Operation in CLK Asynchronous Mode If transmission data is written to the SODR2 register when the TXE bit in the SMC22 register is "1", the TDRE bit in the SSD2 register is cleared and a transmitting operation starts. When the data in the SODR2 register is loaded to the shifter and the output of transmission data starts, the TDRE bit in the SSD2 register is set. If data is written to the SODR register when data is being transmitted (when the TDRE bit is set to "1"), the TDRE bit is cleared and data is transmitted continuously following the transmission of the specified bit length data. If "0" is written to the TXE bit in the SMC22 register during a transmitting operation, the transmitting operation is prohibited following the transmission of the specified bit length data when the SODR2 register is vacant (when the TDRE bit is set to "1"). When there is data in the SODR2 register (when the TDRE bit is set to "1"), the transmitting operation is prohibited after the data in the SODR register is transmitted. Figure 16.7-7 Transmission in CLK Asynchronous Mode TXE Write to SODR2 TDRE Interrupt to the CPU UO1 Interrupt to the CPU St D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp St D0 D1 D2 St : Start bit D0 to D7: Data bit Sp : Stop bit 383 CHAPTER 16 UART/SIO 16.8 Operation of the Operation Mode 1 Operation mode 1 operates in clock synchronous mode. I Explanation of UART/SIO Operation Mode In CLK synchronous mode, the clock is selected, with bits CLK2 to CLK0 in the SMC21 register, from among three types of internal clocks, an external clock, and a baud rate generator output. Shift operation is performed with the selected clock as a shift clock. When the external clock is entered, set the SCKE bit to "0". When the internal clock or the output of the baud rate generator is output as a shift clock, set the SCKE bit to "1". The baud rate calculation expressions for the internal and external clocks and the baud rate generator are shown in the following Figure 16.8-1 Baud Rate Calculation Expression when the Dedicated Baud Rate Generator is Used (CLK2, CLK1, CLK0 = 011B) 1 Baud rate value = 2x [bps] SRC2 register value (SRC2) 64/FCH 16/FCH 8/FCH 4/FCH x Clock gear selection FCH: Main clock oscillation frequency Figure 16.8-2 Baud Rate Calculation Expression for the Internal and External Clocks (Other than CLK2, CLK1, CLK0 = 011B) Baud rate value = 1 Selected clock for CLK2 to CLK0 [bps] 384 16.8 Operation of the Operation Mode 1 I 8-bit Receiving Operation Figure 16.8-3 Registers Used at Reception in Operation Mode 1 Serial mode control register 1 (SMC21) bit7 bit6 bit5 bit4 bit3 CL bit2 bit1 bit0 MD PEN TDP SBL CLK2 CLK1 CLK0 1 0 0 0 1 Serial mode control register 2 (SMC22) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TIE RERC RXE TXE BRGE TXOE SCKE RIE x Serial status and data register (SSD2) bit7 bit6 bit5 bit4 0 x bit3 bit2 bit1 bit0 : x: 1: 0: Used bit Unused bit Bit with 1 Bit with 0 PER OVE FER RDRF TDRE x x x Receiving operation is permitted by setting the TXE and RXE bits of serial mode control register 2 (SMC22) to "1" and then started when data is written to the SODR2 register. Reception is performed in synchronization with the rising edge of the shift clock. Upon the completion of 8-bit data reception, shifter data is loaded to the SIDR2 register and the RDRF flag is then set to "1". If the RIE bit is set to "1" at this time, an interrupt request to the CPU is generated. If an overrun error occurs when the receiving operation finishes, data is not loaded into the SIDR2 register. Writing "0" to the RXE bit during a receiving operation stops the receiving operation after the 8bit data has been received. When serial operation is stopped, always keep the serial clock input at the "H" level (without referencing the value of the RXE bit). Figure 16.8-4 8-Bit Data Receiving Operation in CLK Synchronous Mode Write to SODR2 SCK1 SI1 Load to SIDR2 RDRF D0 D1 D2 D3 D4 D5 D6 D7 Interrupt to CPU 385 CHAPTER 16 UART/SIO I Continuous Receiving Operation In CLK synchronous mode, not only 8-bit data reception but also continuous reception can be performed. In continuous reception, the TIE bit of the SMC22 register and the TDRE bit of the SSD2 register are used in addition to the bits used for 8-bit data reception. Reception is enabled by setting the TXE and RXE bits of the serial mode control register 2 (SMC22) to "1" and starts when data is written to the SODR2 register. This is performed in synchronization with the rising edge of the shift clock. When a shift operation is started, the TDRE bit of SSD2 is set to "1". If the TIE bit of SMC22 is set to "1" at this time, a CPU interrupt is generated. Writing data to the SODR2 register before 8-bit shift operation finishes permits the next shift operation and continuous reception even after the reception of 8-bit data. When 8-bit data reception finishes, shifter data is loaded to the SIDR2 register and the RDRF flag of SSD2 is set to "1". If the RIE bit of SMC22 is "1" at this time, a CPU interrupt request is generated. If an overrun error occurs upon the completion of 8-bit data reception, data is not loaded to the SIDR2 register. In this case, the contents of the SIDR2 register are those of the previously received data. Reading the SIDR2 register clears the reception interrupt (RDRF flag of SSD2). Continuous reception stops when "0" is written to the RXE bit of SMC22. If "0" is written to the RXE bit of SMC22 when 8-bit data is being received, continuous reception stops after 8-bit data has been received. Figure 16.8-5 Continuous Receiving Operation in CLK Synchronous Mode SCK1 SI1 Write to SODR2 TDRE Load to SIDR2 RDRF Interrupt to CPU Read of SIDR2 Interrupt to CPU D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 386 16.8 Operation of the Operation Mode 1 I 8-bit Transmitting Operation Figure 16.8-6 Registers Used at Transmission in Operation Mode 1 Serial mode control register 1 (SMC21) bit7 MD bit6 bit5 bit4 bit3 bit2 bit1 bit0 PEN TDP SBL CL CLK2 CLK1 CLK0 1 0 0 0 1 Serial mode control register 2 (SMC22) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TIE RERC RXE TXE BRGE TXOE SCKE RIE x Serial status and data register (SSD2) bit7 bit6 bit5 bit4 1 bit3 bit2 bit1 bit0 : x: 1: 0: Used bit Unused bit Bit with 1 Bit with 0 PER OVE FER RDRF TDRE x x x Transmission is started by setting the TXE and RXE bits of the serial mode control register 2 (SMC22) to "1" and writing data to the SODR2 register. When transmission is started, the data written to the SODR2 register is loaded to the shifter and then shift operation is performed. When data is loaded from the SODR2 register to the shifter, the TDRE flag of SSD2 is set to "1". If the TIE bit of SMC22 is "1" at this time, a CPU interrupt request is generated. Serial data output is permitted by setting the TXOE bit of SMC22 to "1". Serial data is output in synchronization with the falling edge of the shift clock. If "0" is written to the TXE bit of SMC22 when 8-bit data is being transmitted, transmission stops after 8-bit data has been transmitted. After 8-bit data has been transmitted, the RDRF bit of SSD2 is set to "1". If the RIE bit of SMC22 is "1" at this time, a CPU interrupt request is generated. Data transmission starts with bit 0 and ends with bit 7. When serial operation is stopped, keep the serial clock input at the "H" level (without referencing the value of the TXE bit of SMC22). Figure 16.8-7 8-Bit Transmitting Operation in CLK Synchronous Mode Write to SODR2 SCK1 SO1 TDRE RDRF Interrupt to CPU Interrupt to CPU D0 D1 D2 D3 D4 D5 D6 D7 387 CHAPTER 16 UART/SIO I Continuous Transmission at Operation Mode 1 In CLK synchronous mode, not only 8-bit data transmission but also continuous transmission can be performed. Transmission is started by setting the TXE and RXE bits of serial mode control register 2 (SMC22) to "1" and writing data to the SODR2 register. When transmission is started, the data written to the SODR2 register is loaded to the shifter and then shift operation is performed. When data is loaded from the SODR2 register to the shifter, the TDRE flag of SSD2 is set to "1". If the TIE bit of SMC22 is "1" at this time, a CPU interrupt request is generated. Continuous transmission is performed by writing the next transmission data to the SODR2 register during transmission when the TDRE bit is "1" (the SODR2 register is vacant). When data is written to the SODR2 register, the TDRE bit of SSD2 is cleared. After 8-bit data has been transmitted, the data written to the SODR2 register is loaded to the shifter to continue transmission. Transmission stops when "0" is written to the TXE bit of SMC22. If the SODR2 register is vacant (TDRE bit of SSD2 = "1") when "0" is written to the TXE bit during transmission, transmission stops after 8-bit data has been transmitted. If data exists in the SODR2 register (TDRE bit of SSD2 = "0"), transmission stops after data in the SODR2 register has been transmitted. When 8-bit data transmission finishes, the RDRF bit of SSD2 is set to "1". If the RIE bit is "1" at this time, a CPU interrupt request is generated. Figure 16.8-8 Continuous Receiving Operation in CLK Synchronous Mode Write to SODR2 SCK1 SO1 TDRE D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 RDRF Interrupt to CPU Interrupt to CPU 388 CHAPTER 17 HIGH-SPEED UART This chapter describes the functions and operation of the high-speed UART. 17.1 "Overview of the High-Speed UART" 17.2 "Configuration of the High-Speed UART" 17.3 "Pins of the High-Speed UART" 17.4 "Registers of the High-Speed UART" 17.5 "High-Speed UART Interrupts" 17.6 "Operation of the High-Speed UART" 17.7 "Operation of Operation Modes 0, 1, 2, and 4" 17.8 "Operation of Operation Mode 3" 17.9 "Program Example of the UART" 389 CHAPTER 17 HIGH-SPEED UART 17.1 Overview of the High-Speed UART The high-speed UART is a general-purpose serial data communication interface used to transfer variable-length data in clock synchronous or clock asynchronous mode. The transfer format is the non-return-to-zero (NRZ) transfer format. The transfer rate can be set with a dedicated baud rate generator, external clock, or internal timer (2channel 8-bit PWM timer 1). Either a single-clock or a dual-clock system can be used. I Function of the High Speed UART The high-speed UART transmits serial data to and receives serial data from other CPUs and peripheral devices (input and output of serial data). * * * Its full-duplex double buffer allows bidirectional transmission in full-duplex mode. Synchronous transfer mode or asynchronous transfer mode can be selected. With the built-in baud rate generator, one of 14 baud rates can be selected. Moreover, an arbitrary baud rate can be specified using the externally input clock and 2-channel 8-bit PWM timer 1 output. Variable-length data is supported. Without a parity bit, a data length of 5-bits to 9-bits can be selected. With a parity bit, 4-bits to 8-bits can be specified (see Table 17.1-1 "Operation Modes of the High-Speed UART". The non-return-to-zero (NRZ) transfer format is used for data transfer. Use of either the single-clock system or dual-clock system can be specified by software. * * * Table 17.1-2 "Transfer Cycles and Transfer Rates When Baud Rate Generator Used", Table 17.1-3 "Transfer Cycles and Transfer Rates When External Clock Used", and Table 17.1-4 "Transfer Cycles and Transfer Rates When 2-channel 8-Bit PWM Timer 1 Used" list the transfer rates provided by the dedicated baud rate generator, external clock, and 2-channel 8-bit PWM timer 1, respectively. Table 17.1-1 Operation Modes of the High-Speed UART Operation mode Data length Synchronous mode No parity 0 1 2 3 4 5 7 8 8+1 9 With parity 4 6 7 8 Asynchronous/synchronous Asynchronous/synchronous Asynchronous/synchronous Asynchronous/synchronous Asynchronous/synchronous 1-bit or 2-bits (*1) 1-bit or 2-bits (*1) 1-bit or 2-bits (*1) 1-bit or 2-bits (*1) 1-bit or 2-bits (*1) Stop bit count *1: However, only one stop bit can be identified during reception. The second stop bit is ignored if transmitted. 390 17.1 Overview of the High-Speed UART I Transfer Clock Selection Figure 17.1-1 Baud Rate Generator and Serial Clock Generator Divider of dedicated baud rate generator PDCK PDS2,1,0 RC2,1,0 SCS1,0 Clock divider SMDE CR 1/3 CPU operation clock Tinst/2 (*1) Subclock 1/4 1/6 1/13 1/2 1/65 1/2n 1/8 1/16 1/64 Serial clock PWM1 output SCK *1 Tinst: Instruction cycle Table 17.1-2 Transfer Cycles and Transfer Rates When Baud Rate Generator Used In asynchronous transfer mode 9.216MHz 1/3 1/8 RC2 RC1 RC0 Baud rate selection division ratio 1 2 4 8 16 32 64 128 Transfer rate (*1) (s/baud) 5.2/192K 10.4/96K 20.8/48K 41.7/24K 83.3/12K 166.7/6K 333.3/3K 666.7/1.5K 9.984MHz 1/65 1/8 Transfer rate (*1) (s/baud) 104/9600 208/4800 416/2400 832/1200 1664/600 3328/300 In synchronous transfer mode 10MHz 1/3 1/1 Transfer rate (*1) (s/baud) 0.6/1.67M 1.2/833.3K 2.4/416.7K 4.8/208.3K 9.6/104.2K 19.2/52.08K 38.4/26.04K 76.8/13.02K Clock frequency PDS division SCS, CR division 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 *1: When the maximum main clock rate is selected 391 CHAPTER 17 HIGH-SPEED UART Figure 17.1-2 Example for Baud Rate Calculation Clock gear selection 1 Baud rate 64/FCH 16/FCH 8/FCH 4/FCH Clock division ratio Baud rate selection Baud rate selection = x 1/2 x (SCS1, SCS0, CR) x (PDS2, PDS1, PDS0) x (RC2, RC1, RC0) FCH: Main clock oscillation frequency Reference: A dedicated baud rate is set by the clock gear register/clock division ratio register (SCS1, SCS0) and the baud rate selection register. See Table 17.1-1 "Operation Modes of the High-Speed UART" for examples of baud rate calculation. 1/208333 baud = 0.4 s (4/FCH) x 1/2 x 8 (asynchronous mode) x 3 (RC2 = RC1 = RC0 = 0) (FCH = 10 MHz) Table 17.1-3 Transfer Cycles and Transfer Rates When External Clock Used Asynchronous transfer mode Baud rate division ratio CR=0 CR=1 16 64 Transfer cycle 96/FCH or more 384/FCH or more Transfer rate (*1) (baud) 104.2 k or less 1 26041 or less Synchronous transfer mode Baud rate division ratio Transfer cycle 16/FCH or more Transfer rate (*1) (baud) 625 k or less FCH: Main clock oscillation frequency *1: The minimum external clock cycle when FCH is set to 10 MHz (6/FCH = 0.6 s) Figure 17.1-3 Example of Baud Rate Calculation (When External Clock is Selected) 1 Baud rate 16 for CR = 0 64 for CR = 1 = External clock input x CR (min. : 8/FCH x 2) FCH: Main clock oscillation frequency 392 17.1 Overview of the High-Speed UART Table 17.1-4 Transfer Cycles and Transfer Rates When 2-channel 8-Bit PWM Timer 1 Used PWM timer counter clock cycle 1 tinst Asynchronous transfer mode Clock division ratio CR=0 CR=1 8 tinst CR=0 CR=1 16 tinst CR=0 CR=1 64 tinst CR=0 CR=1 16 64 16 64 16 64 16 64 Transfer rate (baud) 78125 to 610.4 19531.3 to 152.6 9765.6 to 76.3 2441.4 to 19.1 4882.8 to 38.2 1220.7 to 9.5 1220.7 to 9.5 305.2 to 2.4 2 9765.6 to 76.3 2 39062.5 to 305.2 2 78125 to 610.4 Synchronous transfer mode Clock division ratio 2 Transfer rate (baud) 625k to 4.88k Tinst: Instruction cycle (affected by the clock mode) * In main clock mode (SCS = 1), the maximum clock rate (CS1, CS0 = 11B, 1 instruction cycle = 4/Fch) is selected by the system clock control register (SYCC). Figure 17.1-4 Example for Baud Rate Calculation (When PWM Timer 1 is Selected) Clock gear selection 1 = Baud rate 64/FCH 16/FCH 8/FCH 4/FCH x Input clock selection bit (PWM timer) (SC11=SC21/SC10=SC20) 1(SC11=0,SC10=0) 8(SC11=0,SC10=1) 16(SC11=1,SC10=0) 64(SC11=1,SC10=1) x Compare register (COMR1/COMR2) Compare register setting value + 1 x 2 x CR (cycle) 16 for CR = 0 64 for CR = 1 FCH: Main clock oscillation frequency Reference: The baud rate is determined by the input clock specified by the clock division ratio register (SCS1, SCS0). For the input clock, the external clock or PWM timer 1 is selected. See Table 17.1-2 "Transfer Cycles and Transfer Rates When Baud Rate Generator Used" and Table 17.1-3 "Transfer Cycles and Transfer Rates When External Clock Used" for the calculation. When the external clock is selected 1/39k baud = 1.6 s (min.) x 16 (CR = 0) When PWM timer 1 is selected (FCH = 10 MHz) 1/78k baud = 0.4 s (4/FCH) x 1 (SC11 = 0, SC10 = 0) x 1 (COMR1 = 0) x 2 x 16 (CR = 0) (FCH = 10 MHz) 1/19531 baud = 0.4 s (4/FCH) x 1 (SC11 = 0, SC10 = 0) x 1 (COMR1 = 3) x 2 x 16(CR = 0) (FCH = 10 MHz) See CHAPTER 8 "2-CHANNEL 8-Bit PWM TIMERS", for the PWM timer count clock cycle, PWM compare register setting value, and PWM timer output cycle. 393 CHAPTER 17 HIGH-SPEED UART 17.2 Configuration of the High-Speed UART The high-speed UART consists of the following nine blocks: * Serial mode control register 1 (SMC11) * Serial mode control register 2 (SMC12) * Serial rate control register (SRC1) * Serial status/data register (SSD1) * Serial input data register (SIDR1) * Serial output data register (SODR1) * Clock generator * Reception control circuit * Transmission control circuit I Block Diagram of High-Speed UART Figure 17.2-1 Block Diagram of High-Speed UART Control bus P44/INT24/UCK2 Pin T01 Transmission clock Reception control circuit Received byte counter Reception interrupt Transmission control circuit UART interrupt IRQB Transmission interrupt IRQC Transmission byte counter Parity transfer timing Clock generator Dedicated baud rate generator Reception clock P46/INT26/UI2 Pin Start bit detection circuit Parity RP Parity TP P45/INT25/UO2 Pin Shift register Register Shift register Receiving Register of one byte is Internal data bus Serial mode control register 1 (SMC11) MC2/1/0 PEN SBL MOCAD SMDE UCKE UOE Serial rate control register (SRC1) CR SCS1/0 RC2 to 0 Serial status and data register (SSD1) RDRF ORFE TDRE TIE RIE TP RP Serial mode control register 2 (SMC12) PSEN LSEL PDCK PDS2 PDSI PDSO TO1: PWM timer 1 output of the 2-channel 8-bit PWM timer 394 17.2 Configuration of the High-Speed UART Serial mode control register 1 (SMC11) One of the registers that controls the operation mode of the high-speed UART. This register specifies whether parity is used, the stop bit count, the operation mode (data length), and whether synchronous or asynchronous mode is used, and enables serial clock output of the high-speed UART and serial data output. Serial mode control register 2 (SMC12) One of the registers that controls the data transfer rate (baud rate) of the high-speed UART. This register selects the input clock and sets the transfer rate for the baud rate generator. Serial rate control register (SRC1) SRC1 controls the data transfer rate (baud rate) of the high-speed UART. This register selects the input clock and sets the transfer rate for the baud rate generator. Serial status/data register (SSD1) SSD1 indicates the operational state of transmission or reception, errors occurring in the highspeed UART, and whether data transfer with parity bit or with bit 8 used for transmission data has been specified. This register also enables interrupts and can be used to set and check whether transmission is to be performed with a parity bit or with bit 8 used for transmission data. Serial input data register (SIDR1) Register for storing received data. Serial input is converted and stored in this register. For a data length of 9-bits, the leading bit is stored in the SSD1: RD8/RP bit. Serial output data register (SODR1) Register that sets transmission data. Data written to this register is converted to serial data and output. For a data length of 9-bits, the leading bit is stored in the SSD1: TD8/TP bit. Clock generator This circuit generates transmission or reception clock pulses using the dedicated baud rate generator, the external clock, and two-channel 8-bit PWM timer output. Reception control circuit This circuit consists of a received byte counter, start bit detection circuit, and received parity circuit. The received byte counter counts the bits of data received. It generates an interrupt request whenever a data item of the specified length has been received. The start bit detection circuit detects a start bit in the serial input signal. Upon detection of the start bit, this circuit writes data to the SIDR, applying shifts according to the specified transfer rate. The received parity circuit stores a parity bit in received data if transfer with parity is specified. However, if a data length of 9-bits is specified, the circuit stores the leading bit of the received data. 395 CHAPTER 17 HIGH-SPEED UART Transmission control circuit The transmission control circuit consists of a transmission byte counter and transmission parity circuit. The transmission byte counter counts the bits of transmission data. It generates an interrupt request whenever a data item of the specified length has been transferred. The transmission parity circuit generates a parity bit for data to be transferred if transmission with parity is specified. For a data length of 9-bits, the leading bit of the transmission data is stored. Interrupt sources related to the high-speed UART Reception: IRQB If interrupt requests are enabled (SSD1: RIE = 1), a reception interrupt request (IRQB) is generated when a data item of the specified length has been received correctly or when an overrun error or a framing error occurs during reception. Transmission: IRQC If transmission request interrupts are enabled (SSD1: TIE = 1), a transmission interrupt request (IRQC) is generated when data written to the SODR1 register has been transferred to the internal shift register and writing of the next item of data is allowed. 396 17.3 Pins of the High-Speed UART 17.3 Pins of the High-Speed UART This section describes the pins related to the high-speed UART and provides block diagrams of the pins. I Pins Related to the High-Speed UART The pins related to the high-speed UART are the clock I/O pin (P44/INT24/UCK2), serial data output pin (P45/INT25/UO2), and serial data input pin (P46/INT26/UI2). P44/INT24/UCK2: The P44/INT24/UCK2 pin functions as a general-purpose I/O pin (P44), external interrupt pin (INT24), or clock I/O pin (hysteresis input) for the high-speed UART (UCK2). When clock output is enabled (SMC1: UCKE = 1), this pin functions as the clock I/O pin (UCK2) of the high-speed UART regardless of the value of the corresponding port direction register. At this time, do not select the external clock (SRC1: SCS1, SCS0 = other than 00B). When using this pin as the clock input pin of the high-speed UART, disable clock output (SMC1: UCKE = 0) and set used input port as the use of this pin in the corresponding port direction register (DDR4: bit 4 = 0). Also select the external clock (SRC1: SCS1, SCS0 = 00B). P45/INT25/UO2: The P45/INT25/UO2 pin functions as a general-purpose I/O pin (P45), external interrupt pin (INT25), or serial data output pin for the high-speed UART (UO2). When serial data output is enabled (SMC11: UOE = 1), this pin functions as the serial data output pin (UO2) of the high-speed UART regardless of the value of the corresponding port direction register. P46/INT26/UI2: The P46/INT26/UI2 pin functions as a general-purpose I/O pin (P46), external interrupt pin (INT26), or serial data input pin (hysteresis input) for the high-speed UART (UI2). To use this pin as the serial data input pin for the high-speed UART, set the corresponding port data register for the input port (DDR4:bit 6 = 0). 397 CHAPTER 17 HIGH-SPEED UART I Block Diagrams of Pins Related to the High-Speed UART Figure 17.3-1 Block Diagram of Pins Related to the High-Speed UART To external interrupt circuit Stop/watch mode External interrupt input enable P44, P45, and P46 only To resource Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) PDR read From resource output From resource output enable Port 4 pull-up resistor control register Pull-up resistor About 50 k Pch PDR read (for bit manipulation instructions) Output latch PDR write P44 and P45 only Pch Pin DDR (port data direction register) Nch P44/INT24/UCK2 P45/INT25/UO2 P46/INT26/UI2 DDR write Stop/watch mode (SPL = 1) DDR read DDR (port data direction register) SPL: Pin status specification bit of standby control register (STBC) Reference: When "pull-up resistor available" is selected using the port 4 pull-up resistor control register the pins are set to "H" (pulled up) level, not the high impedance state, in stop mode or watch mode (STBC:SPL = 1). During a reset, however, pull-up is disabled and the pins are set to Hi-z. 398 17.4 Registers of the High-Speed UART 17.4 Registers of the High-Speed UART This section describes the registers related to the high-speed UART. I High-Speed UART Registers Figure 17.4-1 High-Speed UART Registers SMC11 (serial mode control register 1) Address 0 0 2 2H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value PEN SBL MC2 MC1 MC0 SMDE UCKE UOE 00000000B R/W R/W R/W R/W R/W R/W R/W R/W SMC12 (serial mode control register 2) Address 0 0 2 6H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value PSEN LSEL PDCK PDS2 PDS1 PDS0 --100001B R/W R/W R/W R/W R/W R/W SRC1 (serial rate control register) Address 0 0 2 3H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value --011000B CR SCS1 SCS0 RC2 RC1 RC0 R/W R/W R/W R/W R/W R/W SSD1 (serial status/data register) Address 0 0 2 4H bit7 bit6 bit5 bit4 bit3 RIE bit2 bit1 bit0 Initial value RDRF ORFE TDRE TIE R R TD8/TPRD8/RP 00100-1XB R/W R/W R/W R/W R SIDR1 (serial input data register) Address bit7 bit6 0 0 2 5H R R bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB R R R R R R SODR1 (serial output data register) Address 0 0 2 5H W R/W : Read/Write enabled R : Read only W : Write only : Unused X : Undefined bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB W W W W W W W 399 CHAPTER 17 HIGH-SPEED UART 17.4.1 Serial Mode Control Register 1 (SMC11) Serial mode control register 1 (SMC11) specifies whether parity is used, defines the stop bit length, sets the operation mode (data length), sets synchronous or asynchronous mode, and enables/disables serial clock output and serial data output of the high-speed UART. I Serial Mode Control Register 1 (SMC11) Figure 17.4-2 Serial Mode Control Register 1 (SMC11) Address Initial value Serial data output enable bit General-purpose port Serial data output pin of high-speed UART Clock output enable bit General-purpose port or clock input pin of high-speed UART Clock output pin of high-speed UART Synchronous mode selection bit Synchronous transfer mode (synchronous) Asynchronous transfer mode (asynchronous) Operation mode selection bit During write Operation mode Without parity With parity Stop bit count selection bit 2 bits 1 bit Parity control bit Without parity With parity (Odd or even parity can be set by TD8/TP in the SSD register.) Can be read and written Initial value 400 17.4 Registers of the High-Speed UART Table 17.4-1 Functions of the Serial Mode Control Register 1 (SMC11) Bits Bit name bit7 PEN: Parity enable bit SBL: Stop bit count selection bit MC2, MC1, MC0: Operation mode selection bits SMDE: Synchronous mode selection bit * Function For serial data I/O, this bit specifies whether a parity bit is added during transmission and whether parity bits are detected during reception. bit6 * This bit specifies the stop bit count of transmission data. Note: During reception, only the first stop bit is detected; subsequent stop bits are ignored. * * * * * * These bits select the operation mode (data length). Six types of data length can be selected in combination with a parity bit. This bit selects synchronous or asynchronous transfer. When this bit is "0", synchronous transfer mode is selected. When this bit is "1", asynchronous transfer mode is selected. bit5 bit4 bit3 bit2 bit1 UCKE: Clock output enable bit This bit controls serial clock I/O. When this bit is "0", the P44/INT24/UCK2 pin functions as the serial clock input pin. When this bit is "1", the pin functions as the serial clock output pin. Note: * When the UCK2 pin is set to function as serial clock input (UCKE = 0), set the P44/INT24/UCK2 pin to be an input port. Alternatively, select use of the external clock with the clock input selection bit (SRC1: SCS1, SCS0 = 00B). * When the UCKE pin is set to function as a serial clock output (UCKE = 0), select a clock other than the external clock (SRC1:SCS1, SCS0 = other than 00B). Reference: When the UCK2 pin is set to function as a serial clock output (UCKE = 1), the pin functions as the UCK2 output pin regardless of the state of the general-purpose port (P44). * When this bit is "0", the P45/INT25/UO2 pin functions as a general-purpose port (P45). When this bit is "1", it functions as a serial data output pin (UO). Reference: When serial clock output is specified (UOE = 1), the pin functions as the UO2 pin regardless of the state of the general-purpose port (P45). bit0 UOE: Serial data output enable bit 401 CHAPTER 17 HIGH-SPEED UART 17.4.2 Serial Mode Control Register 2 (SMC12) Serial mode control register 2 (SMC12) enables/disables the baud rate generator, specifies whether the output of the high-speed UART I/O signal pins is to be inverted, and sets the input clock division ratio of the baud rate generator. I Serial Mode Control Register 2 (SMC12) Figure 17.4-3 Serial Mode Control Register 2 (SMC12) Address Initial value --100001B Baud rate generator divider setting bit Clock division ratio Baud rate generator clock selection bit CPU operation clock Subclock High-speed UART I/O signal inversion bit Not inverted Inverted Baud rate generator enable bit Disabled Enabled Can be read and written Unused Initial value 402 17.4 Registers of the High-Speed UART Table 17.4-2 Functions of the Serial Mode Control Register 2 (SMC12) Bits Bit name bit7 bit6 bit5 Unused PSEN: Baud rate generator enable bit LSEL: High-speed UART I/O signal inversion bit PDCK: Clock selection bit * * * Function Value read is undefined. Writing has no effect on the operation. This bit enables or disables the baud rate generator. bit4 * This bit specifies whether to invert the high-speed UART I/O data. bit3 Baud rate generator enable bit * This bit selects a division ratio of the divider, which is located in the stage preceding the baud rate generator. Note: For the CPU operation clock, "FCH/2" is used in main watch mode (SYCC:SCS = 1), and "FCL" is used in subwatch mode (SYCC:SCS = 0). * * * Bits 2, 1, and 0 select the division ratio of the divider, which is located in the stage preceding the baud rate generator. In clock synchronous mode, any divide-by-three setting is prohibited. These bits enable/disable the baud rate generator. bit2 bit1 bit0 PDS2, PDS1, PDS0: Baud rate generator divider setting bits 403 CHAPTER 17 HIGH-SPEED UART 17.4.3 Serial Rate Control Register (SRC1) The serial rate control register (SRC1) controls the data transfer rate (baud rate) in asynchronous mode. This register selects an input clock and sets the transfer rate for the baud rate generator. I Serial Rate Control Register (SRC1) Figure 17.4-4 Serial Rate Control Register (SRC1) Address 0 0 2 3H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value --011000B CR SCS1 SCS0 RC2 RC1 RC0 R/W R/W R/W R/W R/W R/W RC2 RC1 RC0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock rate input selection bit Division ratio 1 2 4 8 16 32 64 128 Clock rate input selection bit SCS1SCS0 CR bit External clock PWM timer 1 output (*1) Dedicated baud rate generator 0 1 0 1 0 1 1 0 1 1 0 1 Clock division ratio Asynchronous Synchronous 16 1 64 16 64 16 64 8 2 1 2 0 0 0 1 *1 PWM timer 1 output of the 2-channel 8-bit PWM timer Clock rate input selection bit CR 0 R/W : Can be read and written : Unused : Initial value 1 Valid only in asynchronous transfer mode (SMC: SMDE = 1) (*2) Clock division ratio 16 64 *2 If the dedicated baud rate generator is used (SCS1, SCS0 = 11B), input clock divide by 8 is used regardless of the CR bit value. 404 17.4 Registers of the High-Speed UART Table 17.4-3 Functions of the Serial Rate Control Register (SRC1) Bits Bit name bit7 bit6 Unused * * * Function The read value is undefined. Writing has no effect on operation. This bit selects the clock rate in asynchronous transfer mode. If the dedicated baud rate generator is used (SCS1, SCS0 = 11B), divide by 8 is used regardless of the CR bit value. When the external clock or two-channel 8-bit PWM timer output is specified as the clock input, the baud rate becomes 1/16 or 1/64 of the clock frequency, depending on the CR value. This bit has no meaning in synchronous transfer mode. These bits select clock input. The clock input can be selected from the external clock (UCK pin), two-channel 8-bit PWM timer (PWM timer 1 output), and dedicated baud rate generator. In asynchronous transfer mode, eight baud rates can be selected. In synchronous transfer mode, six baud rates can be selected. These bits are valid only when the dedicated baud rate generator is used for clock input. These bits are invalid when the external clock or two-channel 8-bit PWM timer 1 output is used. bit5 CR: Clock rate selection bit * * bit4 bit3 SCS1, SCS0: Clock input selection bits * * * bit2 bit1 bit0 RC2, RC1, RC0: Baud rate selection bits * 405 CHAPTER 17 HIGH-SPEED UART 17.4.4 Serial Status/Data Register (SSD1) The serial status/data register (SSD1) indicates the transmission/reception status, error status, and received parity data or bit 8 received data in the high-speed UART. SSD1 also enables/disables interrupts, and can be used to set and check transmission parity data or bit 8 transmission data. I Serial Status/Data Register (SSD1) Figure 17.4-5 Serial Status/Data Register (SSD1) Address Initial value 00100-1XB Bit 8 received data/parity bit Without parity With parity (SMC11 : PEN = 1) (SMC11 : PEN = 0) Odd parity is detected. Even parity is detected. Bit 8 received data (*1) Bit 8 transmission data/parity bit With parity Without parity (SMC11 : PEN = 1) (SMC11 : PEN = 0) Odd parity is added. Even parity is added. Bit 8 transmission data (*1) is set. Reception interrupt request enable bit Disables reception interrupt request output. Enables reception interrupt request output. Transmission interrupt request enable bit Disables transmission interrupt request output. Enables transmission interrupt request output. Transmission data flag bit Transmission data is found. Transmission data is not found. Received data flag bit/error flag bit No data is found. Framing error Normal data Overrun error (The old data is retained.) *1 Can be read and written Read only Unused Undefined Initial value Valid only for a data length of nine bits (SMC: MC2, MC1, MC0 = 100B, operation mode 4) 406 17.4 Registers of the High-Speed UART Table 17.4-4 Functions of the Serial Status/Data Register (SSD1) Bits Bit name * * bit7 RDRF: Received data flag bit * * * * ORFE: Overrun error flag bit Function This bit indicates the state of the serial input data register (SIDR1). Setting this bit to 1 start to read the SSD1 register and then reading the SIDR1 register clears the received data flag bit (RDRF). When this bit and the reception interrupt request enable bit (RIE) are both "1", a reception interrupt request is output. This bit is a read-only bit. Writing does not change the value of this bit and has no effect on operation. This bit is a flag for indicating whether an overrun or a framing error has occurred. If an error occurs (ORFE = 1), no data is transferred from the reception shift register to the SIDR1 register. Consequently, the RDRF bit is not set in this case. When this bit is "1", reading the SSD1 register and SIDR1 register, in this sequence, clears this bit to "0". When this bit and the reception interrupt request enable bit (RIE) are both "1", a reception interrupt request is output. This bit is a read-only bit. Writing does not change the value of this bit and has no effect on operation. This bit is a flag indicating the state of the serial output data register (SODR1). When this bit is "1", reading the SSD1 register then writing data in the SODR1 register causes the data to be output to the serial data output pin (U02). When "1" is written to this bit and the transmission interrupt request enable bit (TIE), a transmission interrupt request is output. This bit enables transmission interrupt requests to the CPU. When both this bit and the transmission data flag bit (TDRE) are "1", a transmission interrupt request is output. This bit enables reception interrupt requests to the CPU. When both this bit and the received data flag bit (RDRF) are "1", a reception interrupt request is output. When both this bit and the overrun error flag bit (ORFE) are "1", a reception interrupt request is output when an error occurs. The read value of this bit is undefined. Writing to this bit has no effect on operation. This bit is treated as bit 8 of the SODR1 register in operation mode 3 without parity (data length for transmission or reception: 9-bits). This bit has no meaning in operation modes other than mode 3 without parity. This bit specifies which parity, even or odd, is selected for data transmission when a parity bit is attached. This bit is treated as bit 8 of the SIDR1 register in operation mode 3 without parity (data length for transmission or reception: 9-bits). This bit has no meaning in operation modes other than mode 3 without parity. This bit indicates detection of parity in received data if a parity bit is attached. bit6 * * * * bit5 TDRE: Transmission data flag bit * * TIE: Transmission interrupt request enable bit RIE: Reception interrupt request enable bit * * * * * * * * bit1 TD8/TP: bit 8 transmission data/parity bit bit4 bit3 bit2 Unused * * bit0 RD8/RP: bit 8 received data/ parity bit * 407 CHAPTER 17 HIGH-SPEED UART 17.4.5 Serial Input Data Register (SIDR1) The serial input data register (SIDR1) is used for inputting (receiving) serial data. I Serial Input Data Register (SIDR1) Figure 17.4-6 "Serial Input Data Register (SIDR1)" shows the bit configuration of the serial input data register. Figure 17.4-6 Serial Input Data Register (SIDR1) Address Initial value R : Read only X : Undefined The SIDR1 is used for storing received data. The serial data signal sent to the serial data input pin (UI pin) is first converted in the shift register and then stored in this register. In operation mode 0, 1, 2 or 4 When the received data has been successfully stored in SIDR1, the receive data flag bit (SSD1: RDRF) is set to "1". If reception interrupt requests are enabled, a reception interrupt will occur. If a check of the SSD1: RDRF bit during interrupt processing or by the program indicates that the received data is stored in SIDR1, read SSD1 and SIDR1, then clear the SSD1: RDRF flag. In operation mode 3 Both RDRF and ORFE are set when data transfer ends, the last data bit (D8) is "1", and the stop bit for the last transfer has been detected. If a framing error is detected, however, the flags are set irrespective of the last data bit. An interrupt request to the CPU occurs when these flags are set and the data input bit is "1". 408 17.4 Registers of the High-Speed UART 17.4.6 Serial Output Data Register (SODR1) The serial output data register (SODR1) is used for outputting (transmitting) serial data. I Serial Output Data Register (SODR1) Figure 17.4-7 "Serial Output Data Register (SODR1)" shows the bit configuration of the serial output data register. Figure 17.4-7 Serial Output Data Register (SODR1) Address Initial value W : Write only X : Undefined When data to be transmitted is written to this register after the SSD1 register has been read in the transmission-enabled state, the data is transferred to the shift register for transmission, converted to serial data, and transmitted from the serial data output pin (UO pin). When the transmission data is written to SODR1, the transmission data flag bit is set to "0". After the transmission data is transferred to the shift register for transmission, the transmission data flag bit is set to "1" so that the next transmission data item can be written to the register. If interrupt requests are enabled at this time, an interrupt occurs. The transmission data next item can be written when a transmission interrupt is generated or when the transmission data flag bit is set to "1". 409 CHAPTER 17 HIGH-SPEED UART 17.5 High-Speed UART Interrupts The high-speed UART has three flags related to interrupts: the error flag bit (SSD1: ORFE), received data flag bit (SSD1: RDRF), and transmission data flag bit (SSD1: TDRE). These flags are used for the following two interrupt sources: * Received data is transferred from the shift register for reception to the serial input data register (SIDR1) (reception interrupt) * Transmission data is transferred from the serial output data register (SODR1) to the shift register for transmission (transmission interrupt) I Transmission Interrupt When output data is written to SODR1 after SSD1 is read, the data written to SODR1 is transferred to the shift register for internal transmission. When the register is ready to accept the next data item, the TDRE bit is set to "1". If transmission interrupts are enabled (SSD1: TIE = 1), an interrupt request is issued to the CPU (IRQC). I Reception Interrupt In operation mode 0, 1, 2, or 4 After data has been input up to the stop bit, the RDRF bit is set to "1". If an overrun error or framing error occurs, the ORFE bit is set to "1". These bits are set when the stop bit is detected. If reception interrupts are enabled (SSD1: RIE = 1), an interrupt request is issued to the CPU (IRQB). In operation mode 3 Both the SSD1: RDRF and ORFE flags are set when the last data bit (D8) is "1" because data transfer has been completed and the stop bit for the last transfer has been detected. If a framing error is detected, however, these flags are set regardless of the last data bit. An interrupt request to the CPU is generated when these flags are set and the data input bit is "1". I Register and Vector Table Address for High-Speed UART Interrupts Table 17.5-1 Register and Vector Table Address for High-Speed UART Interrupts Interrupt level setting register Interrupt name IRQB IRQC Register ILR3 (007DH) ILR4 (007EH) Setting bits LB1 (bit7) LC1 (bit1) LB0 (bit6) LC0 (bit0) Vector table address Upper part of the address FFE4H FFE2H Lower part of the address FFE5H FFE3H For an explanation of the operation of interrupts, see 3.4.2 "Interrupt Processing " 410 17.6 Operation of the High-Speed UART 17.6 Operation of the High-Speed UART This section describes the operation of the high-speed UART. The high-speed UART has standard serial communication functions (in operation modes 0, 1, 2, 3, and 4). I Operation of the High-Speed UART Operation modes The high-speed UART has five operation modes. Modes 0, 1, 2, and 4 support ordinary serial transfer. Whether a parity bit is to be attached can be selected and the data length for transfer can be selected from four bits to 9-bits (see Table 17.1-1 "Operation Modes of the High-Speed UART"). Operation mode 3 supports serial transfer of eight-bit data and one slave bit. This mode can be used for connection of two or more slave CPUs to one host CPU. Transfer data format The high-speed UART can only handle data in non-return-to-zero (NRZ) format. Data transfer starts with the start bit ("L" level), then data of the data length specified in bits is transferred using the LSB-first method, and data transfer ends with the stop bit ("H" level). During asynchronous transfer, the relationship between the serial clock and serial I/O signal differs from that shown in Figure 17.6-1 "Transfer Data Format". Figure 17.6-1 "Transfer Data Format" shows the relationship between the transmission or reception clock and data when no parity is attached; operation mode 1, two stop bits, and synchronous transfer are selected; and the transfer data is 01001101B (8-bits). Figure 17.6-1 Transfer Data Format Transmission or reception clock Transmission or received data 411 CHAPTER 17 HIGH-SPEED UART 17.7 Operation of Operation Modes 0, 1, 2, and 4 Operation modes 0, 1, 2, 3, and 4 support the standard serial communication function. I Explanation of Operation Modes 0, 1, 2, and 4 Figure 17.7-1 Operation Modes 0, 1, 2, 3, and 4 bit7 SMC11 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PEN SBL MC2 MC1 MC0 SMDE UCKE UOE 1 SMC12 PSEN LSEL PDCK PDS2 PDS1 PDS0 x x x x x x : Used x : Unused 1 : With 1 0 : With 0 : These pins serve as TD8 and RD8, respectively, in mode 4 without parity. : Set as follows: Mode 0 = 000B, Mode 1 = 001B, Mode 2 = 010B, Mode 3 = 011B, Mode 4 = 100B, : Unused SRC1 CR SCS1 SCS0 RC2 RC1 RC0 SSD1 RDRF OREF TDRE TIE RIE TD8 RD8 /TP /RP SIDR1 Received data is saved. SODR1 Transmission data is written. DDR4 Transmission operation When transmission data is written to SODR1 after SSD1 is read, the data is transferred to the shift register for transmission and parallel-serial conversion starts. The converted transmission data is output from the serial data output pin beginning with the LSB bit (LSB first). When writing of the next item of data is enabled, the TDRE bit is set to "1". If transmission interrupts are enabled (SSD1: TIE = 1), an interrupt request to the CPU is issued. Figure 17.7-2 "Transmission Operation in Operation Modes 0, 1, 2, 3, and 4" shows the transmission operation performed when operation mode 2 is set, no parity is added, and one stop bit is used. 412 17.7 Operation of Operation Modes 0, 1, 2, and 4 Figure 17.7-2 Transmission Operation in Operation Modes 0, 1, 2, 3, and 4 SSD1 read SODR1 write (interrupt processing routine) TDRE Transmission interrupt Transfer to the shift register for transmission Transfer to the shift register for transmission Transmission buffer full Transmission data Reception operation (modes 0, 1, 2, and 4) When received data is sent to the serial data input pin, the data is converted from serial to parallel format using the internal shift register for reception. When data has been sent successfully up to the stop bit, the data in the internal shift register is transferred to the SIDR1 register and the SSD1: RDRF bit is set to "1". If an overrun or framing error occurs, the received data is not transferred to the SIDR1 register and the SSD1: ORFE bit is set to "1". The SSD1: RDRF and ORFE bits are set when data reception is completed and the last stop bit is detected. If reception interrupts are enabled (SSD1: RIE = 1), an interrupt request (IRQB) to the CPU is generated. When the RDRF bit is set, the received data has been transferred to the SIDR1 register. Figure 17.7-3 "Reception Operation in Modes 0, 1, 2 and 4" to Figure 17.7-5 "Operation When a Framing Error Occurs in Operation Modes 0, 1, 2, and 4" show the reception operation performed when operation mode 0, 1, 2, and 4 are set, no parity is attached, and one stop bit is set. Figure 17.7-3 Reception Operation in Modes 0, 1, 2 and 4 Data Reception interrupt 413 CHAPTER 17 HIGH-SPEED UART Figure 17.7-4 Operation When an Overrun Error Occurs in Operation Modes 0, 1, 2, and 4 Data (reception buffer full) Reception interrupt Figure 17.7-5 Operation When a Framing Error Occurs in Operation Modes 0, 1, 2, and 4 Data Reception interrupt Note: After initialization has been canceled by a reset, a period of 11 shift clocks is required for initialization of the internal control section. To perform the initialization, the microprocessor sends dummy data "FFH" at the UART setting baud rate. If UO2 pin output enable is set in the SMC11 register during initialization, the start bit of the dummy data is output. Thus, UO2 pin output enable must be set after 12 shift clocks of the initial baud rate have elapsed after a reset. The dummy data is transmitted only once at UART initialization after a reset. No dummy data is sent unless a reset is performed again. The initial value of the SSD1 register described in the manual is the value set after the completion of UART initialization. 414 17.8 Operation of Operation Mode 3 17.8 Operation of Operation Mode 3 Operation mode 3 applies to cases where one host CPU connects to multiple slave CPUs I Description of high-speed UART operation mode 3 Transmission operation After data is read from the SSD1 register and written into the SODR1 register, the data is transferred to the shift register for transmission and parallel-serial conversion starts. The converted transmission data is output from the serial data output pin beginning with the LSB bit (LSB first). When writing of the next item of data is enabled, the TDRE bit is set to "1". If the transmission interrupts are enabled (SSD1:TIE = 1), an interrupt request is issued to the CPU. Figure 17.8-1 "Transmission Operation in Operation Mode 3" shows the transmission operation that is performed when operation mode 0 is set, no parity is added, and two stop bits are used. Figure 17.8-1 Transmission Operation in Operation Mode 3 SSD1 read SODR1 write (interrupt processing routine) TDRE Transmission buffer full Transmission interrupt Transmission data Transfer to the shift register for transmission START 0 1 2 3 4 5 Transfer to the shift register for transmission 6 7 STOP START Reception operation When data is received at the serial data input pin, the data is converted from serial to parallel using the internal shift register for reception. Once the data has been received successfully up to the stop bit, the data in the internal shift register is transferred to the SIDR1 register and the SSD1:RDRF bit is then set to "1". If an overrun or framing error occurs, the received data is not transferred to the SIDR1 register and the SSD1:ORFE bit is set to "1". The flags of the SSD1:RDRF and ORFE bits are set when received data is successfully transferred with the last data bit set to "1" and the last stop bit detected. If, however, a framing error occurs, the flags are set regardless of the last data bit. A CPU interrupt request is generated when the flags are set and the input data becomes "1". If reception interrupts have been enabled (SSD1:RIE = 1), a CPU interrupt request (IRQB) is generated. When the RDRF bit has been set, the received data is transferred to the SIDR1 register. Figure 17.8-2 "Reception in Operation Mode 3" to Figure 17.8-4 "Operation for a Framing Error in Operation Mode 3" illustrate reception in operation mode 3. 415 CHAPTER 17 HIGH-SPEED UART Figure 17.8-2 Reception in Operation Mode 3 Data 4 5 6 7 8 STOP STOP RDRF Reception interrupt Figure 17.8-3 Operation for an Overrun Error in Operation Mode 3 Data 4 5 6 7 8 STOP RDRF = 1 ORRF Reception interrupt Figure 17.8-4 Operation for a Framing Error in Operation Mode 3 Data 4 5 6 7 8 STOP STOP RDRF = 0 ORRF Reception interrupt Note: Operation of UART initialization This UART requires a period of 11 shift clocks (after supply of the clock for generating a baud rate is started) to initialize. To perform initialization, the microprocessor sends dummy data "FFH" at the UART setting baud rate. Setting UO2 output enable in the SMC11 register during the initialization, the start bit of the dummy data is output. Thus, UO2 output enable must be set after 12 shift clocks of a specified baud rate have elapsed after the supply of the clock for generating a baud rate to the UART is started. The dummy data is transmitted only once upon UART initialization after a reset. No dummy data is sent unless another reset is issued. The initial value of the SSD1 register described in the manual is the value that is set after the completion of UART initialization. * Timing at which the supply of the clock for generating a baud rate is started: * Case in which a dedicated baud rate generator is being used: When operation of the baud rate generator is allowed (When "1" is written into the PSEN bit of the SMC12 register) Case in which the internal timer is being used: When the PWM timer 1 counter starts operating Case in which an external clock is being used: When input of the external clock is started * * 416 17.9 Program Example of the UART 17.9 Program Example of the UART This section shows a program example for the UART. I Program Example of the UART Processing specifications * * * * * Serial transfer, transmission, and reception operations are performed using the communication function of the UART. P44/INT24/SCK2, P45/INT25/SO2, and P46/INT26/UI2 are used for communication. The transfer rate is set to 300 baud by the internal baud rate generator. 13H is transmitted from the UO pin to trigger the operation with an interrupt. The baud rate indicated is that used when the main clock oscillation frequency (FCH) is set to 10 MHz and the main clock is set to the fastest (instruction cycle = 4/FCH) (1/300 baud = 8320tinst). 417 CHAPTER 17 HIGH-SPEED UART Coding example EQU 0010H ;Address of port data register EQU 0011H ;Address of port data direction register EQU 0022H ;Address of serial mode control register EQU 0023H ;Address of serial rate control register EQU 0024H ;Address of serial status/data register EQU 0025H ;Address of serial input data register EQU 0025H ;Address of serial output data register EQU 007DH ;Address of interrupt level setting register DSEG ABS ;[DATA SEGMENT] ORG 0FFE4H IRQB DW WARI ;Set interrupt vector. INT_V ENDS ---------Main program-----------------------------------------------------------CSEG ;[CODE SEGMENT] : CLRI ;Disable interrupts. MOV ILR3,#01111111B ;Set the interrupt level (level 1). MOV DDR4,#00000000B ;Set the UI2 pin as an input pin. MOV SMC11,#01001111B ;Attach no parity; set one stop bit, operation mode 1, and asynchronous mode, clock output enable, and serial data output enable. (Set them after the 11 shift clock period needed for UART initialization after a reset has elapsed.) MOV SRC1,#00011101B ;Select the dedicated baud rate generator and set the baud rate to 300 baud. MOV SSD1,#00001000B ;Disable transmission interrupt requests and enable reception interrupt requests. MOV A,SSD1 ;Perform this before transmission. (Setting TDRE = 1 enables transmission.) MOV A,SIDR1 ;Clear an error flag. MOV SODR1,#13H ;Write transmission data (13H). SETI ;Enable interrupts. : ---------Interrupt processing routine-------------------------------------------WARI PUSHW A ;Save A and T. XCHW A,T PUSHW A MOV A,SSD1 ;Read transfer data and clear the input data flag. MOV A,SIDR1 : User processing : POPW A ;Restore A and T. XCHW A,T POPW A RETI ENDS ---------------------------------END PDR4 DDR4 SMC11 SRC1 SSD1 SIDR1 SODR1 ILR3 INT_V 418 CHAPTER 18 8-BIT SERIAL I/O This chapter describes the functions and operation of the 8-bit serial I/O. 18.1 "Overview of the 8-Bit Serial I/O" 18.2 "Configuration of the 8-Bit Serial I/O" 18.3 "Pins of the 8-Bit Serial I/O" 18.4 "Registers of the 8-Bit Serial I/O" 18.5 "8-Bit Serial I/O Interrupts" 18.6 "Operation of the Serial Output" 18.7 "Operation of the Serial Input" 18.8 "States in Each Mode of 8-Bit Serial I/O Operation" 18.9 "Notes on Using the 8-Bit Serial I/O" 18.10 "8-Bit Serial I/O Connection Example" 18.11 "Program Examples of the 8-Bit Serial I/O" 419 CHAPTER 18 8-BIT SERIAL I/O 18.1 Overview of the 8-Bit Serial I/O The 8-bit serial I/O transfers 8-bit serial data synchronized by the shift clock. The shift clock can be selected from three internal clocks and an external clock. Either LSBfirst or MSB-first can be selected as the data shift direction. I Serial I/O Function The 8-bit serial I/O transfers 8-bit serial data synchronized by the shift clock. * * * * Converts 8-bit parallel data to serial data and outputs. Converts serial data into parallel data and stores it. The shift clock can be selected from three internal clocks and an external clock. Shift clock input and output can be controlled and the internal shift clock can be output. Either LSB-first or MSB-first can be selected as the data shift direction (transfer direction). Table 18.1-1 Shift Clock Period and Transfer Speed Shift clock Clock period 2tinst Internal shift clock (output) 8tinst 32tinst External shift clock (input) 2tinst or more Frequency (Hz) 1/(2tinst) 1/(8tinst) 1/(32tinst) 1/(2tinst) or less Transfer speed (FCH = 10 MHz, maximum clock speed (*1)) 1250 kbps 312.5 kbps 28.125 kbps DC to 1250 kbps FCH: Main clock oscillation tinst: Instruction cycle (depends on clock mode, etc.) *1: For the case of main clock mode (SCS = 1) with the maximum clock speed (CS1, CS0 = 11B, 1 instruction cycle = 4/FCH) selected in the system clock control register (SYCC). 420 18.2 Configuration of the 8-Bit Serial I/O 18.2 Configuration of the 8-Bit Serial I/O Each channel of the 8-bit serial I/O consists of the following four blocks: * Shift clock control circuit * Shift clock counter * Serial data register (SDR) * Serial mode register (SMR) I Block Diagram of 8-Bit Serial I/O Figure 18.2-1 Block Diagram of 8-Bit Serial I/O Internal data bus D0 to D7 MSB-first P43/INT23/ SI2/SCL Pin Transfer direction selection D7 to D0 LSB-first D7 to D0 SST BDS (Shift direction) Serial data register (SDR) P42/INT22/SO2/SDA Pin Output buffer CKS0 CKS1 Output enable Output enable Shift clock selection 2 SOE SCKE SIOE SIOF Overflow 2tinst 8tinst 32tinst Shift clock control circuit P41/INT21/SCK2 Pin Output buffer Clear Shift clock counter tinst: Instruction cycle Serial mode register (SMR) Interrupt request IRQ9 421 CHAPTER 18 8-BIT SERIAL I/O Shift clock control circuit The shift clock can be selected from three internal clocks and an external clock. If an internal clock is selected, the shift clock can be output to the SCK2 pin. Selecting the external clock uses the clock input from the SCK2 pin as the shift clock. The SDR register shift operation is driven by this shift clock and the shifted-out values are output from the SO2 pin. Similarly, the SI2 pin input is shifted into the SDR register. Shift clock counter This counter counts the number of SDR register shifts driven by the shift clock and overflows after the 8-bit shift is complete. When the counter overflows, the serial I/O transfer start bit of the SMR register is cleared (SMR: SST = 0) and the interrupt request flag is set (SMR: SIOF = 1). Halting serial transfer (SMR: SST = 0) halts the count on the shift clock counter and the counter is cleared by the next start (SMR: SST = 1). Serial data register (SDR) This register stores the transfer data. The data written to this register is converted to serial data and is output. At the same time, the serial data is converted to parallel data and stored. Serial mode register (SMR) This is the control register for the serial I/O. The register functions include enabling and disabling serial I/O operation, selecting the shift clock, setting the transfer (shift) direction, controlling interrupts, and checking the status. Cause of an interrupt related to 8-bit serial I/O IRQ9: When the I/O function completes 8-bit serial data I/O, 8-bit serial I/O generates an interrupt request (IRQ9) if output of interrupt requests has been enabled (SMR:SIOE = 1). 422 18.3 Pins of the 8-Bit Serial I/O 18.3 Pins of the 8-Bit Serial I/O This section describes the 8-bit serial I/O pins, provides block diagrams of the pins, and explains the causes of 8-bit serial I/O interrupts. I 8-bit Serial I/O Pins The 8-bit serial I/O pins are P43/INT23/SI2/SCL, P42/INT22/SO2/SDA, P41/INT21/SCK2. P43/INT23/SI2/SCL pin The P43/INT23/SI2/SCL pin can function as an N-ch open-drain I/O port (P43), external interrupt pin (INT23), serial data input (hysteresis input) for 8-bit serial I/O (SI2), or I2C serial clock I/O pin (SCL). P42/INT22/SO2/SDA pin The P42/INT22/SO2/SDA pin can function as a general-purpose I/O port (P42), external interrupt pin (INT22), serial data output pin (N-ch open-drain) for 8-bit serial I/O (SO), or I2C data I/O pin (SDA). Enabling serial data output (SMR:SOE = 1) automatically sets the pin for output (SO2). P41/INT21/SCK2 pin The P41/INT21/SCK2 pin can function either as a general-purpose I/O port (P41), external interrupt pin (INT21), or shift clock I/O pin (hysteresis input) for serial I/O (SCK2). * When used as the shift clock input pin: To use the SCK pin as an input, set as an input port in the port data direction register (DDR4: bit 1 = 0) and disable shift clock output (SMR:SCKE = 0). In this case, select the external shift clock (SMR:CKS1, CKS0 = 11B). * When used as the shift clock output pin: Enabling shift clock output (SMR:SCKE = 1) automatically sets the P41/INT21/SCK2 pin as an output pin regardless of the value of the port data direction register (DDR4: bit 1) and sets the pin to function as the SCK2 output pin. In this case, select an internal shift clock (SMR:CKS1, CKS0 = other than 11B). 423 CHAPTER 18 8-BIT SERIAL I/O I Block Diagram of 8-Bit Serial I/O Pins Figure 18.3-1 Block Diagram of SCK2 Pin Stop/watch mode (SPL = 1) External interrupt input enable To external interrupt circuit To SCK2 input Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) Pull-up resistor About 50 k PDR read SCK2 output SCK2 output enable Port 4 pull-up resistor control register Pch PDR read (for bit manipulation instructions) Output latch PDR write Pch Pin DDR (port data direction register) Nch P41/INT21/SCK2 DDR write Stop/watch mode (SPL = 1) DDR read SPL: Pin status specification bit of standby control register (STBC) Reference: If "pull-up resistor available" is selected using the port 4 pull-up resistor control register, the pins are set to the "H" (pulled up) level, not the high impedance state, in stop mode or watch mode (STBC:SPL = 1) . During a reset, however, the pull-up is disabled and the pins are set to the Hi-z level. 424 18.3 Pins of the 8-Bit Serial I/O Figure 18.3-2 Block Diagram of SI2 Pin To external interrupt circuit Stop/watch mode (SPL = 1) External interrupt input enable To peripheral resource input Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) PDR read SCL output SCL output enable PDR read (for bit manipulation instructions) Output latch PDR write Pin Nch P43/INT23/SI2/SCL Stop/watch mode (SPL = 1) SPL: Pin status specification bit of standby control register (STBC) Reference: For the P43/INT23/SI2/SCL pin, the port 4 pull-up control register cannot be used to select whether pull-up resister is available or unavailable. To use the P43/INT23/SI2/SCL pin as an output pin, attach a pull-up resistor to the external pin. 425 CHAPTER 18 8-BIT SERIAL I/O Figure 18.3-3 Block Diagram of SO2 Pin Stop/watch mode (SPL = 1) External interrupt input enable To external interrupt circuit To SDA input Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) PDR read SD2 output SDA output Peripheral resource output enable PDR read (for bit manipulation instructions) Output latch PDR write Pin Nch P42/INT22/SO2/SDA Stop/watch mode (SPL = 1) SPL: Pin status specification bit of standby control register (STBC) Reference: For the P42/INT22/SO2/SDA pin, the port 4 pull-up control register cannot be used to select whether the pull-up resistor is available or unavailable. To use the P42/INT22/SO2/SDA pin as an output pin, attach a pull-up resistor to the external pin. 426 18.4 Registers of the 8-Bit Serial I/O 18.4 Registers of the 8-Bit Serial I/O This section describes the 8-bit serial I/O registers. I 8-Bit Serial I/O Registers Figure 18.4-1 8-Bit Serial I/O Registers SMR (Serial mode register) Address 0 0 7 0H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST R/W R/W R/W R/W R/W R/W R/W R/W SDR (Serial data register) Address 0 0 7 1H R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable X : Undefined bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB 427 CHAPTER 18 8-BIT SERIAL I/O 18.4.1 Serial Mode Register (SMR) The serial mode register (SMR) is used to enable and disable 8-bit serial I/O operation, select the shift clock, set the transfer direction, control interrupts, and check the status. I Serial Mode Register (SMR) Figure 18.4-2 Serial Mode Register (SMR) Address 0 0 7 0H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST R/W R/W R/W R/W R/W R/W R/W R/W 00000000B SST 0 1 BDS 0 1 Serial I/O transfer start bit Read Serial transfer halted Serial transfer in progress Write Halt/disable serial transfer Start/enable serial transfer Transfer direction select bit LSB-first (start transfer from least significant bit) MSB-first (start transfer from most significant bit) Shift clock select bits 2tinst Internal shift clock External shift clock 8tinst 32tinst SCK pin Output Output Output Input CKS1 CKS0 0 0 1 1 0 1 0 1 tinst: Instruction cycle SOE 0 1 Serial data output enable bit Use P42/INT22/SO2/SDA as a general-purpose port Use P42/INT22/SO2/SDA as the serial data output pin SCKE 0 1 Shift clock output enable bit Use P41/INT21/SCK2 as a general-purpose port or shift clock input pin Use P41/INT21/SCK2 as the shift clock output pin SIOE 0 1 Interrupt request enable bit Disable output of interrupt requests Enable output of interrupt requests Interrupt request flag bit SIOF R/W : Readable and writable : Initial value 0 1 Read Transfer is incomplete Transfer is complete Write Clear this bit No change, no other effect 428 18.4 Registers of the 8-Bit Serial I/O Table 18.4-1 Function of Each Serial Mode Register (SMR) Bit Bit bit7 SIOF: Interrupt request flag bit * Description Set to "1" after the serial I/O operation has input and output 8 bits of serial data. An interrupt request is output if this bit and the interrupt request enable bit (SIOE) are "1". Writing "0" clears the bit. Writing "1" has no effect and does not change the bit value. * bit6 SIOE: Interrupt request enable bit SCKE: Shift clock output enable bit This bit enables or disables output of interrupt requests to the CPU. An interrupt request is output if this bit and the interrupt request flag bit (SIOF) are "1". This bit controls shift clock input and output. The P41/INT21/SCK2 pin becomes the shift clock input pin when this bit is "0" and the shift clock output pin when the bit is "1". Note: * When used as the shift clock input, the P41/INT21/SCK2 pin must be set as an input port. Also, select the external shift clock in the shift clock select bits (CKS1, CKS0 = 11B). * Select an internal shift clock (CKS1, CKS0 = other than 11B) when the pin is the shift clock output (SCKE = 1). Reference: * Enabling the shift clock output (SCKE = 1) causes the P41/INT21/SCK2 pin to function as the SCK output pin regardless of the state of the general-purpose port (P41). * When using the P41/INT21/SCK2 pin as a general-purpose port (P41), set as a shift clock input (SCKE = 0). The P42/INT22/SO2/SDA pin becomes a general-purpose port (P42) when this bit is "0" and the serial data output pin (SO2) when the bit is "1". Reference: Enabling serial data output (SOE = 1) causes the P42/INT22/SO2/SDA pin to function as the SO2 pin regardless of the state of the general-purpose port (P42). * * These bits select the external shift clock or one of the three internal shift clocks. When these bits are other than "11B", an external shift clock is selected and, if the shift clock output enable bit (SCKE) is "1", the shift clock is output from the SCK2 output pin. When these bits are "11B", the external shift clock is selected and, if set as the shift clock input, the shift clock is input from the SCK2 output pin (SCKE=0, DDR2:bit5=0). * * bit5 bit4 SOE: Serial data output enable bit bit3 bit2 CKS1, CKS0: Shift clock select bits * bit1 BDS: Transfer direction select bit This bit selects whether to transfer the serial data starting from the least significant bit (LSB-first, BDS = 0) or the most significant bit (MSB-first, BDS = 1). Note: As the bit order is set when the data is read or written to the serial data register (SDR), changing the value of this bit after data has been written to the SDR register invalidates the data. * * * This bit controls starting and enabling of serial I/O transfer. The bit can also be used to test whether transfer is complete. When using an internal shift clock (CKS1, CKS0 = other than 11B), writing "1" to this bit clears the shift clock counter and starts transfer. When using an external shift clock (CKS1, CKS0 = 11B), writing "1" to this bit enables transfer, clears the shift clock counter, and waits for input of the external shift clock. When transfer is completed, the bit is cleared to "0" and the SIOF bit is set to "1". Writing "0" to this bit during transfer (SST = 1) halts the transfer. Once a transfer has been halted, the output SDR register must be written to again and the transfer restarted for data input (to clear the shift clock counter). bit0 SST: Serial I/O transfer start bit * * 429 CHAPTER 18 8-BIT SERIAL I/O 18.4.2 Serial Data Register (SDR) The serial data register (SDR) stores the 8-bit serial I/O transfer data. For serial output operation, the register functions as the transmission data register. For serial input operation, the register functions as the reception data register. I Serial Data Register (SDR) Figure 18.4-3 "Serial Data Register (SDR)" shows the bit structure of the serial data register. Figure 18.4-3 Serial Data Register (SDR) Address 0 0 7 1H R/W R/W R/W R/W R/W : Readable and writable X : Undefined bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value XXXXXXXXB R/W R/W R/W R/W Serial output operation The register functions as the transmission data register. Starting serial I/O transfer (SMR:SST = 1) performs serial transfer of the data written to this register. As the transmission data is shifted out by the transfer operation, the data does not remain in the SDR register. Serial input operation The register functions as the reception data register. Starting serial I/O transfer (SMR:SST = 1) stores the received serial transfer data in this register. During serial I/O transfer Do not write data to the SDR register while a serial I/O transfer operation is in progress. Similarly, values read from the register at this time have no meaning. If serial output and serial input are enabled at the same time, both serial input and output operations are performed. 430 18.5 8-Bit Serial I/O Interrupts 18.5 8-Bit Serial I/O Interrupts Completion of an 8-bit serial I/O operation generates an interrupt request from the 8-bit data serial I/O. I Interrupts during Serial I/O Operation The 8-bit serial I/O performs serial input and serial output simultaneously. When serial transfer starts, the contents of the serial data register (SDR) are input and output one bit at a time synchronized with the period of the specified shift clock. The interrupt request flag bit (SMR:SIOF) is set to "1" on the leading edge of the eighth shift clock pulse. An interrupt request (IRQ9) is output to the CPU if the interrupt request output enable bit is enabled (SMR:SIOE = 1) at this time. Write "0" to the SIOF bit in the interrupt processing routine to clear the interrupt request. The SIOF bit is always set when the output of 8 bits of serial is completed, regardless of the SIOE bit value. Reference: During serial I/O operation, setting the interrupt request flag bit (SMR:SIOF = 1) is not performed if serial transfer is halted (SMR:SST = 0) at the same time that serial data transfer is completed. An interrupt request is generated immediately if the SIOF bit is "1" when the SIOE bit is switched from disabled to enabled (0 to 1). I Register and Vector Table for the 8-Bit Serial I/O Interrupt Table 18.5-1 Register and Vector Table for the 8-Bit Serial I/O Interrupt Interrupt level setting register Interrupt Register IRQ9 ILR3 (007DH) Setting bits L91 (bit3) L90 (bit2) Upper FFE8H Lower FFE9H Vector table address For more information on interrupt operation, see Section 3.4.2 "Interrupt Processing". 431 CHAPTER 18 8-BIT SERIAL I/O 18.6 Operation of the Serial Output The 8-bit serial I/O can output 8-bit serial data synchronized with a shift clock. I Serial Output Operation Serial output can operate using either an internal or external shift clock. When serial I/O operation is enabled, the contents of the SDR register are output from the serial data output pin (SO2) at the same time that serial input is performed. When using an internal shift clock Figure 18.6-1 "Serial Output Settings (for an Internal Shift Clock)" shows the settings required for operating serial output using an internal shift clock. Figure 18.6-1 Serial Output Settings (for an Internal Shift Clock) bit7 SMR bit6 bit5 bit4 bit3 bit2 bit1 bit0 SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST 1 1 Other than "11" 1 : Used bit 1 : Set "1" SDR Sets transmit data Activating the serial output operation outputs the contents of the SDR register from the serial data output pin (SO2). Output is synchronized with the trailing edge of the selected internal shift clock. At this time, the device being communicated with (serial input device) must be waiting for the input of an external shift clock. When using an external shift clock Figure 18.6-2 "Serial Output Settings (for an External Shift Clock)" shows the settings required for operating serial output using an external shift clock. Figure 18.6-2 Serial Output Settings (for an External Shift Clock) bit7 DDR4 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SMR SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST 0 1 1 1 1 : : 1: 0: Used bit Unused bit Set "1" Set "0" SDR Sets transmit data Enabling the serial output operation outputs the contents of the SDR register from the serial data output pin (SO2). Output is synchronized with the trailing edge of the external shift clock. When serial output is completed, the SDR register must immediately be set again and operation enabled (SMR:SST = 1) so as to be ready to output the next data. When the serial input operation is completed (leading edge) at the receiving device, set the external shift clock to the "H" level while waiting for output of the next data (idle state). 432 18.6 Operation of the Serial Output Figure 18.6-3 "Operation of 8-Bit Serial Output" shows the operation of 8-bit serial output. Figure 18.6-3 Operation of 8-Bit Serial Output For LSB-first transfer bit7 bit6 SDR #7 #6 bit5 #5 bit4 #4 bit3 #3 bit2 #2 bit1 #1 bit0 #0 SO pin Serial output data Shift clock 0 SIOF bit #0 #1 #2 #3 #4 #5 #6 #7 1 2 3 4 5 6 7 Cleared by the program Transfer start SST bit Interrupt request Automatically cleared when transfer is completed I Operation when serial output is completed The interrupt request flag bit is set (SMR:SIOF = 1) and the serial I/O start bit cleared (SMR:SST = 0) on the leading edge of the shift clock after inputting and outputting the eighth bit of serial data. 433 CHAPTER 18 8-BIT SERIAL I/O 18.7 Operation of the Serial Input The 8-bit serial I/O can input 8-bit serial data synchronized with a shift clock. I Serial Input Operation Serial input can operate using either an internal or external shift clock. When serial I/O operation is enabled, the contents of the SDR register are output from the serial data output pin (SO2) at the same time that serial input is performed. When using an internal shift clock Figure 18.7-1 "Serial Input Settings (for an Internal Shift Clock)" shows the settings required for operating serial input using an internal shift clock. Figure 18.7-1 Serial Input Settings (for an Internal Shift Clock) bit7 DDR4 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SMR SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST 1 Other than "11B" 1 SDR Stores the received data : : 1: 0: Used bit Unused bit Set "1" Set "0" Activating the serial input operation inputs the value of the serial data input pin (SI2) to the SDR register. Input is synchronized with the leading edge of the selected internal shift clock. At this time, the device being communicated with (serial output device) must have set a value in the SDR register and be waiting for input of an external shift clock. When using an external shift clock Figure 18.7-2 "Serial Input Settings (for an External Shift Clock)" shows the settings required for operating serial input using an external shift clock. Figure 18.7-2 Serial Input Settings (for an External Shift Clock) bit7 DDR4 0 SMR SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST 0 SDR 1 1 1 : : 1: 0: Used bit Unused bit Set "1" Set "0" bit6 bit5 bit4 bit3 bit2 bit1 bit0 Stores the received data 434 18.7 Operation of the Serial Input Enabling the serial input operation inputs the value of the serial data input pin (SI1) to the SDR register. Input is synchronized with the leading edge of the external shift clock. When serial input is completed, the SDR register must immediately be read and operation enabled (SMR:SST = 1) so as to be ready to input the next data. While waiting for output of the next data (idle state), set the external shift clock to the "H" level. Figure 18.7-3 "Operation of 8-Bit Serial Input" shows the operation of 8-bit serial input. Figure 18.7-3 Operation of 8-Bit Serial Input For MSB-first transfer bit7 SDR #7 bit6 #6 bit5 #5 bit4 #4 bit3 #3 bit2 #2 bit1 #1 bit0 #0 SI2 pin Serial input data Shift clock #7 #6 #5 #4 #3 #2 #1 #0 0 SIOF bit 1 2 3 4 5 6 7 Cleared by the program Interrupt request SST bit Automatically cleared when transfer is completed I Operation When Serial Input is Completed The interrupt request flag bit is set (SMR:SIOF = 1) and the serial I/O start bit is cleared (SMR:SST = 0) on the leading edge of the shift clock after inputting and outputting the eighth bit of serial data. 435 CHAPTER 18 8-BIT SERIAL I/O 18.8 States in Each Mode of 8-Bit Serial I/O Operation This section describes the operation when the device enters sleep mode, the device enters stop or watch mode, or a halt request occurs during operation of the 8-bit serial I/O. I When Using an Internal Shift Clock Operation in sleep mode Figure 18.8-1 "Operation in Sleep Mode (Internal Shift Clock)" shows how serial I/O operation does not halt and transfer continues when the device enters sleep mode. Figure 18.8-1 Operation in Sleep Mode (Internal Shift Clock) SCK2 output SST bit Cleared by the program SIOF bit Interrupt request SO2 pin output #0 #1 #2 #3 #4 #5 #6 Sleep SLP bit (STBC register) Wakeup from sleep mode via IRQ9 #7 Operation in stop or watch mode Figure 18.8-2 "Operation in Stop or Watch Mode (Internal Shift Clock)" shows how serial I/O operation halts and transfer is interrupted when the device enters stop or watch mode. When the device wakes up from stop or watch mode, operation restarts from the point where it halted. Therefore, initialize the serial I/O in accordance with the state of the device with which you are communicating. Figure 18.8-2 Operation in Stop or Watch Mode (Internal Shift Clock) SCK2 output SST bit SIOF bit Interrupt request SO2 pin output STP bit (STBC register) #0 #1 #2 #3 #4 #5 Stop or watch mode Wakeup from stop or watch mode via an external interrupt #6 #7 Oscillation stabilization delay time Stop or watch mode request Cleared by the program 436 18.8 States in Each Mode of 8-Bit Serial I/O Operation Operation during a halt Figure 18.8-3 "Operation during a Halt (Internal Shift Clock)" shows how transfer halts and the shift clock counter is cleared when operation is halted midway through a transfer (SMR:SST = 0). Accordingly, the device with which you are communicating must also be initialized. When performing serial output, update the SDR register before restarting operation. Figure 18.8-3 Operation during a Halt (Internal Shift Clock) SCK2 output SST bit SIOF bit SO2 pin output #0 #1 #2 #3 #4 Operation halted Update SDR register Restart #5 #0 #1 I When Using an External Shift Clock Operation in sleep mode Figure 18.8-4 "Operation in Sleep Mode (External Shift Clock)" shows how serial I/O operation does not halt and transfer continues when the device enters sleep mode. Figure 18.8-4 Operation in Sleep Mode (External Shift Clock) Clock for next data SCK2 input SST bit SIOF bit SO2 pin output #0 #1 #2 #3 #4 #5 #6 Sleep Cleared by the program Interrupt request #7 SLP bit (STBC register) Wakeup from sleep mode via IRQ9 437 CHAPTER 18 8-BIT SERIAL I/O Operation in stop or watch mode Figure 18.8-5 "Operation in Stop or Watch Mode (External Shift Clock)" shows how serial I/O operation halts and transfer is interrupted when the device enters stop or watch mode. When the device wakes up from stop or watch mode, operation restarts from the point where it halted. Therefore, a transfer error occurs. You must reinitialize the serial I/O. Figure 18.8-5 Operation in Stop or Watch Mode (External Shift Clock) Clock for next data SCK2 input SST bit SIOF bit SO2 pin output STP bit (STBC register) #0 #1 #2 #3 #4 #5 Stop or watch mode #6 #7 Stop or watch mode request Oscillation stabilization wait time Cleared by the program Interrupt request #6 #7 Transfer error occurs Wakeup from stop or watch mode via an external interrupt Operation during a halt Figure 18.8-6 "Operation during a Halt (External Shift Clock)" shows how transfer halts and the shift clock counter is cleared when operation is halted midway through a transfer (SMR:SST = 0). Accordingly, the device with which you are communicating must also be initialized. When performing serial output, update the SDR register before restarting operation. At this time, the SO2 pin output changes when an external clock is input. Figure 18.8-6 Operation during a Halt (External Shift Clock) Clock for next data SCK2 input SST bit SIOF bit SO2 pin output #0 #1 #2 #3 Operation halted #6 #7 Restart Update SDR register #4 #5 #0 #1 438 18.9 Notes on Using the 8-Bit Serial I/O 18.9 Notes on Using the 8-Bit Serial I/O This section describes points to note when using the 8-bit serial I/O. I Notes on Using 8-Bit Serial I/O Error in serial transfer start timing As the timing at which serial transfer is activated by the program (SMR:SST = 1) is asynchronous to the trailing (output) or leading (input) edge of the shift clock, the timing of the first serial data input or output may be delayed by up to the period of the specified shift clock. Malfunction due to noise Malfunction may occur on the serial I/O if an unwanted pulse (a pulse which exceeds the hysteresis width) is present on the shift clock due to external noise during serial data transfer. Notes on setting the serial I/O by using the program * * * Write to the serial mode register (SMR) and serial data register (SDR) when the serial I/O is halted (SMR:SST = 0). Do not change the values of other SMR register bits when starting (enabling) serial I/O transfer (SMR:SST = 1). When inputting an external shift clock and when serial data output is enabled (SMR:SOE = 1), the output level of the SO1 pin enters the level of the most significant bit (for MSB-first transfer) or least significant bit (for LSB-first transfer) when the external shift clock is input, even if serial I/O transfer is halted (SMR:SST = 0). If serial I/O transfer is halted (SMR:SST = 0) at the same time that a serial data transfer is completed, the interrupt request flag bit (SMR:SIOF) is not set. Interrupt processing cannot return if the SIOF bit is "1" and interrupt request output is enabled (SIOE = 1). Always clear the SIOF bit. * * Serial I/O transfer speed The serial data output pin (SO2) for serial I/O cannot be used for high-speed transfer because of N-ch open-drain output. Note this point when high-speed shift clocks are used. Shift clock idle state During the delay between 8-bit data transfers (idle state), set the external shift clock to the "H" level. When using an internal shift clock (SMR2:CKS1, CKS0 = other than 11B) to provide the shift clock output (SMR:SCKE = 1), the output enters the "H" level when idling. Figure 18.9-1 "Shift Clock Idle State" shows the idle state of the shift clock. Figure 18.9-1 Shift Clock Idle State Idle state 8-bit data transfer Idle state 8-bit data transfer Idle state External shift clock 439 CHAPTER 18 8-BIT SERIAL I/O 18.10 8-Bit Serial I/O Connection Example This section shows an example of connecting together the 8-bit serial I/O of two MB89530/530H/530A series devices to perform bi-directional serial I/O. I Bi-Directional Serial I/O Figure 18.10-1 8-Bit Serial I/O Connection Example (Interfacing Two MB89530/530H/530A Devices) SO SIO-A SI SCK Output SI SO SIO-B Input SCK External shift clock Internal shift clock 440 18.10 8-Bit Serial I/O Connection Example Figure 18.10-2 Operation of Bidirectional Serial I/O SIO-A START SIO-B START Halt operation of SIO-A (SST = 0) Set the SI1 pin as a serial data input (input port) Halt operation of SIO-B (SST = 0) Set the SI1 pin as a serial data input (input port) - Set the SCK1 pin as the shift clock output - Set the SO1 pin as the serial data output - Select an internal shift clock - Set the data transfer (shift) direction - Set the SCK1 pin as the shift clock input - Set the SO1 pin as the serial data output - Select the external shift clock - Select the same data transfer (shift) direction as SIO-A NO Is serial transfer enabled for SIO-B? (*1) YES Set output data Transfer enable state Set output data Enable serial transfer (SST = 1) Start serial transfer (*2) (SST = 1) SIO-A Serial data transfer in progress SIO-A outputs serial data Simultaneously, SIO-A feeds the SIO-B data NO 8-bit transfer completed? (*3) YES (SST=0) SIO-B Serial data transfer in progress 8-bit transfer completed? (*3) NO YES (SST=0) Read input data Read input data YES Is there more data for transfer? NO END SST: The SST bit is the serial I/O transfer start bit of the serial mode register (SMR). *1 When only the SO, SI, and SCK pins are connected, there is no direct means of determining if serial transfer is enabled on SIO-B. Therefore, use a software timer or other method to have the system wait a sufficient amount of time for SIO-B to enable transfer. *2 Data transfer is not performed correctly if SIO-A starts transfer when serial transfer is not enabled on SIO-B. *3 An interrupt request is generated when an 8-bit data transfer is completed. 441 CHAPTER 18 8-BIT SERIAL I/O 18.11 Program Examples of the 8-Bit Serial I/O This section describes example programs using the 8-bit serial I/O. I Program Example for Serial Output Program specifications * * * * Output 8 bits of serial data (55H) from the SO2 pin of the serial I/O and generate an interrupt when transfer is completed. In the interrupt processing routine, set the next data to be transferred and restart output. Operate using an internal shift clock and output the shift clock from the SCK pin. The transfer speed and time between interrupts is as follows for a main clock oscillation (FCH) of 10 MHz, the main clock speed (gear) set to maximum speed (1 instruction cycle = 4/ FCH), and 32tinst shift clock. * * Transfer speed = 10 MHz/4/32 = 78.1 kbps Interrupt period = 8 x 32 x 4/10 MHz = 102.4 s 442 18.11 Program Examples of the 8-Bit Serial I/O Coding example EQU 0070H ;Address of serial mode register EQU 0071H ;Address of serial data register EQU SMR:7 ;Interrupt request flag bit definition EQU SMR:0 ;Serial I/O transfer start bit definition EQU 007DH ;Address of the interrupt level set register DSEG ABS ;[DATA SEGMENT] ORG 0FFE8H IRQ9 DW WARI ;Interrupt vector setting INT_V ENDS ;------Main program--------------------------------------------------------------CSEG ;[CODE SEGMENT] ;Assume stack pointer (SP), etc., ;have been already initialized. : CLRI ;Disable interrupts. CLRB SST ;Halt serial I/O transfer. MOV ILR3,#11110111B ;Set interrupt level (level 1). MOV SDR,#55H ;Set transfer data (55H). MOV SMR,#01111000B ;Clear interrupt request flag, enable output of interrupt requests, enable shift clock output (SCK2), enable serial data output (SO2), and select 32tinst, LSB-first. SETB SST ;Start serial I/O transfer. SETI ;Enable interrupts. : ;------Interrupt processing routine----------------------------------------------WARI CLRB SIOF ;Clear interrupt request flag. PUSHW A XCHW A,T ;Save A and T. PUSHW A MOV SDR,#55H ;Update transfer data (55H). SETB SST ;Start serial I/O transfer. : User processing : POPW A XCHW A,T ;Restore A and T. POPW A RETI ENDS ;--------------------------------------------------------------------------------END SMR SDR SIOF SST ILR3 INT_V 443 CHAPTER 18 8-BIT SERIAL I/O I Program Example for Serial Input Program specifications * * * Input 8 bits of serial data from the SI1 pin of the serial I/O and generate an interrupt when transfer is completed. In the interrupt processing routine, read the transfer data and re-enable input. Operate using the external shift clock and input the shift clock from the SCK pin. Coding example EQU 0011H ;Address of port direction register EQU 0070H ;Address of serial mode register EQU 0071H ;Address of serial data register EQU SMR:7 ;Interrupt request flag bit definition EQU SMR:0 ;Serial I/O transfer start bit definition EQU 007DH ;Address of the interrupt level set register DSEG ABS ;[DATA SEGMENT] ORG 0FFE8H IRQ9 DW WARI ;Interrupt vector setting INT_V ENDS ;------Main program--------------------------------------------------------------CSEG ;[CODE SEGMENT] ;Assume stack pointer (SP), etc., have been already initialized. : MOV DDR4,#00000000B ;Set P41/INT21/SCK2 and P43/INT23/SI2/SCL as inputs. CLRI ;Disable interrupts. CLRB SST ;Halt serial I/O transfer. MOV ILR3,#11110111B ;Set interrupt level (level 1). MOV SMR,#01001100B ;Clear interrupt request flag bit, enable output of interrupt requests, set shift clock input (SCK2), disable serial data output (SO2), and select the external clock, LSB-first. SETB SST ;Enable serial I/O transfer. SETI ;Enable interrupts. : ;------Interrupt processing routine----------------------------------------------WARI CLRB SIOF ;Clear interrupt request flag. PUSHW A XCHW A,T PUSHW A MOV A,SDR ;Read transfer data. SETB SST ;Enable serial I/O transfer. : User processing : POPW A XCHW A,T POPW A RETI ENDS ;--------------------------------------------------------------------------------END DDR4 SMR SDR SIOF SST ILR3 INT_V 444 CHAPTER 19 I2C INTERFACE This chapter describes the functions and operations of the I2C interface. 19.1 "Overview of the I2C Interface" 19.2 "Configuration of the I2C Interface" 19.3 "Configuration of the I2C Bus Interface" 19.4 "Registers of the I2C Bus Interface" 19.5 "I2C Interface Interrupts" 19.6 "Operation of the I2C Interface" 19.7 "Notes on Using the I2C Bus Interface" 19.8 "I2C Bus Interface Flowcharts" 19.9 "Program Example of the I2C Bus Interface" 445 CHAPTER 19 I2C INTERFACE 19.1 Overview of the I2C Interface The I2C interface that supports Philips's I2C bus specification and Intel's SM bus specification provides master/slave transmission and reception, arbitration lost detection, slave address/general call address detection, generation and detection of start/stop conditions, and buss error detection. I I2C interface Functions (for MB89PV530, MB89P538, MB89F538/F538L, MB89537C/538C, MB89537HC/538HC, MB89537AC/538AC only) The I2C bus interface is a simple structure bidirectional bus consisting of two wires: a serial data line (SDA) and a serial clock line (SCL). All devices connected to the serial bus must support open-drain or open-collector output and to connect a pull-up resistor with each bus line to operate. Each device connected to the bus has a unique address, which can be specified using software. Among these devices, there is always a master-slave relation. The master functions as a master transmission device. It is a full-fledged multi-master bus equipped with a collision detection function and communication adjustment procedure that prevent data corruption if two or more masters attempt to start data transfer simultaneously. Eight-bit bidirectional serial data can be transferred at a transfer rate of up to 100 kbps. As many ICs as required can be connected to one bus provided the upper limit of the bus capacitance (400 pF) is not exceeded. The I2C interface, which supports the Philips's I2C bus and Intel's system management bus, has the following functions: * * * * * * * * * * * * * Master and slave transmission and reception Automatic change from master to slave when arbitration lost detected Address comparison between slave and a general call Detection of data transfer direction Generation and detection of start/stop condition Generation and detection of continuous start condition Bus error detection Selection from 32 types of shift clock frequency by software Selection of acknowledge bit by software Generation and detection of acknowledge bit Byte-data transfer Noise canceller for input spikes up to 20 ns Selection of input buffer of I2C interface and SM bus interface 446 19.2 Configuration of the I2C Interface 19.2 Configuration of the I2C Interface The I2C interface consists of the following 10 blocks. * Clock controller (clock selector, clock divider, shift clock generator) * Start/stop condition generator * Start/stop condition detector * Arbitration lost detector * Slave address comparator * I2C bus status register (IBSR) * I2C bus control register (IBCR) * I2C clock control register (ICCR) * I2C address control register (IACR) * I2C address register (IADR) * I2C data register (IDAR) I I2C Bus Interface Block Diagram 447 CHAPTER 19 I2C INTERFACE Figure 19.2-1 Block Diagram of the I2C Bus Interface ICCR I2C enable Input buffer selection DMBP IBS 5 Clock divider 1 6 7 8 Peripheral clock EN CS4 CSL3 CSL2 CS1 CS0 IBSR Clock selector 2 Shift clock edge Bus busy Repeat start Last bit Start/stop condition detector Error First byte Arbitration lost detector Clock divider 2 8 16 32 64 128 256 512 1024 Sync Clock selector 1 Shift clock generator BB RSC LRB TRX FBT AL Internal data bus IBCR Transmission/ Reception BER BEIE INTE INT IBCR Start Master Enables ACK Enables GC-ACK End IRQ2 SCC MSS ACK GCAA IBSR Start/stop condition detector IDAR register Slave Slave address comparator SCL line SDA line IACR register AAS GCA General call IADR register 448 19.2 Configuration of the I2C Interface Clock controller (clock selector, clock divider, shift clock generator) This circuit selects and generates a shift clock of the I2C bus based on the internal clock. Start/stop condition generator When the bus is released (when the SCL and SDA lines are at a "H" level), transmitting a start condition causes the master to start communication. When the SDA line is changed from "H" to "L" when SCL = H, a start condition is generated. When a stop condition is generated, the master can stop communication. The stop condition is generated when the SDA line is changed from "L" to "H" when SCL = H. Start/stop condition detector This circuit detects the start/stop condition for data transfer. Arbitration lost detector This interface circuit supports the multi-master system. If two or more masters transmit data simultaneously, arbitration lost is generated. When logic level "1" is transmitted when the SDA line is at level "L", this state is regarded as arbitration lost. At this time, IBSR:AL is set to "1" and the master is changed into a slave. Slave address comparator After a start condition is posted, a slave address is transmitted. This address is seven-bit data, followed by a data direction bit (R/W) as bit 8. ACK is returned only to the slave whose address matches the transmitted address. I2C bus status register (IBSR) The IBSR register indicates the status of the I2C interface. This register is read-only. I2C bus control register (IBCR) The IBCR register is used to select the operating mode, enable/disable interrupts, enable/ disable acknowledgement, and enable/disable general call acknowledgement. I2C clock control register (ICCR) The ICCR register is used to permit the operation of the I2C interface and select the shift clock frequency. I2C address control register (IACR) The first three bits of the IACR register are effective. These bits are readable, but writable only when I2C is not operating. When 1 is written into these bits, the corresponding IADR bits are not compared. I2C address control register (IADR) The IADR register is used to set the slave address. I2C data register (IDAR) The IDAR register is used to transfer serial data from the MSB. While data is being received (IBSR:TRX = 0), the value of the data output is "1". 449 CHAPTER 19 I2C INTERFACE I I2C interface interrupt source IRQ2: An interrupt request is generated by the I2C interface when the bus error interrupt request bit is enabled (IBCR: BEIE = "1") and a bus error has occurred or when the transfer end interrupt enable bit is enabled (IBCR: INTE = "1") and data transfer is completed. 450 19.3 Configuration of the I2C Bus Interface 19.3 Configuration of the I2C Bus Interface This section describes the I2C bus interface pins, their block diagrams, registers, and interrupt function and provides a block diagram of the pins. I Pins Related to the I2C Bus Interface The pins related to the I2C bus interface are P42/INT22/SO2/SDA and P43/INT23/SI2/SCL. P42/INT22/SO2/SDA pin The P42/INT22/SO2/SDA pin can function as an N-ch open drain output port (P42) or data I/O pin (SDA). Enabling I2C automatically sets the P42/INT22/SO2/SDA pin as a data I/O pin. P43/INT23/SI2/SCL pin The P43/INT23/SI2/SCL pin can function as an N-ch open-drain output port (P43) or shift clock I/O pin (SCL). Enabling I2C automatically sets the P43/INT23/SI2/SCL pin as a shift clock I/O pin. I Noise canceller on P42/INT22/SO2/SDA and P43/INT23/SI2/SCL Noise cancellation is applied to the external signals of the P42/INT22/SO2/SDA and P43/INT23/ SI2/SCL pins before the internal interface circuit. Spikes of 20 ns or less are canceled. The noise canceller cannot be used while the DMBP bit of the ICCR is enabled (only for MB89PV530). 451 CHAPTER 19 I2C INTERFACE I Block diagram of pins related to the I2C bus interface Figure 19.3-1 Block Diagram of Pins Related to I2C Bus Interface To external interrupt circuit Stop/watch mode (SPL = 1) External interrupt enable To peripheral resource input Internal data bus PDR (port data register) Stop/watch mode (SPL = 1) PDR read Peripheral resource output(*1) PDR read (for bit manipulation instructions) Output latch PDR write Pin Nch P42/INT22/SO2/SDA P43/INT23/SI2/SCL Stop/watch mode (SPL = 1) SPL : Pin status specification bit of standby control register (STBC) *1 P42 is connected to two peripheral resource outputs. P43 is connected to one peripheral resource output. 452 19.4 Registers of the I2C Bus Interface 19.4 Registers of the I2C Bus Interface This section shows the registers related to the I2C bus interface. I Registers Related to I2C Bus Interface Figure 19.4-1 Registers Related to I2C Bus Interface IACR (I2C address control register) Address 0 0 50 H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value -----000B SAC2 SAC1 SAC0 R/W R/W R/W IBSR (I2C bus status register) Address 0 0 51 H bit7 BB R IBCR (I2C bus control register) Address 0 0 52 H bit7 BER R/W ICCR (I2C clock control register) Address 0 0 53 H bit7 DMBP R/W IADR (I2C address register) Address 0 0 54 H bit7 bit6 A6 R/W IDAR (I2C data register) Address 0 0 55 H bit7 D7 R/W R/W : R: : X: Read/write enabled Read only Not used Undefined bit6 D6 R/W bit5 D5 R/W bit4 D4 R/W bit3 D3 R/W bit2 D2 R/W bit1 D1 R/W bit0 D0 R/W Initial value XXXXXXXXB bit5 A5 R/W bit4 A4 R/W bit3 A3 R/W bit2 A2 R/W bit1 A1 R/W bit0 A0 R/W Initial value -XXXXXXXB bit6 IBS R/W bit5 EN R/W bit4 CS4 R/W bit3 CS3 R/W bit2 CS2 R/W bit1 CS1 R/W bit0 CS0 R/W Initial value 000XXXXXB bit6 BEIE R/W bit5 SCC R/W bit4 MSS R/W bit3 ACK R/W bit2 bit1 bit0 INT R/W Initial value 00000000B bit6 RSC R bit5 AL R bit4 LRB R bit3 TRX R bit2 AAS R bit1 GCA R bit0 FBT R Initial value 00000000B GCAA INTE R/W R/W 453 CHAPTER 19 I2C INTERFACE 19.4.1 I2C Address Control Register (IACR) The I2C address control register (IACR) indicates the state of the interface. I I2C address control register (IACR) Figure 19.4-2 I2C Address Control Register (IACR) Address 0050H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value -----000B SAC2 SAC1 SAC0 R/W R/W R/W SAC0 0 1 SAC1 0 1 SAC2 0 1 Bit 0 No effect on any other registers Bit 0 cannot be handled by the slave address comparator. Bit 1 No effect on any other registers Bit 1 cannot be handled by the slave address comparator. Bit 2 No effect on any other registers Bit 2 cannot be handled by the slave address comparator. R/W : Read/Write enabled : Unused : Initial value 454 19.4 Registers of the I2C Bus Interface Table 19.4-1 Description of the I2C Address Control Register (IACR) Bits Bit bit7 bit6 bit5 bit4 bit3 Description Unused * * Values read are undefined. Writing has no effect on the operation. * * bit2 SAC2 Writing 0 into this bit has no effect on the operation. Setting 1 to this bit makes the sleep address comparator ignore bit 2 of the I2C address register (IADR). When the other IADR bits contain an address code which is the same as that sent from the master chip, it is assumed that the address codes match. Writing 0 into this bit has no effect on the operation. Setting 1 to this bit makes the sleep address comparator ignore bit 1 of the I2C address register (IADR). When the other IADR bits contain an address code which is the same as that sent from the master chip, it is assumed that the address codes match. Writing 0 into this bit has no effect on the operation. Setting 1 to this bit makes the sleep address comparator ignore bit 0 of the I2C address register (IADR). When the other IADR bits contain an address code which is the same as that sent from the master chip, it is assumed that the address codes match. * * bit1 SAC1 * * bit0 SAC0 455 CHAPTER 19 I2C INTERFACE 19.4.2 I2C Bus Status Register (IBSR) The IBSR register indicates the status of the interface. I I2C Bus Status Register (IBSR) Figure 19.4-3 I2C Bus Status Register (IBSR) Address 0051H bit7 BB R bit6 RSC R bit5 AL R bit4 LRB R bit3 TRX R bit2 AAS R bit1 GCA R bit0 FBT R Initial value 00000000B FBT 0 1 GCA 0 1 AAS 0 1 TRX 0 1 LRB 0 1 AL 0 1 First byte detection bit The received data is a byte other than the first byte when data is received The received data is the first byte (address data) when data is received General call address detection bit In slave mode, the general call address is not received In slave mode, the general call address is received Addressing detection bit The specific address calling address did not match in slave mode. The specific address calling address matched in slave mode. Data transfer state bit Reception mode Transmission mode Last received bit An acknowledge was detected in the ninth clock. An acknowledge has not been detected in the ninth clock. Arbitration lost bit Arbitration lost is not detected Arbitration lost is generated while the master is transmitting data or "1" is written to the IBCR: MSS bit when another system is using the bus Repeated start condition detection bit Repeated start condition is not detected Start condition is detected again when the bus is in use Bus busy bit Stop condition is detected Start condition is detected (The bus is in use.) RSC 0 1 BB 0 1 R/W : Read only : Initial value 456 19.4 Registers of the I2C Bus Interface Table 19.4-2 Functions of Each Bit in I2C Bus Status Register (IBSR) Bit name Bit 7 BB: Bus busy bit * * * RSC: Repeated start condition detection bit Function This bit indicates the state of the bus. This bit is cleared when a stop condition is detected and set when a start condition is detected. This bit detects the repeated start condition. (RSC=1) This bit is set when a start condition is detected and cleared in the following state. "0" is written to the IBCR: INT bit This bit is not addressed in slave mode. A start condition is detected during bus stop A stop condition is detected Bit 6 1. 2. 3. 4. * Bit 5 AL: Arbitration lost bit This bit detects arbitration lost. This bit is set in the following states. 1. Arbitration lost is detected when the master is transmitting data 2. "1" is written to the IBCR: MSS bit when another system is using the bus * This bit is also cleared when "0" is written to the IBCR: INT bit * This bit stores the SDA line value of the 9th clock when the data byte is transferred. Cleared when an acknowledge bit is detected. (SDA = L) Set when an acknowledge bit is not detected. (SDA = H) Cleared with "0" when a start or stop condition is detected. This bit indicates whether the data transfer is performed in the transmission mode or the reception mode. This bit indicates addressing is performed in slave mode. This bit is set when addressing is performed in slave mode and cleared when a start or stop condition is detected. This bit detects a general call address. If this bit is set to "1" in slave mode, the general call address (00H) is received. This bit is cleared when a start or stop condition is detected. This bit detects the first byte This bit is always set to "1" in the start condition. This bit is set to "1" when a start condition is detected and cleared when "0" is written to the IBCR:INT bit or when this bit is not addressed in slave mode. Bit 4 LRB: Acknowledge storage bit * * * * * * Bit 3 TRX: Data transfer state bit AAS: Addressing detection bit Bit 2 Bit 1 GCA: General call address detection bit * * * * * * Bit 0 FBT: First byte detection bit 457 CHAPTER 19 I2C INTERFACE 19.4.3 I2C Bus Control Register (IBCR) The IBCR register is used to select the operating mode, enables/disables interrupts, enables/disables acknowledge, and enables/disables general call acknowledge. I I2C Bus Control Register (IBCR) Figure 19.4-4 I2C Bus Control Register (IBCR) Address 0052H bit7 BER R/W bit6 BEIE R/W bit5 SCC R/W bit4 MSS R/W bit3 bit2 bit1 bit0 INT R/W Initial value 00000000B ACK GCAA INTE R/W R/W R/W INT Transfer end interrupt request flag bit Read Data transfer not completed One byte data transfer including acknowledge of the ninth clock completed Interrupt request enable bit Disables interrupt request output Enables interrupt request output General call address acknowledge generation enable bit Acknowledge is not generated Acknowledge is generated Data acknowledge generation enable bit Acknowledge is not generated Acknowledge is generated Master/slave selection bit Selects slave mode Selects master mode Start condition generation bit Read Always 0 Write No change Generates repeated start condition in master mode. Clear No change Write 0 1 INTE 0 1 GCAA 0 1 ACK 0 1 MSS 0 1 SCC 0 1 BEIE Bus error interrupt request enable bit Disables bus error interrupt request output Enables bus error interrupt request output Bus error interrupt request bit Read No bus error An illegal start or stop condition is detected Clear No change Write 0 1 BER 0 1 R/W : Read/write enabled : Initial value 458 19.4 Registers of the I2C Bus Interface Table 19.4-3 Functions of Each Bit in I2C Bus Control Register (IBCR) Bit name * * * * * * Function This bit clears a bus error interrupt and detects a bus error. When a bus error is detected, "0" is written and the bus error interrupt is cleared. When "1" is written, there is no change and no effect on others. When an illegal start or stop condition is detected during data transfer, this bit is set. When this bit is set, the I2C bus interface enable bit in the ICCR register (ICCR:EN) is cleared, the I2C bus interface enters stop mode, and data transfer is terminated. This bit enables (BEIE = 1) or disables (BEIE = 0) the generation of a bus error interrupt request. When this bit is set and BER = 1, an interrupt request is sent to the CPU. Bit 7 BER: Bus error interrupt request flag bit Bit 6 BEIE: Bus error interrupt request enable bit * * * Bit 5 SCC: Start condition generation bit When this bit is set, a repeated start condition in master mode is generated. (SCC = 1) * No change when "0" is written. * The read value of this bit is always "0". Note: * Do not write SCC = 1 and MSS = 0 simultaneously. * If "1" is written to SCC when INT = 0, setting the SCC bit to "1" has the higher priority, and a start condition is generated. * This bit selects the slave mode (MSS = 0) or the master mode (MSS = 1). * When this bit is cleared to "0", a stop condition is generated and the master mode is switched to the slave mode after transfer is completed. * When this bit is set to "1", the slave mode is switched to the master mode, a start condition is generated, and transfer is started. * If arbitration lost is generated when the master is transmitting data, this bit is cleared and the master mode is switched to the slave mode. Note: * Do not write SCC = 1 and MSS = 0 simultaneously. * If "0" is written to MSS when INT = 0, "0" in the MSS bit has a higher priority and a stop condition is generated. * * * This bit enables or disables the output of the acknowledge bit in the 9th clock at data reception. This bit is disabled while address data is received in slave mode. Moreover, acknowledge is sent during addressing. This bit permits output of the general call address acknowledge bit during reception in slave mode. Bit 4 MSS: Master/slave selection bit Bit 3 ACK: Data acknowledge generation enable bit GCAA: General call address acknowledge generation enable bit Bit 2 459 CHAPTER 19 I2C INTERFACE Table 19.4-3 Functions of Each Bit in I2C Bus Control Register (IBCR) (Continued) Bit name INTE: Transfer end interrupt request enable bit * * * Function This bit selects whether an interrupt at the end of transfer is enabled (INTE = 1) or disabled (INTE = 0). When this bit is set and INT is set to "1", a transfer end interrupt request is sent to the CPU. Bit 1 Bit 0 INT: Transfer end interrupt request flag bit With this bit, the data transfer end interrupt request flag can be cleared. In addition, it can be determined whether the interrupt is detected. * When "0" is written, the transfer end interrupt request flag is cleared. When "1" is written, no change occurs. * If any of the following five conditions is met when one byte transfer including the acknowledge bit is completed (including the acknowledge bit in the 9th clock), this bit is set to "1". 1. Bus master mode 2. The calling address matches the slave address 3. A general call address is received 4. Arbitration lost is generated 5. An attempt was made to generate a start condition while another system was using the bus * When this bit is set to "1", the SCL line is kept at the "L" level. This bit is cleared when "0" is written to this bit. At this time, this macro releases the SCL line and transfers the next byte. * This bit is also cleared to "0" when a start or stop condition is generated in master mode. Note: * If "1" is written to SCC when INT = 0, "1" in the SCC bit has a higher priority and a start condition is generated. * If "0" is written to MSS when INT = 0, "0" in the MSS bit has a higher priority and the stop condition is generated. 460 19.4 Registers of the I2C Bus Interface 19.4.4 I2C Clock Control Register (ICCR) The ICCR register is used to permit the operation of the I2C and select the shift clock frequency. I I2C Clock Control Register (ICCR) Figure 19.4-5 I2C Clock Control Register (ICCR) Address 0053H bit7 bit6 bit5 EN R/W bit4 CS4 R/W bit3 CS3 R/W bit2 CS2 R/W bit1 CS1 R/W bit0 CS0 R/W Initial value 000XXXXXB DMBP IBS R/W R/W Clock 2 selection bit CS2 CS1 CS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Divider n 4 8 16 32 64 128 256 512 Clock 1 selection bit CS4 CS3 0 0 1 1 EN 0 1 IBS 0 1 DMBP Divider m 5 6 7 8 I2C operation enable bit 0 1 0 1 Disables I2C operation Enables I2C operation Input buffer selection bit System management bus input buffer I2C interface input buffer Divider m bypass bit Bypass prohibited Bypass divider m 0 1 R/W : Read/write enabled X : Undefined : Initial value 461 CHAPTER 19 I2C INTERFACE Table 19.4-4 Functions of Each Bit in I2C Clock Control Register (ICCR) Bit name * * Bit 7 DMBP: Divider m bypass bit * * * * Bit 6 IBS: Input buffer selection bit * * * * Bit 5 EN: Multi-address I2C operation permission bit * * * * * Function This bit is used to bypass the m divider for generating a shift clock frequency. When "0" is written, the value set in CS3 and CS4 becomes the value of the m divider. When "1" is written, the m divider is bypassed. This is equivalent to m = 1. In read cycle, the present set value can be read. When n = 8 (CS2 = CS1 = CS0 = 0), do not set this bit. This bit is used to select the characteristics of the input buffer. Writing 0 selects the system management bus input buffer. Writing 1 selects the I2C input buffer. The current value is read from this bit. This bit permits the operation of the multi-address I2C interface (EN = "1"). When the bit is "0", each bit of the IBSR and IBCR registers (excluding BER and BEIE bits) is cleared to "0". When the IBCR:BER bit is set, the bit is cleared. This bit must be enabled to write all the I2C registers. This bit sets shift clock frequency. Shift clock frequency Fsck is determined by the following formula. Bit 4 Bit 3 CS4, CS3: Clock 1 selection bit Fsck = Bit 2 Bit 1 Bit 0 CS2, CS1, CS0: Clock 2 selection bit 2Finst m x n +4 Where, tinst is an instruction cycle (the clock in the SYCC selected by the CS bit). When DMBP is "0", m is selected by CS4 and CS3. When DMBP is "1," m is "1." n is selected by CS2, CS1, and CS0. Note: The I2C interface described in this section is an I2C bus of the standard mode. Therefore, a shift clock frequency of up to 100 KHz can be set. 462 19.4 Registers of the I2C Bus Interface 19.4.5 I2C Address Register (IADR) The IADR register is used to set the slave address. I I2C Address Register (IADR) Figure 19.4-6 I2C Address Register (IADR) Address 0054H bit7 bit6 A6 R/W R/W : Read/write enabled X : Undefined bit5 A5 R/W bit4 A4 R/W bit3 A3 R/W bit2 A2 R/W bit1 A1 R/W bit0 A0 R/W Initial value -XXXXXXXB In slave mode only, this register specifies a valid slave address. The address consists of 7 bits. The master sends the address using 8 bits by adding a R/W bit to its end. In slave mode, after the reception of an address sent from the master, values in the lower 7 bits of the IDAR register are compared with those of this register to judge the addressing. 463 CHAPTER 19 I2C INTERFACE 19.4.6 I2C Data Register (IDAR) The IDAR register is used to set transmission data and to store received data. I I2C Data Register (IDAR) Figure 19.4-7 I2C Data Register (IDAR) Address 0055H bit7 D7 R/W R/W : Read/write enabled X : Undefined bit6 D6 R/W bit5 D5 R/W bit4 D4 R/W bit3 D3 R/W bit2 D2 R/W bit1 D1 R/W bit0 D0 R/W Initial value XXXXXXXXB In master mode, the data written in the register is shifted to the SDA line bit by bit from the MSB bit. The write side in this register is made up of a double buffer. When the bus is in use (IBSR: BB = 1), written data is loaded to the eight-bit shift register when the transfer of the present byte is completed. The data in the shift register is shifted and output to the SDA line bit by bit. The value written to this register has no effect on the present data transfer. Also in slave mode, the same function can be used after the address is determined. When IBCR: INT = 1 at data reception (IBSR: TRX = 0), the received data can be read from this register. In other cases, "FFH" is always read from this register. During data transfer (IBSR:TRX = 1), however, the value of the shift register can be read from the IDAR register. 464 19.5 I2C Interface Interrupts 19.5 I2C Interface Interrupts The I2C interface may generate an interrupt request when the data transfer is completed, a bus error has occurred, or a timeout is detected. I Interrupt at Bus Error When the following conditions are met, a bus error is assumed to have occurred and the I2C interface is stopped. * * * * When a violation of an I2C bus standard definition is detected during data transfer (including transfer of the ACK bit). When a violation of an I2C bus standard definition is detected while the bus is idle. When the SCL line is set to the "L" level at the time a start condition is generated. When a retransmission start condition is detected (IBSR:RSC = 1) in bus master mode. If the bus error interrupt request enable bit is enabled (IBCR:BEIE = 1) at this time, an interrupt request is output to the CPU. Clear the interrupt request by writing "0" to the IBCR:BER bit in the interrupt processing routine. If a bus error has occurred in spite of the IBCR:BEIE bit value, the BER bit is set to "1". I Interrupt at Data Transfer Completion The I2C interface is used to transmit data to and receive data from the SDA line one bit at a time. One data byte is defined to always consist of eight bits. Data can be changed only while the SCL is set to "L." While the SCL is set to "H," the data must be stabilized. One clock pulse transfers 1 bit of data, starting with the MSB. A byte of data must arrive after the SDA line is pulled down at the 9th clock and an acknowledge signal has been received from the receiving device. That is, nine clock pulses are required to completely transfer one byte of data. When data transfer is completed and the transfer end interrupt request enable bit is enabled (IBCR: INTE = 1), an interrupt request (IRQ2) is output to the CPU. Clear the interrupt request by writing "0" to the INT bit in the interrupt processing routine. If data transfer is completed in spite of the INTE bit value, the INT bit is set to "1". I Register and Vector Table Address Related to Interrupt of I2C Interface Table 19.5-1 "Register and Vector Table Address Related to Interrupt of I2C Interface" shows the register and vector table for I2C interface interrupts. Table 19.5-1 Register and Vector Table Address Related to Interrupt of I2C Interface Interrupt name IRQ2 Interrupt level setting register Register ILR1 (007BH) Bit to be set L21 (bit 5) L20 (bit 4) Vector table address Upper FFF6H Lower FFF7H For interrupt operation, see Section 3.4.2 "Interrupt Processing". 465 CHAPTER 19 I2C INTERFACE 19.6 Operation of the I2C Interface The I2C interface is a serial data base of 8-bit data synchronized with the shift clock. I I2C Bus System The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) to transfer data. All connected devices require an open-drain or open collector output. The logic function is used by connecting a pull-up resistor. Each device connected to the bus has a unique address and can be set by software. Among the devices, simple master/slave relations are established and master devices function as master transmitters or master receivers. The I2C interface is a full-fledged multi-master bus equipped with collision detection and arbitration functions so that data destruction can be prevented even if two or more masters attempt to start data transfer simultaneously. I I2C Bus Protocol Figure 19.6-1 "Data Transfer Example" shows the format required for data transfer. Figure 19.6-1 Data Transfer Example MSB SDA SCL Start condition 7-bit address R/W Acknowledge bit Stop 8-bit address condition No acknowledge LSB MSB LSB After a start condition (S) is generated, a slave address is transmitted. This address is a sevenbit address followed by a data direction bit (R/W) as bit 8. Data transfer is always ended with the master stop condition (P). It is also possible to address to another slave without generating a stop condition by generating a repeated start condition (Sr). I Start Condition While the bus is released (both the SCL and SDA lines are "H"), the master generates a start condition to start transmission. As indicated in Figure 19.6-1, changing the SDA line state from "H" to "L" while SCL is "H" generates a start condition, then a start of transmission (hereinafter referred to as "bus busy") is posted to devices connected to the bus. The two methods for generating a start condition are shown as follows. * Writing "1" to the IBCR: MSS bit in states where the I2C bus is not used (IBCR: MSS = 0, IBSR: BB = 0, IBCR: INT = 0, IBSR: AL = 0). Thereafter, IBSR: BB is set to "1" to indicate bus busy. Writing "1" to the IBCR: SCC bit in interrupt states in bus master mode (IBCR: MSS = 1, IBSR: BB = 1, IBCR: INT = 1, IBSR: AL = 0) and generates a repeated start condition. * Even if "1" is written to the IBCR:MSS bit or "1" is written to the IBCR:SCC bit under conditions other than the above, it is ignored. If "1" is written to the IBCR:MSS bit while another system is 466 19.6 Operation of the I2C Interface using the bus (in the idle state), the IBSR:AL bit is set to "1". I Addressing Addressing in master mode In master mode, after the start condition is generated, "1" is set to IBSR:BB and "1" is set to IBSR:TRX. Then, the address data in the IDAR register (IDAR:D7 to D1) is output from the MSB. This address data consists of 8 bits: 7 bits for the slave address and 1 R/W bit (IDAR:DO) for indicating the direction of data transmission. After the address data is transmitted, the master receives an acknowledgement from the slave (the SDA line is set to "L" by the 9th clock, the master receives the acknowledgement bit from the receiving device), and then reverses bit 0 of the received data (IDAR:DO after transmission) and stores it in the IBSR:TRX bit. Addressing in slave mode In slave mode, the BB and TRX bits in the IBSR register are set to "1" and "0," respectively, after a start condition is detected and data from the master is received by the IDAR register. After receiving the address data, the IDAR and IADR registers are compared. If the values match, IBSR:AAS is set to "1" and an acknowledgement is sent to the master. Thereafter, bit 0 of the received data (IDAR:DO after reception) is stored in the IBSR:TRX bit. I Data Transfer After addressing of a slave has been completed, data can be transmitted and received in byte units in the direction determined by the R/W bit sent by the master. Each byte output to the SDA line is fixed to 8 bits. As shown in Figure 19.6-1 "Data Transfer Example", data (SDA line) is changeable only when the SCL line is at Level L. While the SCL line is at H, the state must be stable. With the MSB at the head, each bit of data is transmitted with one clock pulse. Each byte has an acknowledgement bit (the SDA line is set to "L" by the 9th clock and the master receives the acknowledgement from the receiving device). Therefore, 9 clock pulses are required to transfer one complete data byte. I Acknowledge Acknowledge is transmitted from the receiving end for the 9th clock of data byte transfer from the transmitting end. When data is received, the IBCR:ACK bit is used to enable or disable acknowledgement. When data is transmitted, acknowledgement from a receiving end is stored into the IBSR:LRB bit. Upon transmission from a slave, if no acknowledgement is received from the master, 0 is set to IBSR:TRX, and then the slave enters reception mode. The master can generate a stop condition when the slave releases the SCL line or repeatedly generates a start condition. I Stop Condition By generating a stop condition, the master can release the bus to terminate communication. A stop condition can be generated by changing the SDA line from "L" to "H" when the SCL line is at the "H" level. The master can generate start conditions continuously without generating a stop condition. This is called the repeated start condition. In bus master mode, a stop condition is generated by writing "0" to the IBCR: MSS bit in the interrupt state (IBCR: MSS = 1, IBSR: BB = 1, IBCR: INT = 1, IBSR: AL = 0) and the master mode is switched to the slave mode. 467 CHAPTER 19 I2C INTERFACE Even if "0" is written to the IBCR: MSS bit in other the above, it is ignored. I Arbitration This interface circuit is a full-fledged multi-master bus that can connect two or more masters. If a master transfers data and another master transfers data simultaneously, an arbitration is generated. An arbitration occurs in the SDA line when the SCL line is at the "H" level. The master recognizes the occurrence of an arbitration lost when its transmission data is "1" and data on the SDA line is at the "L" level, and then it sets data output to off and sets the IBSR: AL bit to "1". When the IBSR: AL is set to "1", "0" is written to IBCR: MSS and IBSR: TRX. As a result, the TRX is cleared and the master mode is switched to the slave reception mode. Note: When the bus is used as described above, an attempt to generate a start condition sets IBSR:AL to 1. However, IBCR:MSS is set to 1. 468 19.7 Notes on Using the I2C Bus Interface 19.7 Notes on Using the I2C Bus Interface This section describes precautions to take when using the I2C bus interface. I Notes on Using the I2C Bus Interface Precaution in Setting the I2C Bus Interface Register * * Before writing to the bus control register (IBCR), the I2C interface must be enabled (ICCR: EN). When the master slave selection bit (IBCR: MSS) is set, transfer starts. Precaution in Setting the Shift Clock Frequency * To calculate the shift clock frequency using the Fsck expression (1) in Table 19.4-4 "Functions of Each Bit in I2C Clock Control Register (ICCR)", it is necessary to know the values of m, n, and DMBP. * When m is 5 (ICCR:CS4 = CS3 = 0) and n is 8 (ICCR:CS2 = CS1 = CS0 = 0), the DMBP value cannot be selected. Other combinations do not present a problem. Precautions Related to Priority when Contention Occurs during Transfer of the Next Byte, Occurrence of a Start Condition, and Occurrence of a Stop Condition * Contention of the next byte transfer and stop condition When "0" is written to IBCR: MSS in states where IBCR: INT is cleared, the MSS bit has a higher priority and a stop condition is generated. * Contention of the next byte transfer and start condition When "1" is written to IBCR: SCC in states where IBCR: INT is cleared, the SCC bit has a higher priority and a start condition is generated. Precaution on Setting with Software * * Do not select the repeated start condition (IBCR: EN = 0) and the slave mode (IBCR: MSS = 0) at the same time. In those states in which the interrupt request flag bits (BER and INT in the IBCR register) are set to "11B" and the interrupt request enable bits are enabled (BEIE and INTE in the IBCR register are set to "11B"), recovery from interrupt processing is not possible. Clear the BER and INT bits in the IBCR register. When I2C operation is not permitted (ICCR:EN = 0), all the bits of the bus status register IBSR and the bus control register IBCR (excluding the bus error BER bit and the bus error enable BEIE bit) are cleared. * 469 CHAPTER 19 I2C INTERFACE Input buffer selection (for other than MB89567A) This I2C interface can support the I2C bus and SM bus. Therefore, select an appropriate input buffer characteristics depending on the bus interface system to be used. The characteristics of this input buffer can be selected by using the IBS bit of the ICCR register. Specifying 0 for the bit sets the SM bus, while specifying 1 sets the I2C bus. 470 19.8 I2C Bus Interface Flowcharts 19.8 I2C Bus Interface Flowcharts This section provides sample operation flowcharts for the I2C bus interface. I Sample flowchart of an I2C master transmission/reception program Main routine Start Set a slave address Enable operation of example of I2C Is the master performing transmission? Interrupt routine Start Has a bus error Yes occurred? No Has AL been generated? No Master receiving Set the number of bytes of data to be received Receive the set slave address (data direction bit = 1) Is it the master? Yes No 3 3 2 1 A stop condition is generated RETI 3 Enable generation of an acknowledgement To the routine for interrupting the slave program 2 Clear the cause of bus error interrupt Enable operation of I2C Specify initial I2C settings RETI Yes Master transmitting No Set the number of bytes of data to be transmitted Send the set slave address (data direction bit = 0) Has ACK been returned? Yes No 1 Yes BBbit = 1? Yes BBbit=1? Has 1 No been set in data direction bit TRX? Is the number of remaining bytes to be received 0? Yes 1 No Sending the slave address generates a start condition Wait for the specified time Is 0 set in BBbit and 1 in Albit? No Sending the slave address generates a start condition Wait for the specified time Is 0 set in BBbit and 1 in Albit? Yes Is the Yes number of remaining bytes to be transmitted 0? No 1 Is the number of remaining bytes to be received 1? Yes Yes Disable the operation of I2C Yes Disable the operation of I2C No Reduce the number of bytes to be transmitted Set the data to be transmitted Clear the cause of transmission end interrupt RETI No Enable generation of an acknowledgement Disable generation of acknowledgement No LOOP No LOOP Is the received byte the first byte? Yes No Reduce the number of bytes to be received Store the received data into RAM Clear the cause of transmission end interrupt RETI 471 CHAPTER 19 I2C INTERFACE I Sample flowchart of an I2C slave transmission/reception program Main routine Start Set the slave address Enable operation of I2C Set slave mode LOOP Interrupt routine Start YES Has a bus error occurred? 1 Clear the cause of transmission end interrupt 2 Clear the cause of bus error interrupt Enable operation of I2C Specify initial I2C settings 2 No Has it been addressed? No RETI 1 Yes Is 1 set in data direction bit TRX? No Is the received data an address? RETI Yes Has ACK been returned? No Yes 1 Yes Set the data to be transmitted Clear the cause of transmission end interrupt No Store the received data into RAM Clear the cause of transmission end interrupt RETI RETI 472 19.9 Program Example of I2C Bus Interface 19.9 Program Example of the I2C Bus Interface This section shows a sample program for the I2C bus interface. I Program Example for Master Transfer Mode Processing specifications * * * * * Transfer rate: 100kbps Use of a buffer with input features that support the SM bus Setting in master transfer mode Data (64H) transmission to the slave at address 19H The following equation shows the m and n values of the ICCR register required to set the serial transfer rate (Fsck) at about 100 kbps when the oscillation frequency (Fc) is 10MHz. Fsck = 2Finst = mxn+4 2(10 MHz/2/2) = 100 kbps 6x8+4 Finst = 1/tinst x 10 MHz/2/2=2.5 MHz m is selected by CS4 and CS3 of the ICCR register. n is selected by CS2, CS1, and CS0 of the ICCR register. m x n = 5 MHz/100 KHz - 4 = 46 (app. 6 x 8) The ICCR register value (bits 4 to 0) is 01000B and ICCR:DMBP (bit 7) is set to 0B. 473 CHAPTER 19 I2C INTERFACE Coding example IBSR IBCR ICCR IADR IDAR EN BER INT ILR1 INT_V EQU EQU EQU EQU EQU EQU EQU EQU 0051H 0052H 0053H 0054H 0055H ICCR:5 IBCR:7 IBCR:0 ;Address of the I2C bus status register ;Address of the I2C bus control register ;Address of the I2C clock control register ;I2C address register ;I2C data register ;Define the I2C bus interface enable bit. ;Definition of the bus error interrupt request flag bit ;Definition of the transfer end interrupt request flag bit ;Address of the interrupt level setting register ;[DATA SEGMENT] EQU 007BH DSEG ABS ORG OFFF6H IRQ2 DW WARI ;Interrupt vector setting INT_V ENDS ;---------Main program------------------------------------------------------------CSEG ;[CODE SEGMENT] ;Assume that the stack pointer (SP) and other necessary elements have already been initialized. : CLRI ;Disables interrupts. SETB MOV MOV SETI MOV MOV MOV STA_CON MOV EN ILR1,#11011111B ICCR,#028H ;Enable I2C operation. ;Set the interrupt level (level 1). ;Enable I2C operation and select 100 kHz for the shift clock frequency. ;Enables interrupts. ;Set the local address to B2H. ;Transfer the calling address as 19H and SET R/W permission to write. ;Enable the interrupt request flag, set master mode, and enable acknowledge. ;Wait for generation of a start condition and end transfer of the first byte. ; ; ; ;Transfer 64H as data. IADR,#10110010B IDAR,#00110010B IBCR,#01011110B A,#01110110B OR A,IBSR CMP A,#11111111B BNZ STA_CON MOV IDAR,#01100100B : ;---------Interrupt program-------------------------------------------------------WARI BBS IBCR:7,BE_INT ;Check the bus error interrupt request flag. BBS IBCR:0,DTC_INT ;Transfer end interrupt request flag BE_INT CLRB BER ;Clear the bus error interrupt request flag. PUSHW A XCHW A,T ;Save A and T. PUSHW A : User processing : JMP WARI_F DTC_INT CLRB INT ;Clear the data transfer end interrupt request flag. PUSHW A XCHW A,T ;Save A and T. PUSHW A : WARI_F POPW A XCHW A,AT ;Restore A and T. POPW A RETI ENDS ;---------------------------------------------------------------------------------END 474 CHAPTER 20 WILD REGISTER FUNCTION This chapter describes the functions and operations of the wild register function. 20.1 "Overview of the Wild Register Function" 20.2 "Configuration of the Wild Register Function" 20.3 "Registers of the Wild Register Function" 20.4 "Operation of the Wild Register Function" 20.5 "General Hardware Connections" 475 CHAPTER 20 WILD REGISTER FUNCTION 20.1 Overview of the Wild Register Function The wild register includes a combination of a 6-byte data register, a 6-byte upper address register, a 6-byte lower address register, a 1-byte data enable register, and a 1-byte data test register. The wild register has many functions, but its main function is to replace ROM codes in the ROM space. This section describes the functions of the wild register. I Wild Register Function The wild register consists of a combination of a 6-byte data register, a 6-byte upper address register, a 6-byte lower address register, a 1-byte data enable register, and a 1-byte data test register. Data in the ROM space can be replaced with arbitrary data in these registers by specifying the data and address for replacement. Data of up to six bytes can be allocated to the six data registers. Up to six addresses can be allocated to the six upper address registers and six lower address registers. Using the wild register function, you can debug a program and apply a patch to a faulty location after masking. You can also replace any ROM code in the ROM space and search tables according to settings by other applications. The settings of the wild register are made employing a specialized communication method via a device. Note: The functions of the wild register cannot be debugged by a tool. Use the MB89P568 to check wild register operation on an actual machine. 476 20.2 Configuration of the Wild Register Function 20.2 Configuration of the Wild Register Function The wild register function consists of the following two blocks: * Wild register data setting registers (WRDR1 to WRDR6) * Wild register upper address setting registers (WRARH1 to WRARH6) * Wild register lower address setting registers (WRARL1 to WRARL6) * Wild register enable register (WREN) * Wild register data test register (WROR) * Wild register comparison circuit and logic control circuit I Block Diagram of the Wild Register Function Figure 20.2-1 Block Diagram of the Wild Register Function Internal ROM Wild register function Control circuit section Access control circuit Decoder and logic control circuit Address comparison circuit Wild register upper address setting register Internal bus Wild register lower address setting register Access control circuit Wild register data setting register Wild register enable register Wild register data test register Memory space 477 CHAPTER 20 WILD REGISTER FUNCTION 20.3 Registers of the Wild Register Function This section describes the registers related to the wild register function. I Registers Related to the Wild Register Function Figure 20.3-1 Registers Related to the Wild Register Function Wild register data setting register (WRDR1 to WRDR6) Address 0 C 8 2H 0 C 8 5H 0 C 8 8H 0 C 8 BH 0 C 8 EH 0 C 9 1H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB Wild register upper address setting register (WRARH1 to WRARH6) Address 0 C 8 0H 0 C 8 3H 0 C 8 6H 0 C 8 9H 0 C 8 CH 0 C 8 FH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value RA15 RA14 RA13 RA12 RA11 RA10 RA09 RA08 R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB Wild register lower address setting register (WRARL1 to WRARL6) Address 0 C 8 1H 0 C 8 4H 0 C 8 7H 0 C 8 AH 0 C 8 DH 0 C 9 0H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value RA07 RA06 RA05 RA04 RA03 RA02 RA01 RA00 R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB Wild register enable register (WREN) Address 0 0 7 7H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value EN05 EN04 EN03 EN02 EN01 EN00 R/W R/W R/W R/W R/W R/W --000000B Wild register data test register (WROR) Address 0 0 7 8H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value DRR5 DRR4 DRR3 DRR2 DRR1 DRR0 R/W R/W R/W R/W R/W R/W --000000B R/W : R: : X: Read/write enabled Read-only enabled Not used Undefined 478 20.3 Registers of the Wild Register Function 20.3.1 Data Setting Registers (WRDR1 to WRDR6) The data setting registers (WRDR1 to WRDR6) contain correction data to be set using the wild register function. I Data Setting Registers (WRDR1 to WRDR6) Figure 20.3-2 Setting Data Registers (WRDR1 to WRDR6) WRDR1 Address 0C82H bit7 RD07 R/W bit6 RD06 R/W bit5 RD05 R/W bit4 RD04 R/W bit3 RD03 R/W bit2 RD02 R/W bit1 RD01 R/W bit0 RD00 R/W Initial value XXXXXXXXB WRDR2 Address 0C85H bit7 RD07 R/W bit6 RD06 R/W bit5 RD05 R/W bit4 RD04 R/W bit3 RD03 R/W bit2 RD02 R/W bit1 RD01 R/W bit0 RD00 R/W Initial value XXXXXXXXB WRDR3 Address 0C88H bit7 RD07 R/W bit6 RD06 R/W bit5 RD05 R/W bit4 RD04 R/W bit3 RD03 R/W bit2 RD02 R/W bit1 RD01 R/W bit0 RD00 R/W Initial value XXXXXXXXB WRDR4 Address 0C8BH bit7 RD07 R/W bit6 RD06 R/W bit5 RD05 R/W bit4 RD04 R/W bit3 RD03 R/W bit2 RD02 R/W bit1 RD01 R/W bit0 RD00 R/W Initial value XXXXXXXXB WRDR5 Address 0C8EH bit7 RD07 R/W bit6 RD06 R/W bit5 RD05 R/W bit4 RD04 R/W bit3 RD03 R/W bit2 RD02 R/W bit1 RD01 R/W bit0 RD00 R/W Initial value XXXXXXXXB WRDR6 Address 0C91H bit7 RD07 R/W bit6 RD06 R/W bit5 RD05 R/W bit4 RD04 R/W bit3 RD03 R/W bit2 RD02 R/W bit1 RD01 R/W bit0 RD00 R/W Initial value XXXXXXXXB R/W : Read/write enabled X : Undefined 479 CHAPTER 20 WILD REGISTER FUNCTION Figure 20.3-3 Data Settings for Wild Registers WRDR1 to WRDR6 bit7 RD07 R/W bit6 RD06 R/W bit5 RD05 R/W bit4 RD04 R/W bit3 RD03 R/W bit2 RD02 R/W bit1 RD01 R/W bit0 RD00 R/W Initial value XXXXXXXXB Bit name RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 Description A 1-byte register that saves data for the address assigned by WRARL and WRARH. Data is valid at the address (WRARL/WRARH) corresponding to each wild register number. R/W : Read/write enabled X : Undefined Note: Six data setting registers (WRDR1 to WRDR6) are provided. Data setting registers correspond to address setting registers (WRARH1 to WRARH6, WRARL1 to WRARL6), respectively. 480 20.3 Registers of the Wild Register Function 20.3.2 Upper Address Setting Registers (WRARH1 to WRARH6) The upper address setting registers (WRARH1 to WRARH6) contain the upper part of an address where data is corrected. I Upper Address Setting Registers (WRARH1 to WRARH6) Figure 20.3-4 Upper Address Setting Registers (WRARH1 to WRARH6) WRARH1 Address 0C80H bit7 RA15 R/W bit6 RA14 R/W bit5 RA13 R/W bit4 RA12 R/W bit3 RA11 R/W bit2 RA10 R/W bit1 RA09 R/W bit0 RA08 R/W Initial value XXXXXXXXB WRARH2 Address 0C83H bit7 RA15 R/W bit6 RA14 R/W bit5 RA13 R/W bit4 RA12 R/W bit3 RA11 R/W bit2 RA10 R/W bit1 RA09 R/W bit0 RA08 R/W Initial value XXXXXXXXB WRARH3 Address 0C86H bit7 RA15 R/W bit6 RA14 R/W bit5 RA13 R/W bit4 RA12 R/W bit3 RA11 R/W bit2 RA10 R/W bit1 RA09 R/W bit0 RA08 R/W Initial value XXXXXXXXB WRARH4 Address 0C89H bit7 RA15 R/W bit6 RA14 R/W bit5 RA13 R/W bit4 RA12 R/W bit3 RA11 R/W bit2 RA10 R/W bit1 RA09 R/W bit0 RA08 R/W Initial value XXXXXXXXB WRARH5 Address 0C8CH bit7 RA15 R/W bit6 RA14 R/W bit5 RA13 R/W bit4 RA12 R/W bit3 RA11 R/W bit2 RA10 R/W bit1 RA09 R/W bit0 RA08 R/W Initial value XXXXXXXXB WRARH6 Address 0C8FH bit7 RA15 R/W bit6 RA14 R/W bit5 RA13 R/W bit4 RA12 R/W bit3 RA11 R/W bit2 RA10 R/W bit1 RA09 R/W bit0 RA08 R/W Initial value XXXXXXXXB R/W : Read/write enabled X : Undefined 481 CHAPTER 20 WILD REGISTER FUNCTION Figure 20.3-5 Upper Address Registers (WRARH1 to WRARH6) Settings WRARH1 to WRARH6 bit7 RA15 R/W bit6 RA14 R/W bit5 RA13 R/W bit4 RA12 R/W bit3 RA11 R/W bit2 RA10 R/W bit1 RA09 R/W bit0 RA08 R/W Initial value XXXXXXXXB Bit name RA15 RA14 RA13 RA12 RA11 RA10 RA09 RA08 Description 1-byte register that specifies an upper address allocated in memory. Specify an address for each upper address register. R/W : Read/write enabled X : Undefined 482 20.3 Registers of the Wild Register Function 20.3.3 Lower Address Setting Registers (WRARL1 to WRARL6) The lower address setting registers (WRARL1 to WRARL6) contain the lower part of an address where data is corrected. I Lower Address Setting Registers (WRARL1 to WRARL6) Figure 20.3-6 Lower Address Setting Registers (WRARL1 to WRARL6) WRARL1 Address 0C81H bit7 RA07 R/W bit6 RA06 R/W bit5 RA05 R/W bit4 RA04 R/W bit3 RA03 R/W bit2 RA02 R/W bit1 RA01 R/W bit0 RA00 R/W Initial value XXXXXXXXB WRARL2 Address 0C84H bit7 RA07 R/W bit6 RA06 R/W bit5 RA05 R/W bit4 RA04 R/W bit3 RA03 R/W bit2 RA02 R/W bit1 RA01 R/W bit0 RA00 R/W Initial value XXXXXXXXB WRARL3 Address 0C87H bit7 RA07 R/W bit6 RA06 R/W bit5 RA05 R/W bit4 RA04 R/W bit3 RA03 R/W bit2 RA02 R/W bit1 RA01 R/W bit0 RA00 R/W Initial value XXXXXXXXB WRARL4 Address 0C8AH bit7 RA07 R/W bit6 RA06 R/W bit5 RA05 R/W bit4 RA04 R/W bit3 RA03 R/W bit2 RA02 R/W bit1 RA01 R/W bit0 RA00 R/W Initial value XXXXXXXXB WRARL5 Address 0C8DH bit7 RA07 R/W bit6 RA06 R/W bit5 RA05 R/W bit4 RA04 R/W bit3 RA03 R/W bit2 RA02 R/W bit1 RA01 R/W bit0 RA00 R/W Initial value XXXXXXXXB WRARL6 Address 0C90H bit7 RA07 R/W bit6 RA06 R/W bit5 RA05 R/W bit4 RA04 R/W bit3 RA03 R/W bit2 RA02 R/W bit1 RA01 R/W bit0 RA00 R/W Initial value XXXXXXXXB R/W : Read/write enabled X : Undefined 483 CHAPTER 20 WILD REGISTER FUNCTION Figure 20.3-7 Lower Address Registers (WRARL1 to WRARL6) Settings WRARL1 to WRARL6 bit7 RA07 R/W bit6 RA06 R/W bit5 RA05 R/W bit4 RA04 R/W bit3 RA03 R/W bit2 RA02 R/W bit1 RA01 R/W bit0 RA00 R/W Initial value XXXXXXXXB Bit name RA07 RA06 RA05 RA04 RA03 RA02 RA01 RA00 Description 1-byte register that specifies an upper address allocated in memory. Specify an address for each upper address register. R/W : Read/write enabled X : Undefined 484 20.3 Registers of the Wild Register Function 20.3.4 Wild Register Enable Register (WREN) The WREN register enables or disables operation of the wild register function for each wild register number. I Wild Register Enable Register (WREN) Figure 20.3-8 Wild Register Enable Register (WREN) WREN (Wild Register Enable Register) Address 0077H bit7 R/W R/W : Read/write enabled : Unused bit6 R/W bit5 EN05 R/W bit4 EN04 R/W bit3 EN03 R/W bit2 EN02 R/W bit1 EN01 R/W bit0 EN00 R/W Initial value --000000B Table 20.3-1 Functions of the Wild Register Enable Register (WREN) Bit name Bit 7 Bit 6 Unused bits Function The read value is undefined. Writing this bit has no effect on operation. Setting this bit to 0 disables the wild register function. Setting this bit to 1 enables the wild register function. If a match is then found for the address set in WRARH6 and WRARL6, the value in the WRDR6 is output to the internal bus instead of the value in ROM. Setting this bit to 0 disables the wild register function. Setting this bit to 1 enables the wild register function. If a match is then found for the address set in WRARH5 and WRARL5, the value in the WRDR5 is output to the internal bus instead of the value in ROM. Setting this bit to 0 disables the wild register function. Setting this bit to 1 enables the wild register function. If a match is then found for the address set in WRARH4 and WRARL4, the value in WRDR4 is output to the internal bus instead of the value in ROM. Setting this bit to 0 disables the wild register function. Setting this bit to 1 enables the wild register function. If a match is then found for the address set in WRARH3 and WRARL3, the value in the WRDR3 is output to the internal bus instead of the value in ROM. Bit 5 EN05 Bit 4 EN04 Bit 3 EN03 Bit 2 EN02 485 CHAPTER 20 WILD REGISTER FUNCTION Table 20.3-1 Functions of the Wild Register Enable Register (WREN) (Continued) Bit name Function Setting this bit to 0 disables the wild register function. Setting this bit to 1 enables the wild register function. If a match is then found for the address set in WRARH2 and WRARL2, the value in the WRDR2 is output to the internal bus instead of the value in ROM. Setting this bit to 0 disables the wild register function. Setting this bit to 1 enables the wild register function. If a match is then found for the address set in WRARH1 and WRARL1, the value in the WRDR1 is output to the internal bus instead of the value in ROM. Bit 1 EN01 Bit 0 EN00 486 20.3 Registers of the Wild Register Function 20.3.5 Wild Register Data Test Register (WROR) This section describes the wild register test register and its relationship to the wild register. I Wild register data test register (WROR) and its relationship to the wild register Figure 20.3-9 Wild Register Data Test Register (WROR) and Its Relationship to the Wild Register WROR bit7 0078H bit6 bit5 DRR5 R/W bit4 DRR4 R/W bit3 DRR3 R/W bit2 DRR2 R/W bit1 DRR1 R/W bit0 DRR0 R/W Initial value --000000B Bit name ------DRR5 DRR4 DRR3 DRR2 DRR1 DRR0 Description Bits that enable the ordinary read function for the corresponding data registers (WRDR1 to WRDR6) R/W : Read/write enabled : Undefined 487 CHAPTER 20 WILD REGISTER FUNCTION 20.4 Operation of the Wild Register Function This section describes the sequence of wild register function operations. I Wild Register Operations A special program defining access between external memory (for example, EEPROM) and the wild register must be placed before ordinary user programs. The procedure for setting the wild register is described below. This section does not discuss the communication method between external memory and the device. * * * * Write addresses at which internal ROM codes are to be modified in the upper address registers (WRARH1 to WRARH6) and lower address registers (WRARL1 to WRARL6). Write new code to the corresponding data registers (WRDR1 to WRDR6). Set the corresponding enable bits in the enable register (WREN) by writing to enable the wild register function. In the normal state, the data registers (WRDR1 to WRDR6) can be written to only via the address bus or data bus. These registers cannot be read directly via the address bus or data bus. To read these registers directly via the address bus or data bus, the corresponding bits in the data test register (WROR) must be set correctly. The main function of the data test register is to serve as a dedicated test function register. Table 20.4-1 "Sequence of Wild Register Function Operations" shows the sequence setting the registers with the wild register function. Table 20.4-1 Sequence of Wild Register Function Operations Order 0 Operation Set data for replacement in the internal ROM space using the appropriate communication method. Write to the first upper address register (WRARH1 to WRARH6). Write to the first lower address register (WRARL1 to WRARL6). Write the first new ROM code, which will replace the existing internal ROM code, to the first data register (WRDR1 to WRDR6). To replace more than one internal ROM code, repeat steps 1 to 3. Up to six addresses and data items can be set. When no more setting is required, go to the next step. Enable the corresponding bits in the enable register (WREN). Operation example Write the address of an internal ROM code to be modified at address F011H, and write the address of the replacement data to A6H to B5H. Up to six internal ROM codes can be changed. Set WRARH1 = F0H, and set WRARH2 to WRARH6 accordingly. Set WRARL1 = 11H, and set WRARL2 to WRARL6 accordingly. Set WRDR1 = B5H, and set WRDR2 to WRDR6 accordingly. Repeat steps 1 to 3. 1 2 3 4 5 Setting bit 0 of the WREN to "1" enables the WRDR1 register. The data in this register can be accessed if the address is set accordingly. To replace more than one ROM code, set additional addresses and WRDR registers. 488 20.4 Operation of the Wild Register Function Table 20.4-2 List of Wild Register Addresses Operation WRARH1 to WRARH6 Enables reading from and writing to the addresses assigned to the registers. Enables reading from and writing to the addresses assigned to the registers. Enables writing to the addresses assigned to the registers. Reading is controlled by WROR. Enables reading from and writing to the addresses assigned to the register. Enables reading from and writing to the addresses assigned to the register. Write Ordinary Read Ordinary RMW Ordinary WRARL1 to WRARL6 Ordinary Ordinary Ordinary WRDR1 to WRDR6 Ordinary Depends on WROR Depends on WROR WREN Ordinary Ordinary Ordinary WROR Ordinary Ordinary Ordinary Reference: When these registers are used for the wild register function, writing to them may cause an error. Therefore, when modifying data in these registers, set the WREN value to "00H" before modifying the data. 489 CHAPTER 20 WILD REGISTER FUNCTION 20.5 General Hardware Connections This section describes the general connections between hardware units when the wild register function is used. I Hardware Connections Figure 20.5-1 General Hardware Connections Microchip EEPROM 25AA080 8K bits SO SI SCK SI SO MB89530/530H/530A series SCK When serial I/O is used as the communication interface with external EEPROM, special precautions are required. For serial I/O of the MB89530/530H/530A series, the SP-compatible method is selected as the communication method for this series. When an external memory device is selected, an SPI-compatible device needs to be selected for correct communication with the device. 490 CHAPTER 21 CLOCK OUTPUT This section describes the functions and operation of clock output. 21.1 "Overview of Clock Output" 21.2 "Clock Output Components" 21.3 "Clock Output Pins" 21.4 "Registers for Clock Output" 21.5 "Description of Clock Output Operation" 21.6 "Notes on Use of Clock Output" 21.7 "Sample Program of Clock Output" 491 CHAPTER 21 CLOCK OUTPUT 21.1 Overview of Clock Output Clock output supplies divide by 2 waveforms of the high-speed clock and waveforms of the low-speed clock from a port. This section describes the main clock output and subclock output. I Clock output The following describes the pins used for clock output: * P30/PPG03/MCO: A general-purpose I/O port for outputting the main clock divided by 2 (P30), 6-bit PPG, and main clock. (For instance, when the main clock is 10 MHz, MCO output is set to 5 MHz.) P31/SCK1 (UCK1)/LMCO: A general-purpose port (P31), SIO/UART clock I/O, subclock output. * 492 21.2 Clock Output Components 21.2 Clock Output Components The clock output block consists of the following three components: * Clock output control register (CKR) * Main clock oscillator * Subclock oscillator I Block diagram of clock output Figure 21.2-1 Clock Output Block Diagram CKR MCO LMCO Main clock oscillator Divide by 2 divider Pin P30/PPG03/MCO Subclock oscillator Pin P31/SCK1(UCK1)/LMCO Main clock oscillator Supplies the system main clock (10 MHz) in main watch mode. Subclock oscillator Supplies the system subclock (32.768 kHz) in subwatch mode. Clock output control register (CKR) Enables output of the subclock square waves and divide by 2 main clock square waves supplied from the main clock oscillator. 493 CHAPTER 21 CLOCK OUTPUT 21.3 Clock Output Pins This section provides a description and block diagram of the pins related to clock output. I Pins for the main clock output P30/PPG03/MCO: A general-purpose I/O port for outputting the main clock divided by 2 (P30), 6-bit PPG, and main clock. (For instance, when the main clock is 10 MHz, MCO output is set to 5 MHz.) * MCO: Outputs divide by 2 main clock square waves. I Pins for the subclock output P31/SCK1 (UCK1)/LMCO: A general-purpose I/O port (P31), SIO/UART clock I/O, subclock output. * LMCO: Outputs square waves whose frequency is the same as that of the subclock. I Block diagram of P30/PPG03/MCO and P31/SCK1 (UCK1)/LMCO Figure 21.3-1 Block Diagram of P30/PPG03/MCO and P31/SCK1(UCK1)/LMCO Pins for Clock Output P31 only To peripheral resource PDR (port data register) Stop/watch mode Pull-up resistor About 50 k PDR read Internal data bus From resource output Pull-up control register From resource output enable PDR read (for bit manipulation instructions) Pch Output latch PDR write Pch Pin DDR (Port data direction register) P31/SCK1 (UCK1)/LMCO Nch P30/PPG03/MCO DDR write Stop and watch mode (SPL = 1) DDR read DDR (port data direction register) SPL: Pin state setting pin in the standby control register (STBC) Reference: When "pull-up resistor available" is selected using the pull-up option setting register, the pins are set to the "H" (pulled up) level, not the high impedance state, in stop mode or watch mode (SPL = 1). During a reset, however, the pull-up is disabled and the pins are set to Hiz. 494 21.4 Registers for Clock Output 21.4 Registers for Clock Output This section describes the registers for clock output. I Registers for clock output Figure 21.4-1 Registers for Clock Output Clock output control register (CKR) Address 005AH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value MCO LMCO R/W R/W ------00B R/W : Read/Write enabled : Unused 495 CHAPTER 21 CLOCK OUTPUT 21.4.1 Clock Output Control Register (CKR) The clock output control register (CKR) is used to enable clock output. I Clock output control register (CKR) Figure 21.4-2 Clock Output Control Register (CKR) Address 0 0 5 AH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value MCO LMCO R/W R/W ------00B LMCO Subclock output enable bit 0 1 Disables subclock output. Enables subclock output. MCO Main clock output enable bit 0 1 Disables main clock output. Enables main clock output. R/W : Read/Write enabled : Unused : Initial value Table 21.4-1 Description of Clock Output Control Register (CKR) Bits Bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Description Unused * * Value read are undefined. Writing has no effect on operation. MCO: Main clock output enable bit LMCO: Subclock output enable bit * * This bit enables output of waveforms of the main clock divided by 2 for P30/PPG03/MCO. This bit enables output of the subclock waveform for P31/ SCK1/(UCK1)/LMCO. 496 21.5 Description of Clock Output Operation 21.5 Description of Clock Output Operation This section describes the clock output operation. I Description of clock output operation Figure 21.5-1 Setting for Clock Output bit7 CKR bit6 bit5 bit4 bit3 bit2 bit1 MCO bit0 LMCO : Bit used Setting bit 0 of the clock output control register to 1 makes P31/SCK1(UCK1)/LMCO output square waves with a frequency that is the same as that of the subclock oscillator. Setting bit 1 of the clock output control register to 1 makes P30/PPG03/MCO output divide by 2 square waves of the main clock oscillator frequency. 497 CHAPTER 21 CLOCK OUTPUT 21.6 Notes on Use of Clock Output This section provides notes on using the clock output. I Notes on use of clock output For P30/PPG03/MCO, MCO cannot provide a clock output when PPG03 output is enabled, even if the corresponding clock control register bit is enabled. To use MCO output, disable PPG03. For P31/SCK1(UCK1)/LMCO, LMCO cannot provide clock output when SCK1(UCK1) output is enabled, even if the clock control register bit corresponding to it is enabled. To use LMCO output, disable SCK1(UCK1). 498 21.7 Sample Clock Output Program 21.7 Sample Clock Output Program This section provides a sample program for clock output. I Sample clock output program Processing specification Outputting divide by 2 square waves of the main clock oscillator frequency Coding sample CKR EQU 005AH ;Clock control register ;----------Main program------------------------------------------------------CSEG ;[CODE SEGMENT] : MOV CKR,#00000010B ;Enabling main clock output : ENDS ;----------------------------------------------------------------------------END 499 CHAPTER 21 CLOCK OUTPUT 500 CHAPTER 22 FLASH MEMORY This chapter explains the functions and operation of the 1M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: 1. Parallel programmer 2. Writing/erasing data using a serial programmer 3. Executing programs to write/erase data This chapter explains "Executing programs to write/erase data". *: A user must create a serial programmer for writing. 22.1 "Outline of Flash Memory" 22.2 "Sector Configuration of the Flash Memory" 22.3 "Flash Memory Control Status Register (FMCS)" 22.4 "Starting the Flash Memory Automatic Algorithm" 22.5 "Confirming the Automatic Algorithm Execution State" 22.6 "Detailed Explanation of Writing to Erasing Flash Memory" 22.7 "Notes on using Flash Memory" 501 CHAPTER 22 FLASH MEMORY 22.1 Outline of Flash Memory The 1M-bit flash memory is mapped to the 4000H to FFFFH bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted. As a result, improvements in programs and data can be performed efficiently. I Flash Memory Features * * * * * * * * Sector configuration: 48K bytes x 8 bits (16 K + 8 K + 8 K + 16 K) Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200) Erase pause/restart functions provided Detection of completion of writing/erasing using data polling or toggle bit functions Detection of completion of writing/erasing using CPU interrupts Compatible with JEDEC standard commands Sector erase function (any combination of sectors) Minimum of 10,000 write/erase operations Embedded Algorithm is a trademark of Advanced Micro Device, Inc. I Writing to/Erasing Flash Memory The flash memory cannot be written to and read at the same time. That is, when data is written to or erased data from the flash memory, the program in the flash memory must first be copied to RAM. The entire process is then executed in RAM so that data is simply written to the flash memory. This eliminates the need for the program to access the flash memory from the flash memory itself. I Flash Memory Register Compatible with JEDEC standard commands Bit No. 007AH Read/write Initial value bit7 INTE (R/W) (0) bit6 RDYINT (R/W) (0) bit5 WE (R/W) (0) bit4 RDY (R) (X) bit3 Reserved (R/W) (0) bit2 Reserved (R/W) (0) bit1 (-) (-) bit0 Reserved (R/W) (0) 502 22.2 Sector Configuration of the Flash Memory 22.2 Sector Configuration of the Flash Memory Figure 22.2-1 "Flash Memory Sector Configuration" shows the sector configuration of the flash memory. I Sector Configuration Figure 22.2-1 "Flash Memory Sector Configuration" shows the addresses of each sector used when access is made from the CPU and when a flash memory writing programmer is used. Figure 22.2-1 Flash Memory Sector Configuration Flash memory 16K bytes CPU address FFFFH to C000H BFFFH to A000H 9FFFH to 8000H 7FFFH to 4000H Programmer address(*1) 1FFFFH to 1C000H 1BFFFH to 1A000H 19FFFH to 18000H 17FFFH to 14000H 8K bytes 8K bytes 16K bytes * Programmer address The programmer address is equivalent to the CPU address when data is written to the flash memory using a parallel programmer. When a general programmer is used for writing/ erasing, this address is used for writing/erasing. 503 CHAPTER 22 FLASH MEMORY 22.3 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory. I Flash Memory Control Status Register (FMCS) Figure 22.3-1 Control Status Register (FMCS) Address 007AH bit7 bit6 bit5 bit4 RDY R bit3 bit2 bit1 bit0 Reserved Initial value 000X00-0B INTE RDYINT WE R/W R/W R/W Reserved Reserved R/W R/W R/W Reserved 0 Reserved bit Bit reserved for test. Set this bit to 0 for normal operation. Unused bit 0 Reserved 0 Set this bit to 0 for normal operation. Reserved bit Bit reserved for test. Set this bit to 0 for normal operation. ReadDY bit (for enabling data to be written into/erased from flash memory) Data is being written or erased. Data writing/erasing has been completed. (Subsequent data can be written/erased.) Write enable bit Disables data to be written into/erased from flash memory. Enables data to be written into/erased from flash memory. Flash memory operation state indication bit Data is being written/erased. Data writing/erasing has been completed. (An interrupt request is generated.) RDY 0 1 WE 0 1 RDYINT 0 1 INTE 0 tinst : Instruction cycle R/W : Read/Write enabled : Initial value 1 Bit causing an interrupt to the CPU to be generated Enables an interrupt when data writing/erasing is completed. Disables an interrupt when data writing/erasing is completed. 504 22.3 Flash Memory Control Status Register (FMCS) Table 22.3-1 Description of the Control Status Register (FMCS) bits Bit INTE: INTERRPUT Enable Description Bit causing an interrupt to the CPU to be generated when writing into or erasing from flash memory is completed. An interrupt to the CPU is generated when both the INTE bit and RDYINT bit are 1. If the INTE bit is 0, no interrupt is generated. Bit for indicating operation status of flash memory. This bit is set to 1 when writing into or erasing from flash memory is completed. While this bit is set to 0 after writing into or erasing from flash memory has been completed, data cannot be written into or erased from flash memory. After data has been written into or erased from flash memory and this bit has been set to 1, data can be written into or erased from flash memory. Writing 0 clears this bit with 0, while if 1 is written into this bit, it is ignored. This bit is set to 1 upon the termination of the flash memory automatic algorithm (see Section 22.4 "Starting the Flash Memory Automatic Algorithm".). The read modifier write (RMW) command always reads 1 from this bit. Bit for write-enabling flash memory areas. When this bit is set to 1, a write instruction performed after a command sequence for a section from 1000H to FFFFH (see Section 22.4 "Starting the Flash Memory Automatic Algorithm") is issued writes data into a flash memory area. When this bit is set to 0, no write/erase signals are generated. This bit is used to start a command for writing data into or erasing data from flash memory. It is recommended that this bit be set to 0 to prevent data from being incorrectly written into flash memory, whenever there is no data to be written or erased. Bit for writing data into or erasing data from flash memory. No data can be written into or erased from flash memory while this bit is set to 0. However, a read command, reset command, and suspend commands such as the sector erase suspend command can be accepted while this bit is set to 0. Bit reserved for test. Specify 0 for this bit for normal operation. Specify 0 to this bit for normal operation. Bit reserved for test. Specify 0 for this bit for normal operation. bit7 bit6 RDYINT: READY INTERRUPT bit5 WE: WRITE ENABLE bit4 RDY: READY bit3 bit2 bit1 bit0 Reserved bit Unused bit Reserved bit Note: The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions are made using one or the other of these bits. Automatic algorithm Termination timing RDYINT bit RDY bit 1 machine cycle 505 CHAPTER 22 FLASH MEMORY 22.4 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled for sector erase. I Command Sequence Table Table 22.4-1 "Command Sequence Table" lists the commands used for flash memory write/ erase. Table 22.4-1 Command Sequence Table Command sequence Bus write access 1st bus write cycle Address Read/Reset (*1) Read/ (*1) Reset Write program Chip Erase Sector Erase 1 XXXX Data F0 2nd bus write cycle Address Data 3rd bus write cycle Address Data 4th bus read/ write cycle Address Data 5th bus write cycle Address Data 6th bus write cycle Address Data - 3 AAAA AA 5554 55 AAAA F0 RA RD - - - - 3 6 6 AAAA AAAA AAAA AA AA AA 5554 5554 5554 55 55 55 AAAA AAAA AAAA A0 80 80 PA AAAA AAAA PD AA AA 5554 5554 55 55 AAAA SA 10 30 Sector Erase Suspend Sector Erase Restart Entering address "XXXXX" and data (B0H) suspends erasing during sector erase. Entering address "XXXXX" and data (30H) restarts erasing after erasing has been suspended during sector erase. Note: The addresses shown in the table are those on the CPU memory map. All addresses and data are represented in hexadecimal notation. The letter X indicates an appropriate value. RA: Read address PA: Write address. SA: Sector address. See Section 22.2 "Sector Configuration of the Flash Memory". RD: Read data PD: Write data. *1: Both of the two types of Read/Reset commands can reset the flash memory to read mode. 506 22.5 Confirming the Automatic Algorithm Execution State 22.5 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences. I Hardware Sequence Flags The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3 and DQ2. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit 2 flag (DQ2). The hardware sequence flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase code write is valid. The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the flash memory after setting of the command sequence (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm". Table 22.5-1 "Bit Assignments of Hardware Sequence Flags" lists the bit assignments of the hardware sequence flags. Table 22.5-1 Bit Assignments of Hardware Sequence Flags bit7 Hardware sequence flag DQ7 bit6 DQ6 bit5 DQ5 bit4 bit3 DQ3 bit2 DQ2 bit1 bit0 - To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition, the hardware sequence flags can be used to confirm whether the second or subsequent sector erase code write is valid. The following sections describe each hardware sequence flag separately. Table 22.5-2 "Hardware Sequence Flag Functions" lists the functions of the hardware sequence flags. 507 CHAPTER 22 FLASH MEMORY Table 22.5-2 Hardware Sequence Flag Functions State Executing Automatic writing operation Write/erase operation during automatic erasing Erasing Suspending Stopping Exceeding the time limit Read (sector in which data is being erased) Read (sector in which no data is erased) Write (sector in which no data is erased) DQ7 DQ7 0 1 DATA DQ7 DQ7 0 DQ6 Toggle Toggle 1 DATA Toggle Toggle Toggle DQ5 0 0 0 DATA 0 1 1 DQ3 0 1 0 DATA 0 0 1 DQ2 1 Toggle Toggle DATA 1(*1) 1 (*2) Automatic writing operation Write/erase operation during automatic erasing *1 While an erase suspend write is being performed, DQ2 outputs logical 1 to the address of the sector into which data is being written. However, DQ2 toggles to successive reads from the erase-suspended sector. *2 When 1 is set to DQ5 (excess of the time limit), DQ2 toggles to successive reads from a sector in which data is being written or erased, and never toggles to any read to other sectors. 508 22.5 Confirming the Automatic Algorithm Execution State 22.5.1 Data Polling Flag (DQ7) The data polling flag uses the data polling function to post that the automatic algorithm is being executed or has terminated I Write Read-access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit 7 last written, regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output bit 7 of the read value of the address specified by the address signal. I Automatic erasing Read-access during execution of the automatic erasing algorithm causes the flash memory to output 0, regardless of the value at the address specified by the address signal. After the automatic erasing algorithm is executed, 1 is output. I Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 7 (DATA: 7) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a decision to be made on whether the flash memory is in the erase suspended state and which sector is being erased. Note: When the automatic algorithm comes to the end of its operation, bit 7 (data polling) changes its state asynchronously during a read operation. This means that flash memory sends data about the operation state to bit 7 and will then send out fixed data. When flash memory ends the automatic algorithm or even if bit 7 is outputting fixed data, the values of the other bits are still undetermined. Fixed data in the other bits can be read by successively executing read operations. 509 CHAPTER 22 FLASH MEMORY 22.5.2 Toggle Bit Flag (DQ6) Like the data polling flag, the toggle bit flag uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. I Automatic write/erase Making successive read accesses while the automatic writing/erasing algorithm is being performed toggles flash memory and makes it output 1 and then 0, in turn, regardless of the specified address. Making successive read accesses when the automatic writing/erasing algorithm ends makes flash memory to stop bit 6 toggle and outputs the value of bit 6 (DATA:6) corresponding to the value read from the specified address. The toggle bit becomes effective after the last write cycle in each command sequence. I Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 6 (DATA: 6) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Note: For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the toggle operation after approximately 2s without any data being rewritten. For an erase, if all of the selected sectors are write-protected, the toggle bit performs toggling for approximately 100s and then returns to the read/reset state without any data being rewritten. 510 22.5 Confirming the Automatic Algorithm Execution State 22.5.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. I Automatic write/erase Bit 5 indicates that execution of the automatic algorithm exceeded the time (internal pulse count) specified in flash memory. For an excess, bit 5 outputs 1. Thus, if this bit outputs 1 while the automatic algorithm is operating, data writing or data erasing failed. Bit 5 indicates a failure when an attempt is made to write data into a non-blank area without erasing any data. In the case of such a failure, fixed data cannot be read from bit 7 (data polling) and bit 6 (toggle bit) remains unchanged (toggled). If the time limit is exceeded while there is a failure, 1 is set in bit 5. In this case, note that the setting of bit 5 to 1 does not indicate a flash memory failure but the incorrect use of flash memory. If bit 5 is set to 1 as described above, execute a reset command. 511 CHAPTER 22 FLASH MEMORY 22.5.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started. I Sector erase After the first sector erase command sequence is executed, the sector erase wait period begins. Bit 3 outputs 0 in the sector erase wait period and, if the period has ended, it outputs 1. Data polling and the toggle bit become effective after the first sector erase command sequence is executed. If the data polling function or toggle bit function indicates that the erase algorithm is being executed, internally controlled erase has already started if this flag is 1. Continuous write of the sector erase codes or commands other than the Sector Erase Suspend command will be ignored until erase is terminated. (Only erase suspend code input is allowed.) If this flag is 0, the flash memory will accept write of additional sector erase codes. To confirm this, it is recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag is 1 after the second state check, it is possible that additional sector erase codes may not be accepted. Read-access during execution of sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 3 of the read value of the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. 512 22.5 Confirming the Automatic Algorithm Execution State 22.5.5 Toggle Bit-2 Flag (DQ2) The toggle bit-2 flag (DQ2) is used to detect that flash memory is performing an automatic erase operation or erase suspend operation, together with the toggle bit. I Sector erase This toggle bit is used to detect that flash memory is performing an automatic erase operation or erase suspend operation, together with the toggle bit, bit 6. Executing successive reads to a sector in which an automatic erase operation is being performed toggles bit 2. When the flash memory is in erase suspend read mode, executing successive reads to an erase-suspended sector toggles bit 2. When the flash memory is in erase suspend write mode, successively reading addresses from a sector that is not erase-suspended provides 1 to bit 2. Unlike bit 2, bit 6 toggles during normal write, erase, or erase suspend write. For example, bit 2 is used together with bit 6 to detect erase suspend read mode (bit 2 toggles but bit 6 does not toggle). In addition, bit 2 is used to detect sectors in which data is being deleted. While flash memory is erasing data, bit 2 toggles to a read from a sector from which data is being erased. 513 CHAPTER 22 FLASH MEMORY 22.6 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued. I Detailed Explanation of Flash Memory Write/Erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm") for a write cycle to the bus to perform Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations. Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has terminated can be determined using the data polling or other function. At normal termination, the flash memory is returned to the read/reset state. Each operation of the flash memory is described in the following order: 22.6.1 "Setting the read/reset state" 22.6.2 "Writing data" 22.6.3 "Erasing all data (erasing chips)" 22.6.4 "Erasing data (erasing sectors)" 22.6.5 "Suspending sector erase" 22.6.6 "Restarting sector erase" 514 22.6 Detailed Explanation of Writing to and Erasing Flash Memory 22.6.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. I Setting the Read/Reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Read/Reset command has two types of command sequences that execute the first and third bus operations. However, there are no essential differences between these command sequences. The read/reset state is the initial state of the flash memory. When the power is turned on and when a command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other commands wait for input. In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally. 515 CHAPTER 22 FLASH MEMORY 22.6.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. Figure 22.6-1 "Example of the Flash Memory Write Procedure" shows an example of the flash memory write procedure. I Writing Data The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. When data write to the target address is completed in the fourth cycle, the automatic algorithm and automatic write are started. I Specifying addresses Only even addresses can be specified in bytes for the write addresses specified in a write data cycle. Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the Write command writes only data of one byte for each execution. I Notes on writing data Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy data 1 had been written. However, when data is read in the read/reset state, the data remains 0. Data 0 can be set to data 1 only by erase operations. All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started during writing, the data of the written addresses will be unpredictable. I Writing to the Flash Memory Figure 22.6-1 "Example of the Flash Memory Write Procedure" is an example of the procedure for writing to the flash memory. The hardware sequence flags (see Section 22.5 "Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writing has terminated. The data read to check the flag is read from the address written to last. The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes. For example, even if the timing limit exceeded flag (DQ5) is 1, the data polling flag bit (DQ7) must be rechecked. Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit exceeded flag bit (DQ5) changes to 1. The toggle bit flag (DQ6) must therefore be rechecked. 516 22.6 Detailed Explanation of Writing to and Erasing Flash Memory Figure 22.6-1 Example of the Flash Memory Write Procedure Start writing FMCS: WE (bit 5) Enable flash memory write Write command sequence (1) AAAA <-- AA (2) 5554 <-- 55 (3) AAAA <-- A0 (4) Write address <-- Write data Read internal address Next address Data polling (DQ7) Data Data 0 Timing limit (DQ5) 1 Read internal address Data Data polling (DQ7) Data Write error Final address FMCS: WE (bit 5) Enable flash memory write Confirm with the hardware sequence flags. Complete writing 517 CHAPTER 22 FLASH MEMORY 22.6.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. I Erasing all Data (Erasing Chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed, the chip erase operation is started. For chip erase, the user need not write to the flash memory before erasing. During execution of the automatic erase algorithm, the flash memory writes 0 for verification before all of the cells are erased automatically. 518 22.6 Detailed Explanation of Writing to and Erasing Flash Memory 22.6.4 Erasing Data (Erasing Sectors) This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time. I Erasing Data (Erasing Sectors) Optional sectors in the flash memory can be erased by sending the Sector Erase command in the command sequence table (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. I Specifying sectors The Sector Erase command is executed in six bus operations. Sector erase wait of 50s is started by writing the sector erase code (30h) to an accessible even-numbered address in the target sector in the sixth cycle. To erase multiple sectors, write the erase code (30h) to the addresses in the target sectors after the above processing operation. I Notes on specifying multiple sectors Erase is started when the sector erase wait period of 50s terminates after the final sector erase code has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of the command sequence) must be written within 50s of writing of the address of a sector and the address of the next sector must be written within 50s of writing of the previous erase code. Otherwise, the address and erase code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used for reading the sector erase timer indicates the sector to be erased. I Erasing Sectors The hardware sequence flags (see Section 22.5 "Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Figure 22.6-2 "Example of the Sector Erase Procedure" is an example of the procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to confirm that erasing has terminated. The data that is read to check the flag is read from the sector to be erased. The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag (DQ5) is changed to 1. For example, even if the timing limit exceeded flag (DQ5) is 1, the toggle bit flag (DQ6) must be rechecked. The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked. 519 CHAPTER 22 FLASH MEMORY Figure 22.6-2 Example of the Sector Erase Procedure Start erasing FMCS: WE (bit 5) Enable flash memory erase Erase command sequence (1) AAAA <-- AA (2) 5554 <-- 55 (3) AAAA <-- 80 (4) 5554 <-- 55 (5) Sector address <-Erase code (30H) 0 1 Sector erase timer (DQ3) (6) Sector address <-Erase code (30H) Read internal address Y Another erase sector N Read internal address 1 Read internal address 2 Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6) N 0 Y Next sector Timing limit (DQ5) 1 Read internal address 1 Read internal address 2 N Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6) Y Erase error Final sector Y N FMCS: WE (bit 5) Disable flash memory erase Confirm with the hardware sequence flags. Complete erasing 520 22.6 Detailed Explanation of Writing to and Erasing Flash Memory 22.6.5 Suspending Sector Erase This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased. I Suspending Erasing of Sectors Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the command sequence table (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Suspend command suspends the sector erase operation being executed and enables data to be read from sectors that are not being erased. In this state, only reading is enabled; data cannot be written. This command is valid only during sector erase operations that include the erase wait time. The command will be ignored during chip erase or write operations. This command is implemented by writing the erase suspend code (B0h). At this time, specify an optional address in the flash memory for the address. An Erase Suspend command issued again during erasing of sectors will be ignored. Entering the Sector Erase Suspend command during the sector erase wait period will immediately terminate sector erase wait, cancel the erase operation, and set the erase stop state. Entering the Erase Suspend command during the erase operation after the sector erase wait period has terminated will set the erase suspend state after a maximum period of 15s has elapsed. 521 CHAPTER 22 FLASH MEMORY 22.6.6 Restarting Sector Erase This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors. I Restarting Erasing of Sectors Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command in the command sequence table (see Table 22.4-1 "Command Sequence Table" in Section 22.4 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Restart command is used to restart erasing of sectors from the sector erase suspend state set using the Sector Erase Suspend command. The Sector Erase Restart command is implemented by writing the erase restart code (30h). At this time, specify an optional address in the flash memory area for the address. If a Sector Erase Restart command is issued during sector erase, the command will be ignored. 522 22.7 Notes on using Flash Memory 22.7 Notes on using Flash Memory This section provides notes on using the MB89F538/F538L, especially for flash memory. I Input of a hardware reset ( RST ) To input a hardware reset when reading is in progress, i.e., when the automatic algorithm has not been started, secure a minimum low-level width of 500 ns. To input a hardware reset while a write or erase is in progress, i.e., while the automatic algorithm is being started, secure a minimum low-level width of 500 ns. In this case, 20 s are required until the data becomes readable after the operation being performed terminates and the flash memory is fully initialized. Performing a hardware reset during a write operation makes the data being written undetermined. Also note that performing a hardware reset during an erase operation may make the sector from which data is being erased unusable. I Software reset, watchdog timer reset When write/erase of flash memory is set up for normal mode and CPU memory access mode is internal ROM mode, and if a reset cause occurs while the automatic algorithm of flash memory is being activated, the CPU may run out of control. The cause of a reset does not initialize the flash memory and keeps the automatic algorithm operating. Thus, when the CPU starts a sequence after the reset is canceled, the flash memory may not have been in a read state. Prevent a cause of a reset from occurring while the flash memory is writing or erasing. I Program access to flash memory While the automatic algorithm is being activated, any read access to the flash memory is disabled. When CPU memory access mode is set to internal ROM mode, move program areas into another area such as RAM, and then start a write or erase. In this case, when sectors containing interrupt vectors are erased, the writing or erasing of interrupt processing cannot be executed. For the same reason, other interrupt processing shall be disabled while the automatic algorithm is being activated. 523 CHAPTER 22 FLASH MEMORY 524 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING This chapter describes the example of the serial programming when the flash MCU programmer by Yokogawa Digital Computer Corporation. 23.1 "Basic Configuration of MB89F538/F538L Serial Programming Connection" 23.2 "Connection Example of Serial Programming (when User Power Supply is Used)" 23.3 "Connection Example of Serial Programming (when Power Supply is Supplied from Flash MCU Programmer)" 23.4 "Minimum Connection Example with Flash MCU Programmer (when User Power Supply is Used)" 23.5 "Minimum Connection Example with Flash Microcomputer Programmer (when Power Supply is Supplied from Flash MCU Programmer)" 525 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING 23.1 Basic Configuration of MB89F538/F538L Serial Programming Connection In MB89F538/F538L, the serial on-board programming of flash ROM (Fujitsu standard) is supported. The specification is explained as follows. I Basic Configuration of MB89F538/F538L Serial Programming Connection Based on Fujitsu standard serial on-board programming, the flash MCU programmer by Yokogawa Digital Computer Corporation can be used. Figure 23.1-1 "Basic Configuration of MB89F538/F538L Serial Programming Connection" shows the basic configuration of the MB89F538/F538L serial programming connection. Figure 23.1-1 Basic Configuration of MB89F538/F538L Serial Programming Connection Host interface cable (AZ221) General-purpose common cable (AZ210) RS232C Flash Microcomputer Programmer + memory card Clock synchronous serial MB89F538/F538L user system Operable in stand-alone mode Note: Please inquire to Yokogawa Digital Computer Corporation for more information about the operation method of flash MCU programmer (AF220/AF210/AF120/AF110), general-purpose common cable for connection (AZ210) and the connector. 526 23.1 Basic Configuration of MB89F538/F538L Serial Programming Connection Pins for Fujitsu standard serial on-board programming Table 23.1-1 Pins for Fujitsu Standard Serial On-board Programming Pin MOD2, MOD1 MOD0, P22, P23, P10 X0, X1 Function Mode pins Note Set MOD2 = 0, MOD1 = 1, MOD0 = 1, P22 = 1, P23 = 0, P10 = 1 to change to serial programming mode. The internal operation of CPU clock at the serial programming mode is divided by four of the oscillation frequency. Moreover , it is necessary to input the oscillation frequency with 3 MHz or more at the serial programming. - Oscillation pins RST SI2 SO2 SCK2 VCC Reset pin Serial data input pin Serial data output pin Serial clock input pin Power voltage supply pin Use 8-bit serial I/O. When the user system supplies the programming voltage, the connection with the flash MCU programmer is unnecessary. It is common with flash MCU programmer's GND. VSS GND pin Moreover, if SI, SO, SCK pins are also used by the user system, the control circuit is necessary (see Figure 23.1-2 "Control Circuit"). (During the serial programming, the user circuit can be cut off by the flash MCU programmer's /TICS signal. See the connection example.) Figure 23.1-2 Control Circuit AF220/AF210/AF120/AF110 write control pin AF220/AF210/AF120/AF110 /TICS pin 4.7 K MB89F538/F538L write control pin User 527 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING About oscillation clock frequency and serial input clock frequency For MB89F538/F538L, the serial clock frequency that is able to input is calculate from the following formula. Therefore, please change the serial clock input frequency in the flash MCU programmer's setting by the using oscillation clock frequency. Serial clock frequency (Max.) = 0.125 x oscillation clock frequency Example: Oscillation clock frequency Max. Serial Clock Frequency provided by MCU 500 kHz 1 MHz 1.25 MHz Max. Serial Clock Frequency provided by AF220/AF210/AF120/AF110 500 kHz 850 kHz 1.25 MHz Max. Clock Serial Frequency provided by AF200 500 kHz 500 kHz 500 kHz 4 MHz 8 MHz 10 MHz Configuration of flash microcomputer programmer system (made by Yokogawa Digital Computer Corporation) Table 23.1-2 Configuration of Flash Microcomputer Programmer System (Made by Yokogawa Digital Computer Corporation) Model Mainframe AF220/AC4P AF210/AC4P AF120/AC4P AF110/AC4P AZ221 AZ210 FF201 AZ290 /P2 /P4 Function Model with Ethernet interface built in / 100 to 220 V power adaptor Standard model / 100V to 220 V power adaptor Single-key Ethernet interface model / 100V to 220 V power adaptor Single-key model/100V to 220 V power adaptor PC/AT RS232C cable only for Programmer Standard target probe (a), length: 1 m Fujitsu F2MC-16LX flash microcomputer control model Remote controller 2 MB PC card (option) for flash memory sizes of up to 128 KB 4 MB PC card (option) for flash memory sizes of up to 512 KB Inquiries: Yokogawa Digital Computer Corporation Telephone number: (81)-42-333-6224 Note: Though AF200 flash microcomputer programmer is not available, it is possible to correspond by using control module FF201. Example of serial programming connection is possible to correspond by the connection example that is shown in the next page. 528 23.2 Connection Example of Serial Programming (when User Power Supply is Used) 23.2 Connection Example of Serial Programming (when User Power Supply is Used) In the user system, to change to serial programming mode, input MOD1, MOD0 = 11 to the mode pin that is set to MOD2, MOD1, MOD0 = 000 from TAUX3 of AF220/AF210/ AF120/AF110. (Serial programming mode: MOD2, MOD1, MOD0 = 011) I Example of Connection for Serial Programming (when Power Supplied by User) Figure 23.2-1 Example of Connection for Serial Programming in MB89F538/538L (when Power Supplied by User) AF220/AF210/AF120/AF110 User system flash microcomputer programmer Connector DX10-28S MB89F538/F538L MOD2 P23 TAUX3 (19) 4.7 K MOD1 MOD0 4.7 K 4.7 K X0 X1 TTXD TRXD TCK (13) 4.7 K (27) (6) 4. 7 K /TICS (10) User 4.7 K /TRES 4.7 K (5) RST SO2 SCK2 SI2 P22 4.7 K P10 User TVCC (2) User power supply GND (7,8, 14,15, 21,22, 1,28) Pin 14 DX10-28S Pin28 Pin 15 Connector (made by Hirose Electric) pin layout VCC VSS Pin 1 Pins 3, 4, 9, 11, 12, 16, 17, 18, 20, 23, 24, 25, and 26 are open. DX10-28S, right-angle type 529 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING * Moreover, if SI2, SO2 pins are also used by the user system, SCK2 pin and the following control circuit is necessary. (During the serial programming, the user circuit can be cut off by the flash MCU programmer's /TICS signal.) AF220/AF210/AF120/AF110 write control pin AF220/AF210/AF120/AF110 /TICS pin 4.7 K MB89F538/F538L write control pin User * * Connect AF220/AF210/AF120/AF110 during user power supply is "OFF". In Figure 23.2-1 "Example of Connection for Serial Programming in MB89F538/F538L (when Power Supplied by User)," the values indicated for the pull-up and pull-down resistors are samples, which can be changed depending on your system requirements. When noise may cause the input levels at the MOD0 or MOD1 pin to fluctuate, it is recommended that antinoise measures be taken by connecting capacitors or other devices. 530 23.3 Connection Example of Serial Programming (when Power Supply is Supplied from Flash MCU Pro- 23.3 Connection Example of Serial Programming (when Power Supply is Supplied from Flash MCU Programmer) In the user system, to change to serial programming mode, input MOD1, MOD0 = 11 to the mode pin that is set to MOD2, MOD1, MOD0 = 000 from TAUX3 of AF220/AF210/ AF120/AF110. (Serial programming mode: MOD2, MOD1, MOD0 = 011). I Example of Connection for Serial Programming (when Power Supplied by Flash MCU Programmer) Figure 23.3-1 Example of Connection for Serial Programming in MB89F538/538L (when Power Supplied by Flash MCU Programmer) AF220/AF210/AF120/AF110 User system flash microcomputer programmer Connector DX10-28S MB89F538/F538L(*1) MOD2 P23 4.7 K MOD1 MOD0 4.7 K P22 X0 X1 P10 4.7 K 4.7 K TAUX3 (19) TTXD TRXD TCK (13) 4.7 K (27) (6) 4.7 K (10) User 4.7 K 4.7 K SI2 SO2 SCK2 /TICS /TRES (5) RST User TVCC VCC TVPP1 (2) (3) (16) (7,8, 14,15, 21,22, 1,28) User power supply VSS Pin 14 Pin 1 DX10-28S Pin28 Pin 15 Connector (made by Hirose Electric) pin layout VCC GND Pins 4, 9, 11, 12, 17 18, 20, 23, 24, 25, and 26 are open. DX10-28S, right-angle type *1 For details on how to supply power from the flash MCU programmer on the MB89F538L (3V model), contact Yokogawa Digital Computer Corporation. 531 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING * Moreover, if SI2, SO2 pins are also used by the user system, SCK2 pin and the following control circuit is necessary. (During the serial programming, the user circuit can be cut off by the flash MCU programmer's /TICS signal.) AF220/AF210/AF120/AF110 write control pin AF220/AF210/AF120/AF110 /TICS pin 4.7 K MB89F538/F538L write control pin User * Connect AF220/AF210/AF120/AF110 during user power supply is "OFF". No short-circuit with the user power supply is allowed when AF220/AF210/AF120/AF110 supplies the programming power supply. * In Figure 23.3-1 "Example of Connection for Serial Programming in MB89F538/F538L (when Power Supplied by Flash MCU Programmer)," the values indicated for the pull-up and pulldown resistors are samples, which can be changed depending on your system requirements. When noise may cause the input levels at the MOD0 or MOD1 pin to fluctuate, it is recommended that anti-noise measures be taken by connecting capacitors or other devices. 532 23.4 Minimum Connection Example with Flash MCU Programmer (when User Power Supply is Used) 23.4 Minimum Connection Example with Flash MCU Programmer (when User Power Supply is Used) If each pin is set as shown in Figure 23.4-1 "Example of Minimum Connection for Flash MCU Programmer in MB89F538/538L (when Power Supplied by User)", MOD1 and MOD0 do not need to be connected with the flash MCU programmer. I Example of Minimum Connection for Flash MCU Programmer (when Power Supplied by User) Figure 23.4-1 Example of Minimum Connection for Flash MCU Programmer in MB89F538/538L (when Power Supplied by User) AF220/AF210/AF120/AF110 flash microcomputer User system programmer MB89F538/F538L MOD2 P23 4.7 K When 1, Seral programming 4.7 K MOD1 4.7 K P22 4.7 K P10 MOD0 When 1, Seral programming 4.7 K X0 X1 Connector DX10-28S /TRES TTXD TRXD TCK TVCC (5) (13) (27) (6) (2) (7,8, 14,15, 21,22, 1,28) 4.7 K 4.7 K RST SI2 SO2 SCK2 VCC GND User power supply VSS Pin 14 Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S, right-angle type DX10-28S Pin 1 Pin28 Pin 15 Connector (made by Hirose Electric) pin layout 533 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING * Moreover, if SI2, SO2, SCK2 pins are also used by the user system, the following control circuit is necessary. (During the serial programming, the user circuit can be cut off by the flash MCU programmer's /TICS signal.) AF220/AF210/AF120/AF110 write control pin AF220/AF210/AF120/AF110 /TICS pin 4.7 K MB89F538/F538L write control pin User * * Connect AF220/AF210/AF120/AF110 during user power supply is "OFF". In Figure 23.4-1 "Example of Minimum Connection for Flash MCU Programmer in MB89F538/F538L (when Power Supplied by User)," the values indicated for the pull-up and pull-down resistors are samples, which can be changed depending on your system requirements. When noise may cause the input levels at the MOD0 or MOD1 pin to fluctuate, it is recommended that anti-noise measures be taken by connecting capacitors or other devices. 534 23.5 Minimum Connection Example with Flash Microcomputer Programmer (when Power Supply is Sup- 23.5 Minimum Connection Example with Flash Microcomputer Programmer (when Power Supply is Supplied from Flash MCU Programmer) If each pin is set as shown in Figure 23.5-1 "Example of Minimum Connection for Flash MCU Programmer in MB89F538/538L (when Power Supplied by Flash MCU Programmer)" during the serial programming, the connection with MOD1 and MOD2 and flash MCU programmer is unnecessary. I Minimum Connection Example with Flash Microcomputer Programmer (when Power Supply is Supplied from Flash MCU Programmer) Figure 23.5-1 Example of Minimum Connection for Flash MCU Programmer in MB89F538/538L (when Power Supplied by Flash MCU Programmer) AF220/AF210/AF120/AF110 flash microcomputer User system programmer MB89F538/F538L(*1) MOD2 When 1, Seral programming 4.7 K MOD1 4.7 K P22 When 1, Seral programming 4.7 K 4.7 K MOD0 P10 P23 4.7 K X0 X1 Connector DX10-28S /TRES TTXD TRXD TCK TVCC VCC TVPP1 GND (5) (13) (27) (6) (2) (3) (16) (7,8, 14,15, 21,22, 1,28) 4.7 K 4.7 K RST SI2 SO2 SCK2 VCC User power supply VSS Pin 14 Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S, right-angle type Pin 1 DX10-28S Pin28 Pin 15 Connector (made by Hirose Electric) pin layout *1 For details on how to supply power from the flash MCU programmer on the MB89F538L (3V model), contact Yokogawa Digital Computer Corporation. 535 CHAPTER 23 MB89F538/F538L SERIAL PROGRAMMING * Moreover, if SI2, SO2, SCK2 pins are also used by the user system, the following control circuit is necessary. (During the serial programming, the user circuit can be cut off by the flash MCU programmer's /TICS signal.) AF220/AF210/AF120/AF110 write control pin AF220/AF210/AF120/AF110 /TICS pin 4.7 K MB89F538/F538L write control pin User * Connect AF220/AF210/AF120/AF110 during user power supply is "OFF". No short-circuit with the user power supply is allowed when AF220/AF210/AF120/AF110 supplies the programming power supply. * In Figure 23.5-1 "Example of Minimum Connection for Flash MCU Programmer in MB89F538/F538L (when Power Supplied by Flash MCU Programmer)," the values indicated for the pull-up and pull-down resistors are samples, which can be changed depending on your system requirements. When noise may cause the input levels at the MOD0 or MOD1 pin to fluctuate, it is recommended that anti-noise measures be taken by connecting capacitors or other devices. 536 APPENDIX This appendix lists the I/O map and instructions. APPENDIX A "I/O Maps" APPENDIX B "Overview of Instructions" APPENDIX C "Mask Options" APPENDIX D "Write Specifications for the One-Time PROM and EPROM Microcomputer" APPENDIX E "EPROM with Piggyback/Evaluation Chip" APPENDIX F "Pin Statuses of the MB89530/530H/530A Series" APPENDIX G "Troubleshooting" 537 APPENDIX A I/O Maps APPENDIX A I/O Maps The registers of the peripheral functions contained in MB89530/530H/530A are assigned addresses as listed in Table Table A-1 "I/O Map." I I/O Maps Table A-1 I/O Map Address 00H 01H 02H 03H 04H to 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H to 21H 22H 23H 24H 25H 26H 27H SMC11 SRC1 SSD1 SIDR1/SODR1 SMC12 CNTR1 SYCC STBC WDTC TBTC WPCR PDR2 DDR2 PDR3 DDR3 PDR4 DDR4 PDR5 PDR6 Register abbreviation PDR0 DDR0 PDR1 DDR1 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Vacancy) System clock area control register Standby control register Watchdog control register Timebase timer control register Watch prescaler control register Port 2 data register Port 2 direction register Port 3 data register Port 3 direction data register Port 4 data register Port 4 direction register Port 5 data register Port 6 data register (Vacancy) Serial mode control register 1 (UART) Serial rate control register (UART) Serial status at data register (UART) Serial input/output data register (UART) Serial mode control register 2 (UART) PWM control register 1 R/W R/W R/W R/W R/W R/W 00000000B --011000B 00100-1XB XXXXXXXXB --100001B 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R X-1MM100B 00010---B 0---XXXXB 00---000B 00--0000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXX11XXB 0000--00B 11111111B XXXXXXXXB Read/Write R/W W R/W W Initial value XXXXXXXXB 00000000B XXXXXXXXB 00000000B 538 APPENDIX A I/O Maps Table A-1 I/O Map (Continued) Address 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H to 48H 49H 4AH to 4BH 4CH 4DH 4EH 4FH 50H PPGC1 PRL12 PRL11 PRL13 IACR DDCR DDC selection register (Vacancy) PPG1 control register (12-bit PPG) PPG1 reload register 2 (12-bit PPG) PPG1 reload register 1 (12-bit PPG) PPG1 reload register 3 (12-bit PPG) I2C address control register R/W R/W R/W R/W R/W 00000000B 0X000000B XX000000B XX000000B -----000B Register abbreviation CNTR2 CNTR3 COMR1 COMR2 PCR1 PCR2 RLBR SMC21 SMC22 SSD2 SIDR2/SODR2 SRC2 ADC1 ADC2 ADDL ADDH PPGC2 PRL22 PRL21 PRL23 Register name PWM control register 2 PWM control register 3 PWM compare register 1 PWM compare register 2 PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register Serial mode control register 1 (UART/SIO) Serial mode control register 2 (UART/SIO) Serial status and data register (UART/SIO) Serial data register (UART/SIO) Baud rate generator load register A/D control register 1 A/D control register 2 Lower A/D data register Upper A/D data register PPG2 control register (12-bit PPG) PPG2 reload register 2 (12-bit PPG) PPG2 reload register 1 (12-bit PPG) PPG2 reload register 3 (12-bit PPG) 16-bit timer control register Upper 16-bit timer count register Lower 16-bit timer count register External interrupt 1 control register 1 External interrupt 1 control register 2 (Vacancy) R/W -------0B Read/Write R/W R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 000-0000B -000----B XXXXXXXXB XXXXXXXXB 000--000B 00000000B XXXXXXXXB 00000000B 00000000B 00001---B XXXXXXXXB XXXXXXXXB X00000X0B -0000001B XXXXXXXXB ------00B 00000000B 0X000000B XX000000B XX000000B --000000B 00000000B 00000000B 00000000B 00000000B TMCR TCHR TCLR EIC1 EIC2 539 APPENDIX A I/O Maps Table A-1 I/O Map (Continued) Address 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH to 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 ILR4 ITR Interrupt level set register 1 Interrupt level set register 2 Interrupt level set register 3 Interrupt level set register 4 Interrupt test register SMR SDR PURR0 PURR1 PURR2 PURR3 PURR4 WREN WROR PURR6 Serial mode register (SIO) Serial data register (SIO) Port 0 pull-up resistor register Port 1 pull-up resistor register Port 2 pull-up resistor register Port 3 pull-up resistor register Port 4 pull-up resistor register Wild register enable register Wild register data test register Port 6 pull-up resistor register (Vacancy) W W W W Access prohibited 11111111B 11111111B 11111111B 11111111B XXXXX00B Register abbreviation IBSR IBCR ICCR IADR IDAR EIE2 EIF2 RCR1 RCR2 CKR Register name I2C bus status register I2C bus control register I2C clock control register I2C address register I2C data register External interrupt 2 control register External interrupt 2 flag register 6-bit PPG control register 1 6-bit PPG control register 2 Clock output control register (Vacancy) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B XXXXXXXXB 11111111B 11111111B 11111111B 11111111B 1111--11B --000000B --000000B ---11111B Read/Write R R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 000XXXXXB -XXXXXXXB XXXXXXXXB 00000000B -------0B 00000000B 0X000000B ------00B 540 APPENDIX A I/O Maps Table A-2 Extended I/O area Address C80H C81H C82H C83H C84H C85H C86H C87H C88H C89H C8AH C8BH C8CH C8DH C8EH C8FH C90H C91H Register abbreviation WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WRARH3 WRARL3 WRDR3 WRARH4 WRARL4 WRDR4 WRARH5 WRARL5 WRDR5 WRARH6 WRARL6 WRDR6 Register name Upper address set register 1 Lower address set register 1 Data set register 1 Upper address set register 2 Lower address set register 2 Data set register 2 Upper address set register 3 Lower address set register 3 Data set register 3 Upper address set register 4 Lower address set register 4 Data set register 4 Upper address set register 5 Lower address set register 5 Data set register 5 Upper address set register 6 Lower address set register 6 Data set register 6 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Explanation of read/write * * * R/W: Read and write possible R: Read only W: Write only Explanation of initial values * * * * * 0: The initial value of this bit is "0." 1: The initial value of this bit is "1." X: The initial value of this bit is undefined. M: The initial value of this bit is the mask option. -: This bit is unused. Note: Do not use the vacancy. 541 APPENDIX B Overview of Instructions APPENDIX B Overview of Instructions Appendix B describes the instructions used by the F2MC-8L. B.1 "Overview of F2MC-8L Instructions" B.2 "Addressing" B.3 "Special Instructions" B.4 "Bit Manipulation Instructions (SETB, CLRB)" B.5 "F2MC-8L Instructions" B.6 "Instruction Map" 542 APPENDIX B Overview of Instructions B.1 Overview of F2MC-8L Instructions The F2MC-8L supports 140 types of instructions. I Overview of F2MC-8L Instructions The F2MC-8L has 140 1-byte machine instructions (256-byte instruction map). An instruction code consists of an instruction and zero or more operands that follow. Figure B.1-1 "Relationship between the Instruction Codes and the Instruction Map" shows the relationship between the instruction codes and the instruction map. Figure B.1-1 Relationship between the Instruction Codes and the Instruction Map 0 to 2 bytes, which are assigned depending on the instruction 1 byte Instruction code Machine instruction Operand Operand Higher 4 bits [Instruction map] * * * * The instructions are classified into four types: transfer, arithmetic, branch, and other. A variety of addressing methods is available. One of ten addressing modes can be selected depending on the selected instruction and specified operand(s). Bit manipulation instructions are provided. operations. They can be used for read-modify-write Some instructions are used for special operations. Lower 4 bits 543 APPENDIX B Overview of Instructions I Symbols used with Instructions Table B.1-1 "Symbols in the Instruction List" lists the symbols used in the instruction code descriptions in Appendix B. Table B.1-1 Symbols in the Instruction List Symbol dir off ext #vct #d8 #d16 dir:16 rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri X (X) ((X)) Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8 bits:3 bits) Branch relative address (8 bits) Register indirect addressing (examples: @A, @IX, @EP) Accumulator (8 or 16 bits, which are determined depending on the instruction being used) Higher 8 bits of the accumulator (8 bits) Lower 8 bits of the accumulator (8 bits) Temporary accumulator (8 or 16 bits, which are determined depending on the instruction being used) Higher 8 bits of the temporary accumulator (8 bits) Lower 8 bits of the temporary accumulator (8 bits) Index register (16 bits) Extra pointer (16 bits) Program counter (16 bits) Stack pointer (16 bits) Program status (16 bits) Either accumulator or index register (16 bits) Condition code register (8 bits) Register bank pointer (5 bits) General-purpose register (8 bits, i = 0 to 7) X is immediate data (8 or 16 bits, which are determined depending on the instruction being used). The content of X is to be accessed (8 or 16 bits, which are determined depending on the instruction being used). The address indicated by the X is to be accessed (8 or 16 bits, which are determined depending on the instruction being used). Meaning 544 APPENDIX B Overview of Instructions B.2 Addressing The F2MC-8L has the following ten addressing modes: * Direct addressing * Extended addressing * Bit direct addressing * Index addressing * Pointer addressing * General-purpose register addressing * Immediate addressing * Vector addressing * Relative addressing * Inherent addressing I Explanation of Addressing Direct addressing Direct addressing is indicated by dir in the instruction list. This addressing is used to access the area between 0000H and 00FFH. In this addressing mode, the higher byte of the address is 00H and the lower byte is specified by the operand. Figure B.2-1 "Example of Direct Addressing" shows an example. Figure B.2-1 Example of Direct Addressing MOV 12H, A 0 0 1 2 H 4 5H A 4 5H Extended addressing Extended addressing is indicated by ext in the instruction list. This addressing is used to access the entire 64-KB area. In this addressing mode, the first operand specifies the higher byte of the address, and the second operand specifies the lower byte. Figure B.2-2 "Example of Extended Addressing" shows an example. Figure B.2-2 Example of Extended Addressing MOVW A, 1 2 3 4H 1 2 3 4H 5 6H 1 2 3 5H 7 8H A 5 6 7 8H 545 APPENDIX B Overview of Instructions Bit direct addressing Bit direct addressing is indicated by dir:b in the instruction list. This addressing is used to access a particular bit in the area between 0000H and 00FFH. In this addressing mode, the higher byte of the address is 00H and the lower byte is specified by the operand. The bit position at the address is specified by the lower three bits of the operation code. Figure B.2-3 "Example of Bit Direct Addressing" shows an example. Figure B.2-3 Example of Bit Direct Addressing SETB 34H : 2 0 0 3 4H 7 6 543 21 0 XXXXX1XXB Index addressing Index addressing is indicated by @IX+off in the instruction list. This addressing is used to access the entire 64-KB area. In this addressing mode, the address is the value resulting from sign-extending the contents of the first operand and adding them to IX (index register). Figure B.2-4 "Example of Index Addressing" shows an example. Figure B.2-4 Example of Index Addressing MOVW A, @IX+5 AH IX 2 7 A 5 H 2 7 F FH 1 2H 2 8 0 0 H 3 4H A 1 2 3 4H Pointer addressing Pointer addressing is indicated by @EP in the instruction list. This addressing is used to access the entire 64-KB area. In this addressing mode, the address is contained in EP (extra pointer). Figure B.2-5 "Example of Pointer Addressing" shows an example. Figure B.2-5 Example of Pointer Addressing MOVW A, @EP EP 2 7 A 5H 2 7 A5H 1 2 H 2 7 A6 H 3 4 H A 1 2 3 4H General-purpose register addressing General-purpose register addressing is indicated by Ri in the instruction list. This addressing is used to access a register bank in the general-purpose register area. In this addressing mode, the higher byte of the address is always 01 and the lower byte is specified based on the contents of RP (register bank pointer) and the lower three bits of the operation code. Figure B.2-6 "Example of general-purpose register addressing" shows an example. Figure B.2-6 Example of General-purpose Register Addressing MOV A, R 6 0 1 5 6H ABH A ABH RP 0 1 0 1 0 B 546 APPENDIX B Overview of Instructions Immediate addressing Immediate addressing is indicated by #d8 in the instruction list. This addressing is used when immediate data is required. In this addressing mode, the operand is used as immediate data. Whether the data is specified in bytes or words is determined by the operation code. Figure B.2-7 "Example of Immediate Addressing" shows an example. Figure B.2-7 Example of Immediate Addressing MOV A, #56H A 5 6H Vector addressing Vector addressing is indicated by vct in the instruction list. This addressing is used to branch to a subroutine address stored in the vector table. In this addressing mode, vct information is contained in the operation codes, and the corresponding table addresses are created as shown in Table B.2-1 "Vector Table Addresses Corresponding to vct". Table B.2-1 Vector Table Addresses Corresponding to vct #vct 0 1 2 3 4 5 6 7 Vector table address (higher address:lower address of branch destination) FFC0H : FFC1H FFC2H : FFC3H FFC4H : FFC5H FFC6H : FFC7H FFC8H : FFC9H FFCAH : FFCBH FFCCH : FFCDH FFCEH : FFCFH Figure B.2-8 "Example of Vector Addressing" shows an example. Figure B.2-8 Example of Vector Addressing CALLV #5 (Conversion) F F C AH F F C BH F EH D CH PC F E D CH 547 APPENDIX B Overview of Instructions Relative addressing Relative addressing is indicated by rel in the instruction list. This addressing is used to branch to within the area between the address 128 bytes higher and that 128 bytes lower relative to the address contained in the PC (program counter). In this addressing mode, the result of a signed addition of the contents of the operand to the PC is stored in the PC. Figure B.2-9 "Example of Relative Addressing" shows an example. Figure B.2-9 Example of Relative Addressing BNE F EH Previous PC 9 A B CH 9ABCH + FFFEH Current PC 9 A B AH In this example, a branch to the address of the BNE operation code occurs, thus resulting in an infinite loop. Inherent addressing Inherent addressing is indicated as the addressing without operands in the instruction list. This addressing is used to perform the operation determined by the operation code. In this addressing mode, different operations are performed via different instructions. Figure B.2-10 "Example of Inherent Addressing" shows an example. Figure B.2-10 Example of Inherent Addressing NOP Previous PC 9 A B CH Current PC 9 A B DH 548 APPENDIX B Overview of Instructions B.3 Special Instructions This section describes the special instructions used for other than addressing. I Special Instructions JMP @A This instruction sets the contents of A (accumulator) to PC (program counter) as the address, and causes a branch to that address. One of the N branch destination addresses is selected from a table, and then transferred to A. The instruction can be executed to perform N-branch processing. Figure B.3-1 "JMP @A" shows a summary of the instruction. Figure B.3-1 JMP @A (Before execution) A Previous PC 1 2 3 4H X X X XH (After execution) A Current PC 1 2 3 4H 1 2 3 4H MOVW A, PC This instruction performs the operation which is the reverse of that performed by JMP @A. That is, the instruction stores the contents of PC in A. When the instruction is executed in the main routine, so that a specific subroutine is called, whether A contains a predetermined value can be checked by the subroutine. This can be used to determine that the branch source is not any unexpected section of the program and to check for program runaway. Figure B.3-2 "MOVW A, PC" shows a summary of the instruction. Figure B.3-2 MOVW A, PC A Previous PC X X X XH 1 2 3 4H A Current PC 1 2 3 4H 1 2 3 4H After the MOVW A, PC instruction is executed, A contains the address of the operation code of the next instruction, rather than the address of the operation code of MOVW A, PC. Accordingly, Figure B.3-2 "MOVW A, PC" shows that A contains 1234H, which is the address of the operation code of the instruction that follows MOVW A, PC. 549 APPENDIX B Overview of Instructions MULU A This instruction performs an unsigned multiplication of AL (lower eight bits of the accumulator) and TL (lower eight bits of the temporary accumulator), and stores the 16-bit result in A. The contents of T (temporary accumulator) do not change. The contents of AH (higher eight bits of the accumulator) and TH (higher eight bits of the temporary accumulator) before execution of the instruction are not used for the operation. The instruction does not change the flags, and therefore care must be taken when a branch may occur depending on the result of a multiplication. Figure B.3-3 "MULU" shows a summary of the instruction. Figure B.3-3 MULU (Before execution) A T 5 6 7 8H 1 2 3 4H (After execution) A T 1 8 6 0H 1 2 3 4H DIVU A This instruction divides the 16-bit value in T by the unsigned 8-bit value in AL, and stores the 8bit result and the 8-bit remainder in AL and TL, respectively. A value of 0 is set to both AH and TH. The contents of AH before execution of the instruction are not used for the operation. An unpredictable result is produced from data that results in more than eight bits. In addition, there is no indication of the result having more than eight bits. Therefore, if it is likely that data will cause a result of more than eight bits, the data must be checked to ensure that the result will not have more than eight bits before it is used. The instruction does not change the flags, and therefore care must be taken when a branch may occur depending on the result of a division. Figure B.3-4 "DIVU A" shows a summary of the instruction. Figure B.3-4 DIVU A (Before execution) A T 5 6 7 8H 1 8 6 2H A T (After execution) 0 0 3 4H 0 0 0 2H XCHW A, PC This instruction swaps the contents of A and PC, resulting in a branch to the address contained in A before execution of the instruction. After the instruction is executed, A contains the address that follows the address of the operation code of MOVW A, PC. This instruction is effective especially when it is used in the main routine to specify a table for use in a subroutine. Figure B.3-5 "XCHW A, PC" shows a summary of the instruction. Figure B.3-5 XCHW A, PC (Before execution) A 5 6 7 8H A (After execution) 1 2 3 5H PC 1 2 3 4H PC 5 6 7 8H 550 APPENDIX B Overview of Instructions After the XCHW A, PC instruction is executed, A contains the address of the operation code of the next instruction, rather than the address of the operation code of XCHW A, PC. Accordingly, Figure B.3-5 "XCHW A, PC" shows that A contains 1235H, which is the address of the operation code of the instruction that follows XCHW A, PC. This is why 1235H is stored instead of 1234H. Figure B.3-6 "Example of Using XCHW A, PC" shows an assembly language example. Figure B.3-6 Example of Using XCHW A, PC (Main routine) (Subroutine) MOVW XCHW DB MOVW A, #PUTSUB A, PC 'PUT OUT DATA', EOL A, 1234 H PUTSUB PTS1 XCHW A, EP PUSHW A MOV A, @EP INCW EP MOV IO, A CMP A, #EOL BNE PTS1 POPW A XCHW A, EP JMP @A Output table data here CALLV #vct This instruction is used to branch to a subroutine address stored in the vector table. The instruction saves the return address (contents of PC) in the location at the address contained in SP (stack pointer), and uses vector addressing to cause a branch to the address stored in the vector table. Because CALLV #vct is a 1-byte instruction, the use of this instruction for frequently used subroutines can reduce the entire program size. Figure B.3-7 "Example of Executing CALLV #3" shows a summary of the instruction. Figure B.3-7 Example of Executing CALLV #3 (Before execution) PC SP 5 6 7 8H 1 2 3 4H X XH X XH (-2) PC SP (After execution) F E D CH 1 2 3 2H 5 6H 7 9H 1 2 3 2H 1 2 3 3H 1 2 3 2H 1 2 3 3H F F C 6H F F C 7H F EH D CH F F C 6H F F C 7H F EH D CH After the CALLV #vct instruction is executed, the contents of PC saved on the stack area are the address of the operation code of the next instruction, rather than the address of the operation code of CALLV #vct. Accordingly, Figure B.3-7 "Example of Executing CALLV #3" shows that the value saved in the stack (1232H and 1233H) is 5679H, which is the address of the operation code of the instruction that follows CALLV #vct (return address). 551 APPENDIX B Overview of Instructions B.4 Bit Manipulation Instructions (SETB, CLRB) Some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual. I Read-modify-write Operation By using these bit manipulation instructions, only the specified bit in a register or RAM location can be set to 1 (SETB) or cleared to 0 (CLRB). However, as the CPU operates on data in 8-bit units, the actual operation (read-modify-write operation) involves a sequence of steps: 8-bit data is read, the specified bit is changed, and the data is written back to the location at the original address. Table B.4-1 "Bus Operation for Bit Manipulation Instructions" shows bus operation for bit manipulation instructions. Table B.4-1 Bus operation for Bit Manipulation Instructions CODE A0 to A7 MNEMONIC CLRB dir:b TO 4 Cycle 1 2 A8 to AF SETB dir:b 3 4 Address bus N+1 dir address dir address N+2 Data bus dir Data Data Next instruction RD 0 0 1 0 WR 1 1 0 1 RMW 0 1 0 0 I Read Operation Upon the Execution of Bit Manipulation Instructions For some I/O ports and for the interrupt request flag bits, the value to be read differs between a normal read operation and a read-modify-write operation. I/O ports (during a bit manipulation) From some I/O ports, an I/O pin value is read during a normal read operation, while an output latch value is read during a bit manipulation. This prevents the other output latch bits from being changed accidentally, regardless of the I/O directions and states of the pins. Interrupt request flag bits (during a bit manipulation) An interrupt request flag bit functions as a flag bit indicating whether an interrupt request exists during a normal read operation. However, 1 is always read from this bit during a bit manipulation. This prevents the flag from being cleared accidentally by a value of 0 which would otherwise be written to the interrupt request flag bit when another bit is manipulated. 552 APPENDIX B Overview of Instructions B.5 F2MC-8L Instructions Table B.5-1 "Transfer Instructions" to Table B.5-4 "Other Instructions" list the instructions used with the F2MC-8L. I Transfer Instructions Table B.5-1 Transfer Instructions No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNEMONIC MOV dir, A MOV @IX+off, A MOV ext, A MOV @EP, A MOV Ri, A MOV A, #d8 MOV A, dir MOV A, @IX+off MOV A, ext MOV A, @A MOV A, @EP MOV A, Ri MOV dir, #d8 MOV @IX+off, #d8 MOV @EP, #d8 MOV Ri, #d8 MOVW dir, A MOVW @IX+off, A MOVW ext, A MOVW @EP, A MOVW EP, A MOVW A, #d16 MOVW A, dir 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 Operation (dir)<--(A) ((IX)+off)<--(A) (ext)<--(A) ((EP))<--(A) (Ri)<--(A) (A)<--d8 (A)<--(dir) (A)<--((IX)+off) (A)<--(ext) (A)<--((A)) (A)<--((EP)) (A)<--(Ri) (dir)<--d8 ((IX)+off)<--d8 ((EP))<--d8 (Ri)<--d8 (dir)<--(AH), (dir+1)<--(AL) ((IX)+off )<--(AH), ((IX)+off+1)<--(AL) (ext)<--(AH), (ext+1)<--(AL) ((EP))<--(AH), ((EP)+1)<--(AL) (EP)<--(A) (A)<--d16 (AH)<--(dir), (AL)<--(dir+1) TL AL AL AL AL AL AL AL AL AL TH AH AH AH dH dH N + + + + + + + + + Z + + + + + + + + + V - C - OP CODE 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 553 APPENDIX B Overview of Instructions Table B.5-1 Transfer Instructions (Continued) No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 MNEMONIC MOVW A, @IX+off MOVW A, ext MOVW A, @A MOVW A, @EP MOVW A, EP MOVW EP, #d16 MOVW IX, A MOVW A, IX MOVW SP, A MOVW A, SP MOV @A, T MOVW @A, T MOVW IX, #d16 MOVW A, PS MOVW PS, A MOVW SP, #d16 SWAP SETB dir:b CLRB dir:b XCH A, T 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Operation (AH)<--((IX)+off), (AL)<--((IX)+off+1) (AH)<--(ext), (AL)<--(ext+1) (AH)<--((A)), (AL)<--((A)+1) (AH)<--((EP)), (AL)<--((EP)+1) (A)<--(EP) (EP)<--d16 (IX)<--(A) (A)<--(IX) (SP)<--(A) (A)<--(SP) ((A))<--(T) ((A))<--(TH), ((A)+1)<--(TL) (IX)<--d16 (A)<--(PS) (PS)<--(A) (SP)<--d16 (AH)<-- -->(AL) (dir):b <--1 (dir):b <--0 (AL)<-- -->(TL) (A)<-- -->(T) (A)<-- -->(EP) (A)<-- -->(IX) (A)<-- -->(SP) (A)<--(PC) TL AL AL AL AL AL AL - TH AH AH AH AH AH - AH dH dH dH dH dH dH dH dH AL dH dH dH dH dH N + + + + + - Z + + + + + - V + - C + - OP CODE C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 XCHW A, T XCHW A, EP XCHW A, IX XCHW A, SP MOVW A, PC Note: In automatic transfer to T during byte transfer to A, AL is transferred to TL. If an instruction has two or more operands, they are assumed to be saved in the order indicated by MNEMONIC. 554 APPENDIX B Overview of Instructions I Arithmetic Instructions Table B.5-2 Arithmetic Operation Instructions No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MNEMONIC ADDC A, Ri ADDC A, #d8 ADDC A, dir ADDC A, @IX+off ADDC A, @EP ADDCW A ADDC A SUBC A, Ri SUBC A, #d8 SUBC A, dir SUBC A, @IX+off SUBC A, @EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation (A)<--(A)+(Ri)+C (A)<--(A)+d8+C (A)<--(A)+(dir)+C (A)<--(A)+((IX)+off)+C (A)<--(A)+((EP))+C (A)<--(A)+(T)+C (AL)<--(AL)+(TL)+C (A)<--(A)-(Ri)-C (A)<--(A)-d8-C (A)<--(A)-(dir)-C (A)<--(A)-((IX)+off)-C (A)<--(A)-((EP))-C (A)<--(T)-(A)-C (AL)<--(TL)-(AL)-C (Ri)<--(Ri)+1 (EP)<--(EP)+1 (IX)<--(IX)+1 (A)<--(A)+1 (Ri)<--(Ri)-1 (EP)<--(EP)-1 (IX)<--(IX)-1 (A)<--(A)-1 (A)<--(AL)x(TL) (A)<--(T)/(AL), MOD -->(T) (A)<--(A) (A)<--(A) (A)<--(A) (TL)-(AL) (T)-(A) (T) (T) (T) TL dL - TH 00 - AH - N + + + + + + + + + + + + + + + + + + + + + + + + Z + + + + + + + + + + + + + + + + + + + + + + + + V + + + + + + + + + + + + + + + + - C + + + + + + + + + + + + + + + + + OP CODE 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 dH - dH - dH - dH dH 00 dH dH dH - R R R + + - 29 30 C --> A 555 APPENDIX B Overview of Instructions Table B.5-2 Arithmetic Operation Instructions (Continued) No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 MNEMONIC ROLC A CMP A, #d8 CMP A, dir CMP A, @EP CMP A, @IX+off CMP A, Ri DAA DAS XOR A XOR A, #d8 XOR A, dir XOR A, @EP XOR A, @IX+off XOR A, Ri AND A AND A, #d8 AND A, dir AND A, @EP AND A, @IX+off AND A, Ri OR A OR A, #d8 OR A, dir OR A, @EP OR A, @IX+off OR A, Ri CMP dir, #d8 CMP @EP, #d8 CMP @IX+off, #d8 CMP Ri, #d8 INCW SP DECW SP 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 1 2 Operation TL - TH - AH - N + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - Z + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - V + + + + + + + C + + + + + + + + + + + + - OP CODE 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 C <-- A (A)-d8 (A)-(dir) (A)-((EP)) (A)-((IX)+off) (A)-(Ri) decimal adjust for addition decimal adjust for subtraction (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (A)<--(AL) (dir)-d8 ((EP))-d8 ((IX)+off)-d8 (Ri)-d8 (SP)<--(SP)+1 (SP)<--(SP)-1 (TL) d8 (dir) ((EP)) ((IX)+off) (Ri) (TL) d8 (dir) ((EP)) ((IX)+off) (Ri) (TL) d8 (dir) ((EP)) ((IX)+off) (Ri) R R R R R R R R R R R R R R R R R R + + + + - 49 50 51 1 1 2 2 1 2 1 3 2 3 2 1 1 52 53 54 55 56 57 58 59 60 61 62 556 APPENDIX B Overview of Instructions I Branch Instructions Table B.5-3 Branch Instructions No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MNEMONIC BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir:b, rel BBS dir:b, rel JMP @A JMP ext CALLV #vct CALL ext XCHW A, PC RET RETI 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 Operation if Z=1 then PC<--PC+rel if Z=0 then PC<--PC+rel if C=1 then PC<--PC+rel if C=0 then PC<--PC+rel if N=1 then PC<--PC+rel if N=0 then PC<--PC+rel if V if V N=1 then PC<--PC+rel N=0 then PC<--PC+rel TL - TH - AH - N - Z + V - C OP CODE - FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if (dir:b)=0 then PC<--PC+rel if (dir:b)=1 then PC<--PC+rel (PC)<--(A) (PC)<--ext vector call subroutine call (PC)<--(A), (A)<--(PC)+1 return from subroutine return from interrupt - - - - + - - - - - - - - - dH - restore 557 APPENDIX B Overview of Instructions I Other Instructions Table B.5-4 Other Instructions No. 1 2 3 4 5 6 7 8 9 MNEMONIC PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 4 4 4 4 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 Operation TL - TH - AH - N - Z - V - C OP CODE - 40 50 41 51 00 81 91 80 90 dH - R S - - - - - - - 558 B.6 H 3 PUSHW MOV MOVW CLRI INCW DECW JMP MOVW @A A, PC MOVW A, SP MOVW A, IX MOVW A, EP XCHW A, PC XCHW A, SP MOVW IX, #d16 MOVW @EP, A DEC R0 INC R1 BBS dir : 2 dir : 2, rel SETB SETB R4, #d8 CMP R5, #d8 MOV A, R6 OR A, R7 A, R7 R6, #d8 MOV R7, #d8 R5, #d8 CMP R6, #d8 CMP R7, #d8 SETB SETB SETB BBS dir : 3 dir : 3, rel BBS dir : 4 dir : 4, rel BBS dir : 5 dir : 5, rel BBS dir : 6 dir : 6, rel BBS dir : 7 dir : 7, rel INC R7 INC R6 DEC R7 INC R5 DEC R6 CALLV #7 INC R4 DEC R5 CALLV #6 BLT rel INC R3 DEC R4 CALLV #5 BGE rel INC R2 DEC R3 CALLV #4 BZ rel DEC R2 CALLV #3 BNZ rel DEC R1 CALLV #2 BN rel R0 CALLV #1 BP rel EP, #d16 CALLV #0 BC rel BNC rel XCHW A, IX XCHW A, EP MOVW SP SP, A MOVW IX IX, A MOVW EP EP, A MOVW A, #d16 MOVW SP, #d16 MOVW ext, A MOVW dir, A MOVW MOVW DECW EP MOVW A, ext MOVW A, dir MOVW MOVW A, @EP INC DECW IX INCW A DECW SP INCW A INCW dir : 0 dir : 0, rel CLRC dir : 1 dir : 1, rel MOV A @A, T MOVW A @A, T DAA A, #d8 OR MOV A, dir dir, #d8 MOV BBC dir : 6 dir : 6, rel A, @IX+d @IX+d, A CLRB BBC dir : 7 dir : 7, rel SETB BBS dir : 0 dir : 0, rel SETB BBS dir : 1 dir : 1, rel SETB MOV A, @EP @EP#, d8 @EP#, d8 OR MOV A, R0 R0, #d8 MOV A, R1 R1, #d8 MOV A, R2 OR A, R3 A, R3 OR A, R4 A, R4 OR A, R5 A, R5 OR A, R6 AND A, R7 AND A, R6 XOR R7, A MOV AND A, R5 XOR R6, A MOV A, R7 R4, #d8 MOV CMP R3, #d8 AND A, R4 XOR R5, A MOV A, R6 R3, #d8 MOV CMP R2, #d8 R2, #d8 CMP OR A, R2 AND A, R3 XOR R4, A MOV A, R5 R1, #d8 CMP OR A, R1 AND A, R2 XOR R3, A MOV A, R4 R0, #d8 A, R0 AND A, R1 XOR R2, A MOV A, R3 CMP CMP CMP CLRB OR A, @IX+d @IX+d,#d8 @IX+d,#d8 OR dir, #d8 dir : 5 dir : 5, rel BBC A, dir AND AND A, @EP AND A, R0 XOR R1, A MOV A, R2 CMP CLRB dir : 4 dir : 4, rel DAS BBC CLRB OR A, #d8 AND A, dir XOR XOR A, @EP XOR R0, A MOV A, R1 A, @A dir : 3 dir : 3, rel MOVW BBC CLRB A, @A ORW A AND A, #d8 MOV dir, A MOV MOV @EP, A MOV A, R0 XOR dir : 2 dir : 2, rel MOV BBC CLRB SETC BBC CLRB SETI BBC A, ext A, PS MOVW ext, A PS, A OR A ANDW A XOR AND A XORW A, T MOV IX XOR A, T XCHW A A, #d8 A, dir CLRB A POPW IX XCH A A PUSHW addr16 POPW 4 5 6 7 8 9 A B C D E F L 0 1 2 I Instruction map 0 NOP SWAP RET RETI 1 MULU DIVU JMP CALL A A addr16 2 ROLC CMP ADDC SUBC A A A Instruction Map 3 RORC CMPW ADDCW SUBCW A A A Table B.6-1 F2MC-8L Instruction Map 4 MOV CMP ADDC SUBC A, #d8 A, #d8 A, #d8 5 MOV CMP ADDC SUBC A, dir A, dir A, dir 6 MOV CMP ADDC SUBC A, @IX+d A, @EP A, @IX+d A, @IX+d A, @IX+d @IX+d, A A, @IX+d A, @IX+d 7 MOV CMP ADDC SUBC A, @EP A, @EP A, @EP 8 MOV CMP ADDC SUBC A, R0 A, R0 A, R0 9 MOV CMP ADDC SUBC A, R1 A, R1 A, R1 A MOV CMP ADDC SUBC A, R2 A, R2 A, R2 B MOV CMP ADDC SUBC A, R3 A, R3 A, R3 C MOV CMP ADDC SUBC A, R4 A, R4 A, R4 D MOV CMP ADDC SUBC A, R5 A, R5 A, R5 Table B.6-1 "F2MC-8L Instruction Map" shows the F2MC-8L instruction map. E MOV CMP ADDC SUBC A, R6 A, R6 A, R6 APPENDIX B Overview of Instructions F MOV CMP ADDC SUBC A, R7 A, R7 A, R7 559 APPENDIX C Mask Options APPENDIX C Mask Options Table C-1 "Mask options" lists the mask options of the MB89530/530H/530A. I Mask options Table C-1 Mask options MB89535A/535AC MB89537/537H/537A MB89537C/537HC/537AC MB89538/538H/538A MB89538C/538HC/538AC Specified at ordering masking MB89F538L-101 MB89F538L-201 MB89F538-101 MB89F538-201 Setting not possible Model No. Specification method Selection of main clock oscillation stabilization wait time (for FCH = 10 MHz) Approx. 214/FCH (approx. 1.6 ms) Approx. 217/FCH (approx. 13.1 ms) Approx. 218/FCH (approx. 26.2 ms) Clock mode selection * Dual-clock system mode * Single-clock system mode MB89P538-101 MB89P538-201 MB89PV530-101 MB89PV530-201 Setting not possible Setting not possible 1 Selectable 218/FCH 218/FCH (Approx. 26.2 ms) (Approx. 26.2 ms) 218/FCH (Approx. 26.2 ms) 2 Selectable -101: Single-clock system mode -201: Dual-clock system mode FCH: Main clock frequency 560 APPENDIX D Write Specifications for the One-Time PROM and EPROM Microcomputer APPENDIX D Write Specifications for the One-Time PROM and EPROM Microcomputer MB89P538 has PROM mode that becomes a function equivalent to MBM27C1001. In this mode, writing is possible with the general-purpose ROM writer using the dedicated adapter. However, note that the electronic signature mode cannot be used. I ROM writer adapter Some ROM writers can write data more stably when a capacitor of about 0.1 F is inserted between VCC and VSS. Table D-1 "ROM writer adapters" lists the ROM writer adapters. Table D-1 ROM writer adapters Product name MB89P538-101PF-G-BND MB89P538-201PF-G-BND MB89P538-101PFM-G-BND MB89P538-201PFM-G-BND MB89P538-101P-G-SH MB89P538-201P-G-SH Package FTP-64P-M06 FTP-64P-M09 DIP-64P-M01 Compatible adapter ROM-64QF-32DP-8LA2(*1) ROM-64QF2-32DP-8LA ROM-64SD-32DP-8LA2(*1) Contact: Sunhayato Corporation Tel. 03-3986-0403 *1 Use the adapters of version 3 or later. I Memory map in EPROM mode Figure D-1 "Memory map in EPROM mode" shows the memory map in EPROM mode. The PROM option is not available. 561 APPENDIX D Write Specifications for the One-Time PROM and EPROM Microcomputer Figure D-1 Memory map in EPROM mode In ordinary operation mode In EPROM mode (Associated address on the EPROM writer) 0000H Not available 0000H 0080H 0100H 0200H 0880H I/O RAM Generalpurpose register Not available 4000H ROM FFFFH FFFFH 4000H Program (EPROM) Not 1FFFFH available I Recommended screening conditions For a product with a blank one-time PROM microcomputer program, Fujitsu recommends using high-temperature aging as the screening method before installation. Figure D-2 "Flow of screening" shows the flow of screening. Figure D-2 Flow of screening Program, verify High-temperature aging + 150C, 48 H Read Installation I Programming yield The all-bit programming at Fujitsu shipping test cannot be performed for a product with a blank one-time PROM microcomputer program. Therefore, a programming yield of 100% may not always be guaranteed. 562 APPENDIX E EPROM with Piggyback/Evaluation Chip APPENDIX E EPROM with Piggyback/Evaluation Chip This section describes how to write EPROM to be mounted on the piggyback/ evaluation chip. I Usable EPROM MBM27C512-20TV I Programming socket adapter To write data into EPROM with the ROM writer, use the programming socket adapter (manufactured by Sunhayato Corporation) shown in Table E-1 "Programming socket adapter." Table E-1 Programming socket adapter Package LCC-32 (rectangle) Adapter socket model ROM-32LC-28DP-YG Contact: Sunhayato Corporation Tel. 03-3986-0403 I Memory space Figure E-1 Memory map of the piggyback/evaluation chip In ordinary operation mode (associated address on the ROM writer) 0000H 0000H I/O 0080H Not RAM available 0880H Not available 4000H 4000H PROM 48 KB EPROM FFFFH FFFFH I Method of writing to EPROM 1. Set the EPROM writer to MBM27C512. 2. Load program data to 4000H to FFFFH of the EPROM writer. 3. Write 4000H to FFFFH with the EPROM writer. 563 APPENDIX F Pin Statuses of the MB89530/530H/530A Series APPENDIX F Pin Statuses of the MB89530/530H/530A Series Table F-1 "Pin status in each mode" lists the pin statuses of the MB89530/530H/530A series. I Pin statuses in each mode Table F-1 Pin status in each mode Pin name Normal operation Sleep mode Stop mode SPL = "0" Oscillation circuit input Oscillation circuit input SPL = "1" Watch mode SPL = "0" SPL = "1" Oscillation circuit input Mode input Reset input Reset ongoing X0,X1 Hi-z Hi-z Hi-z Hi-z MOD0 MOD1 RST Mode input Mode input Mode input Mode input Mode input Mode input Reset input Reset input Retention/ peripheral equipment I/O Reset input Reset input Reset input Reset input P00 to P17 Port/peripheral equipment I/O Retention Hi-z Retention Hi-z Hi-z P20/PWCK P21/PPG01 to P22/ PPG02 P23 to P27 P30/PPG03/ MCO P31/ SCK1(UCK1) /LMCO P32/ SO1(UO1) P33/SI1(UI1) P34/PTO2 P35/PWC P36/WTO P37/PTO1 Retention/ peripheral equipment I/O "H" (for pullup) Hi-z (for other than pull-up) "H" (for pullup) Hi-z (for other than pull-up) Port/peripheral equipment I/O Retention Retention Hi-z 564 APPENDIX F Pin Statuses of the MB89530/530H/530A Series Table F-1 Pin status in each mode (Continued) Pin name Normal operation Sleep mode Stop mode SPL = "0" P40/INT20/ EC P41/INT21/ SCK2 P42/INT22/ SO2/SDA P43/INT23/ SI2/SCL P44/INT24/ UCK2 P45/INT25/ UO2 P46/INT26/ UI2 P47/INT27/ ADST "H" (for pullup) Hi-z (for other than pull-up) "H" (for pullup) Hi-z (for other than pull-up)/ external interrupt 1 input "H" (for pullup) Hi-z (for other than pull-up)/ external interrupt 1 input "H" (for pullup) Hi-z (for other than pull-up) "H" (for pullup) Hi-z (for other than pull-up) "H" (for pullup) Hi-z (for other than pull-up)/ external interrupt 1 input Port/external interrupt 2 input/ peripheral equipment I/O Retention/ external interrupt 2 input/ peripheral equipment I/O Retention/ external interrupt 2 input SPL = "1" Watch mode SPL = "0" SPL = "1" Reset ongoing "H" (for pullup) Hi-z (for other than pull-up)/ external interrupt 2 input Retention/ external interrupt 2 input "H" (for pullup) Hi-z (for other than pull-up)/ external interrupt 2 input Hi-z P50/AN0 to P57/AN7 Port/AD input Retention/AD input Retention Retention Hi-z P60/INT10 to P62/INT12 Port/external interrupt 1 input Retention/ external interrupt 1 input Retention/ external interrupt 1 input Retention/ external interrupt 1 input Hi-z P63/INT13/ X0A Port/external interrupt 1 input/ subclock input Retention/ external interrupt 1 input/ subclock input Retention/ external interrupt 1 input Subclock input Subclock input Oscillation circuit input P64/X1A Port/subclock output Retention/ subclock output Retention Subclock output Subclock output Oscillation circuit output 565 APPENDIX G Troubleshooting APPENDIX G Troubleshooting If a fault occurs, take appropriate action in accordance with the checklist shown below. Alternatively, software may have caused the fault. Therefore, read the manual of the software in use together. I Checklist Table G-1 Checklist Symptom Cause Power supply (VCC, GND) is not connected. The electrical characteristics of the input signal for each pin do not meet the specifications. The MOD0 and MOD1 pins are not processed in the operating mode to be used. Action Connect the power supply (VCC, GND). Make sure that the electrical characteristics of the input signal for each pin meet the specifications. Perform the MOD0 and MOD1 pin processing. When oscillation is ongoing, check it to see whether the frequency of the oscillator being connected is used. If oscillation is not ongoing, the status may have been changed to stop mode of the standby mode. Check the program. If operation is unstable even if power is turned on repeatedly, the initial value may not be set yet. Check mark entry The microcomputer operation is not normal. The oscillator has been connected. However, no oscillation is made at poweron and reset. The microcomputer was operating during evaluation made by the tool. However, it does not operate for the one-time ROM product. Each register and RAM are not initialized yet. 566 APPENDIX G Troubleshooting I Items to be confirmed for inquiry For an inquiry, confirm the following and consult a person in charge of sales or a special agent: 1. Confirm the differences in operation between the normal and abnormal statuses, at the pin level (waveforms). 2. Confirm the frequency of generation of the problem, conditions, the number of times the problem is generated, and to what degree the problem generation depends on the voltage, temperature, and oscillator frequency. 3. Confirm the operation for the one-time product, mask ROM product, and piggyback/ evaluation product. 567 APPENDIX G Troubleshooting 568 Index Numerics 12-bit PPG control register (PPGC1/PPGC2) ...... 278 12-bit PPG function.............................................. 271 12-bit PPG reload register 1 (PRL11/PRL21) ...... 279 12-bit PPG reload register 2 (PRL12/PRL22) ...... 280 12-bit PPG reload register 3 (PRL13/PRL23) ...... 281 12-bit PPG timer function..................................... 270 12-bit PPG timer pin............................................. 275 12-bit PPG timer pin, block diagram of ................ 275 12-bit PPG timer register ..................................... 277 12-bit PPG timer, block diagram of ...................... 273 12-bit PPG timer, note on using........................... 283 12-bit PPG timer, operation of ............................. 282 12-bit PPG timer, program example of ................ 285 16-bit data on RAM, storage of .............................. 38 16-bit data on stack, storage of.............................. 38 16-bit operand, storage of...................................... 38 16-bit timer/counter and vector table, register related to interrupts of............................................ 297 16-bit timer/counter, block diagram of.................. 289 16-bit timer/counter, block diagram of pin related to ................................................................... 291 16-bit timer/counter, note on using ...................... 303 16-bit timer/counter, pin related to ....................... 291 16-bit timer/counter, register related to ................ 293 2-channel 8-bit PWM timer (PWM timer function), overview of................................................. 183 2-channel 8-bit PWM timer operation in CH12PWM mode.......................................................... 208 2-channel 8-bit PWM timer pin............................. 188 2-channel 8-bit PWM timer pin, block diagram of 189 2-channel 8-bit PWM timer, block diagram of ...... 186 2-channel 8-bit PWM timer, interrupt, register and vector table related to ................................ 201 2-channel 8-bit PWM timer, note on using........... 215 2-channel 8-bit PWM timer, register of ................ 190 6-bit PPG control register 1 (RCR1) .................... 263 6-bit PPG control register 2 (RCR2) .................... 264 6-bit PPG timer function....................................... 256 6-bit PPG timer function 2.................................... 257 6-bit PPG timer pin, block diagram of .................. 261 6-bit PPG timer register ....................................... 262 6-bit PPG timer, block diagram of ........................ 259 6-bit PPG timer, note on using............................. 266 6-bit PPG timer, operation of ............................... 265 6-bit PPG timer, pin of ..........................................261 6-bit PPG timer, program example of ...................268 8-bit receiving operation at operation mode 1 ......385 8-bit serial I/O interrupt, register and vector table for ...................................................................431 8-bit serial I/O pin .................................................423 8-bit serial I/O register ..........................................427 8-bit timer mode program, example of..................216 8-bit transmitting operation at operation mode 1 ..387 A A/D control register 1 (ADC1)...............................349 A/D control register 2 (ADC2)...............................351 A/D conversion function........................................342 A/D conversion function, activating ......................355 A/D conversion function, interrupt for ...................354 A/D conversion function, operation of...................356 A/D conversion function, program example of......359 A/D converter interrupt, register and vector table related to ....................................................354 A/D converter power supply voltage.....................345 A/D converter, block diagram of ...........................343 A/D converter, note on using ................................357 A/D data register (ADDH, ADDL) .........................353 acknowledge.........................................................467 addressing ............................................................467 addressing, explanation of....................................545 arbitration..............................................................468 arithmetic instruction.............................................555 arithmetic operation result bit .................................41 automatic erasing .................................................509 automatic write/erase ...................................510, 511 B baud rate generator reload register (SRC2) .........376 bi-directional serial I/O..........................................440 bit manipulation instruction, read operation upon execution of ................................................552 block diagram of 8-bit serial I/O............................421 block diagram of 8-bit serial I/O pin ......................424 block diagram of clock output ...............................493 block diagram of P30/PPG03/MCO and P31/SCK1 (UCK1)/LMCO ............................................494 block diagram of pin related to the I2C bus interface ...................................................................452 569 block diagram of port 0 and port 1 ....................... 100 block diagram of port 2......................................... 107 block diagram of port 3......................................... 115 block diagram of port 4......................................... 122 block diagram of port 5......................................... 132 block diagram of port 6......................................... 136 block diagram, I2C interface ................................. 447 branch instruction ................................................. 557 C caution when changing edge polarity selection.... 320 CH12PWM mode, program example for .............. 222 checklist ............................................................... 566 CK12 mode program, example of ........................ 218 clock controller, block diagram of ........................... 67 clock generator....................................................... 65 clock mode, operating state of ............................... 72 clock output .......................................................... 492 clock output control register (CKR) ...................... 496 clock output operation, description of...................497 clock output, block diagram of.............................. 493 clock output, note on use of ................................. 498 clock output, register for ....................................... 495 clock supply function ....................................145, 169 clock supply function, operation of ............... 151, 175 clock supply map.................................................... 63 command sequence table .................................... 506 condition code register (CCR), structure of ............ 41 configuration of port 0 and port 1 ........................... 99 configuration of port 2 .......................................... 106 configuration of port 3 .......................................... 114 configuration of port 4 .......................................... 121 configuration of port 5 .......................................... 131 configuration of port 6 .......................................... 135 continuous receiving operation ............................ 386 continuous transmission at operation mode 1......388 counter function.................................................... 288 counter function mode, interrupt in....................... 297 counter function, operation of............................... 300 counter function, program example of.................. 306 D data setting register (WRDR1 to WRDR6) ........... 479 data transfer .........................................................467 DDC select register (DDCR) ........................ 127, 139 dedicated register configuration ............................. 39 dedicated register function ..................................... 39 detecting start bit at receiving operation .............. 382 difference among model .......................................... 8 E edge polarity selection, caution when changing .. 320 EPROM mode, memory map in ........................... 561 erasing all data (erasing chip).............................. 518 erasing chip.......................................................... 518 erasing data (erasing sector) ............................... 519 erasing flash memory........................................... 502 erasing sector ...................................................... 519 external dimension for DIP-64P-M01..................... 15 external dimension for FPT-64P-M03 .................... 16 external dimension for FPT-64P-M06 .................... 17 external dimension for FPT-64P-M09 .................... 18 external dimension for MDP-64C-P02 ................... 19 external dimension for MQP-64C-P01 ................... 20 external interrupt 2 control register (EIE2) ........... 333 external interrupt 2 flag register (EIF2) ................ 335 external interrupt circuit 1 interrupt, register and vector table for ........................................... 320 external interrupt circuit 1 operation, interrupt during ................................................................... 320 external interrupt circuit 1 register........................ 315 external interrupt circuit 1, block diagram of ........ 311 external interrupt circuit 1, block diagram of pin for ................................................................... 314 external interrupt circuit 1, function of .................. 310 external interrupt circuit 1, interrupt source of...... 312 external interrupt circuit 1, operation of................ 321 external interrupt circuit 1, pin for......................... 313 external interrupt circuit 1, program example for . 323 external interrupt circuit 2 (level detection), function of ................................................................... 326 external interrupt circuit 2 interrupt, register and vector table for ........................................... 336 external interrupt circuit 2 operation, interrupt during ................................................................... 336 external interrupt circuit 2, block diagram of ........ 327 external interrupt circuit 2, operation of................ 337 external interrupt circuit 2, pin for......................... 329 external interrupt circuit 2, program example for . 339 external interrupt circuit 2, register for ................. 332 external interrupt control register 1 (EIC1)........... 316 external interrupt control register 2 (EIC2)........... 318 external reset pin function...................................... 59 external reset pin, block diagram of ....................... 59 external shift clock, when using an ...................... 437 570 F F2MC-8L instruction, overview of ........................ 543 flash MCU programmer (when power supplied by user), example of minimum connection for 533 flash memory control status register (FMCS) ...... 504 flash memory feature ........................................... 502 flash memory register .......................................... 502 flash memory write/erase, detailed explanation of..... 514 flash memory, program access to........................ 523 flash memory, writing to ....................................... 516 flash microcomputer programmer (when power supply is supplied from flash MCU programmer), minimum connection example with ............................................................ 535 function of I/O port ................................................. 96 function of port 0 and port 1 register .................... 101 function of port 2 register ..................................... 110 function of port 3 register ..................................... 117 function of port 4 register ..................................... 125 function of port 5 register ..................................... 133 function of port 6 register ..................................... 138 function of UART/SIO .......................................... 362 G gear function (function for switching speed of main clock) ........................................................... 73 general-purpose register area................................ 36 general-purpose register, feature of....................... 46 general-purpose register, structure of.................... 45 H hardware reset (RST), input of............................. 523 hardware sequence flag....................................... 507 high speed UART, function of .............................. 390 high-speed PWM timer function operation........... 206 high-speed UART interrupt, register and vector table address for................................................. 410 high-speed UART operation mode 3, description of ................................................................... 415 high-speed UART register ................................... 399 high-speed UART, block diagram of .................... 394 high-speed UART, operation of ........................... 411 high-speed UART, pin related to.......................... 397 high-speed UART, program example of .............. 417 I I/O circuit format..................................................... 26 I/O map ................................................................ 538 I/O port, function of .................................................96 I2C address control register (IACR) ......................454 I2C address register (IADR)..................................463 I2C bus control register (IBCR) .............................458 I2C bus interface block diagram ...........................447 I2C bus interface, note on using ...........................469 I2C bus interface, pin related to ............................451 I2C bus interface, register related to.....................453 I2C bus protocol ....................................................466 I2C bus status register (IBSR) ..............................456 I2C bus system .....................................................466 I2C clock control register (ICCR) ..........................461 I2C data register (IDAR) .......................................464 I2C interface function ............................................446 I2C interface interrupt source................................450 I2C interface, register and vector table address related to interrupt of ..................................465 I2C master transmission/reception program, sample flowchart of .................................................471 2C slave transmission/reception program, sample I flowchart of .................................................472 instruction cycle (tinst) ............................................71 instruction map .....................................................559 instruction, symbol used with................................544 internal shift clock, when using an........................436 interrupt acceptance control bit ..............................42 interrupt at bus error .............................................465 interrupt at data transfer completion.....................465 interrupt during external interrupt circuit 1 operation ...................................................................320 interrupt during external interrupt circuit 2 operation ...................................................................336 interrupt during serial I/O operation ......................431 interrupt level setting register (ILR1, ILR2, ILR3, ILR4), structure of.........................................49 interrupt occurring when interval timer function is selected ......................................................239 interrupt occurring when pulse width measurement function is selected.....................................239 interrupt processing ................................................51 interrupt processing time ........................................54 interrupt related to pulse width count timer...........227 interrupt request from peripheral function...............47 interrupt source of external interrupt circuit 1 .......312 interrupt when interval timer function is active......150 interrupt when interval timer function is active (watch interrupt) .....................................................174 interrupt when interval timer function operating and CH12PWM mode in effect ..........................201 interval timer function ...................................144, 288 571 interval timer function (reload timer mode), program example 1 for ............................................. 250 interval timer function (square wave output function) ........................................................... 180, 224 interval timer function (timebase timer), operation of ................................................................... 151 interval timer function (watch interrupt) ................ 168 interval timer function (watch prescaler), operation of ................................................................... 175 interval timer function mode, interrupt in .............. 297 interval timer function when operating, and CH12PWM mode in effect, interrupt .......... 201 interval timer function, operation of ...... 202, 241, 298 interval timer function, program example of ......... 304 item to be confirmed for inquiry ............................ 567 L long pulse width, measurement of ....................... 245 low power consumption (standby) mode and when counter is suspended, operation in ............302 lower address setting register (WRARL1 to WRARL6) ................................................................... 483 M main clock mode, operation in ............................... 73 main clock oscillation stabilization wait time and reset source .......................................................... 58 main clock output, pin for ..................................... 494 main clock, oscillation stabilization wait time of...... 75 mask option.......................................................... 560 master transfer mode, program example for ........ 473 MB89530/530H/530A series, available model of ..... 5 MB89530/530H/530A series, entire block diagram of ..................................................................... 10 MB89530/530H/530A series, feature of ................... 2 MB89F538/F538L serial programming connection, basic configuration of ................................. 526 memory access mode, selection of ........................ 93 memory map .......................................................... 35 memory map in EPROM mode ............................ 561 memory space...................................................... 563 memory space, configuration of ............................. 34 method of writing to EPROM................................ 563 mode data .............................................................. 92 mode fetch ............................................................. 61 mode pin ................................................................ 61 mode pin (MOD0, 1)............................................... 92 multiple interrupt..................................................... 53 N noise canceller on P42/INT22/SO2/SDA and P43/ INT23/SI2/SCL........................................... 451 note on handling device ......................................... 30 note on specifying multiple sector........................ 519 note on use of clock output .................................. 498 note on using 16-bit timer/counter ....................... 303 note on using 8-bit serial I/O ................................ 439 note on using timebase timer............................... 153 note on using watch prescaler ............................. 177 note on using watchdog timer .............................. 163 note on writing data.............................................. 516 O operation in low power consumption (standby) mode and when counter is suspended ................ 302 operation in main clock mode ................................ 73 operation in sleep mode......................................... 79 operation in standby mode and for stop before completion ................................................. 212 operation in standby mode and for stop request.. 247 operation in stop mode .......................................... 80 operation in subclock mode ................................... 74 operation in watch mode........................................ 82 operation mode 0 of UART/SIO, explanation of... 379 operation mode 0, 1, 2, and 4, explanation of...... 412 operation of A/D conversion function ................... 356 operation of clock supply function........................ 175 operation of counter function ............................... 300 operation of interval timer function....................... 298 operation of interval timer function (watch prescaler) ................................................................... 175 operation of port 0 and port 1............................... 104 operation of port 2................................................ 112 operation of port 3................................................ 119 operation of port 4................................................ 129 operation of port 5................................................ 134 operation of port 6................................................ 141 operation of UART/SIO ........................................ 378 operation of watch prescaler................................ 176 operation of watchdog timer................................. 161 oscillation stabilization wait reset state .................. 61 oscillation stabilization wait time ...................... 75, 91 oscillation stabilization wait time and timebase timer interrupt...................................................... 150 oscillation stabilization wait time and watch interrupt ................................................................... 174 other instruction ................................................... 558 572 P P30/PPG03/MCO and P31/SCK1 (UCK1)/LMCO, block diagram of ........................................ 494 P50/AN0 to P57/AN7 pin, block diagram of ......... 347 pin for external interrupt circuit 1.......................... 313 pin for external interrupt circuit 1, block diagram of ................................................................... 314 pin for external interrupt circuit 2.......................... 329 pin for external interrupt circuit 2, block diagram of ................................................................... 330 pin function, explanation of .................................... 21 pin layout for DIP-64P-M01 and MDP-64C-P02 .... 11 pin layout for FPT-64P-M03 and FPT-64P-M09 .... 12 pin layout for FPT-64P-M06 and MQP-64C-P01 ... 13 pin of 6-bit PPG timer........................................... 261 pin of port 0 and port 1........................................... 99 pin of port 2 .......................................................... 106 pin of port 3 .......................................................... 114 pin of port 4 .......................................................... 121 pin of port 5 .......................................................... 131 pin related to A/D converter ................................. 346 pin related to high-speed UART........................... 397 pin related to high-speed UART, block diagram of ................................................................... 398 pin related to pulse width count timer .................. 228 pin related to pulse width count timer, block diagrams of................................................................ 229 pin related to UART/SIO, block diagram of.......... 366 pin state after reading mode data .......................... 62 pin state during reset ............................................. 62 pin status in each mode ....................................... 564 port 0 and port 1 pull-up resistor control register (PURR0 and PURR1) ................................ 102 port 0 and port 1 register, function of ................... 101 port 0 and port 1, block diagram of ...................... 100 port 0 and port 1, configuration of .......................... 99 port 0 and port 1, operation of.............................. 104 port 0 and port 1, pin of.......................................... 99 port 0 and port 1, register (PDR0 and DDR0) of.. 100 port 2 register, function of .................................... 110 port 2, block diagram of ....................................... 107 port 2, configuration of ......................................... 106 port 2, operation of............................................... 112 port 2, pin of ......................................................... 106 port 2, register of.................................................. 109 port 3 register, function of .................................... 117 port 3, block diagram of ....................................... 115 port 3, configuration of ......................................... 114 port 3, operation of............................................... 119 port 3, pin of..........................................................114 port 3, register of ..................................................116 port 4 register, function of.....................................125 port 4, block diagram of ........................................122 port 4, configuration of..........................................121 port 4, operation of ...............................................129 port 4, pin of..........................................................121 port 4, register of ..................................................124 port 5 register, function of.....................................133 port 5, block diagram of ........................................132 port 5, configuration of..........................................131 port 5, operation of ...............................................134 port 5, pin of..........................................................131 port 5, register of ..................................................132 port 6 pull-up resistor control register (PURR6) ...138 port 6 register, function of.....................................138 port 6, block diagram of ........................................136 port 6, configuration of..........................................135 port 6, operation of ...............................................141 precaution to be taken when selecting model ..........8 prescaler operation...............................................210 program access to flash memory .........................523 program example for master transfer mode .........473 program example for serial input ..........................444 program example for serial output........................442 programming socket adapter................................563 programming yield ................................................562 pulse width count timer, block diagram of ............226 pulse width count timer, interrupt related to..........227 pulse width count timer, note on using .................248 pulse width count timer, pin related to ..................228 pulse width count timer, register related to...........231 pulse width measurement function .......................225 pulse width measurement function, operation of ..244 PWC pulse width control register 1 (PCR1) .........232 PWC pulse width control register 2 (PCR2) .........235 PWC reload buffer register (RLBR) ......................237 PWM compare register 1 (COMR1) .....................197 PWM compare register 2 (COMR2) .....................199 PWM control register 1 (CNTR1)..........................191 PWM control register 2 (CNTR2)..........................193 PWM control register 3 (CNTR3)..........................195 PWM timer function ..............................................184 PWM timer function operation ..............................204 PWM timer function program, example of ............220 R read-modify-write operation..................................552 receiving operation in CLK asynchronous mode ..381 573 reception error in CLK asynchronous mode......... 382 reception interrupt ........................................ 377, 410 recommended screening condition ...................... 562 register (PDR0 and DDR0) of port 0 and port 1 ... 100 register and vector table address for high-speed UART interrupt ........................................... 410 register and vector table address related to interrupt of UART/SIO .............................................. 377 register and vector table for external interrupt circuit 1 interrupt ...................................................... 320 register and vector table for external interrupt circuit 2 interrupt ...................................................... 336 register and vector table related to 2-channel 8-bit PWM timer interrupt ................................... 201 register and vector table related to pulse width count timer interrupt ............................................. 240 register and vector table related to timebase timer interrupt ...................................................... 150 register and vector table related to watch prescaler interrupt ...................................................... 174 register bank pointer (RP), structure of .................. 44 register for external interrupt circuit 2...................332 register of 6-bit PPG timer.................................... 262 register of port 2 ...................................................109 register of port 3 ...................................................116 register of port 4 ...................................................124 register of port 5 ...................................................132 register related to A/D converter .......................... 348 register related to pulse width count timer............231 register related to UART/SIO ............................... 367 reset on RAM content, effect of.............................. 61 reset operation, overview of ................................... 60 reset source ........................................................... 57 ROM writer adapter .............................................. 561 S sample clock output program ............................... 499 sample I/O port program ......................................142 sector configuration.............................................. 503 sector erase .................................................512, 513 sector erase suspend ................................... 509, 510 sector, restarting erasing of.................................. 522 sector, suspending erasing of .............................. 521 serial data register (SDR)..................................... 430 serial I/O function ................................................. 420 serial input data register (SIDR) ........................... 374 serial input data register (SIDR1) .........................408 serial input is completed, operation when ............435 serial input operation ............................................434 serial mode control register 1 (SMC1).................. 368 574 serial mode control register 1 (SMC11) ............... 400 serial mode control register 2 (SMC12) ............... 402 serial mode control register 2 (SMC2) ................. 370 serial mode register (SMR) .................................. 428 serial output data register (SODR)....................... 375 serial output data register (SODR1)..................... 409 serial output is completed, operation when.......... 433 serial output operation ......................................... 432 serial programming (when ower supplied by flash MCU programmer), example of connection for ................................................................... 531 serial programming (when power supplied by user), example of connection for.......................... 529 serial rate control register (SRC1) ....................... 404 serial status/data register (SSD1) ........................ 406 serial status/data register (SSD2) ........................ 372 setting read/reset state ........................................ 515 single chip mode .................................................... 92 sleep mode, operation in........................................ 79 software reset, watchdog timer reset ................... 523 special instruction ................................................ 549 specifying address ............................................... 516 specifying multiple sector, note on....................... 519 specifying sector .................................................. 519 stack area for interrupt processing......................... 56 stack operation at interrupt return .......................... 55 stack operation at start of interrupt processing ...... 55 standby control register (STBC)............................. 83 standby mode ........................................................ 77 standby mode and interrupt, transition to............... 90 standby mode by interrupt, release of.................... 90 standby mode, operating state in........................... 78 standby mode, precaution in setting ...................... 91 start condition....................................................... 466 state transition diagram 1 (power-on reset and dual clock system) ............................................... 85 state transition diagram 2 (single clock system option) ..................................................................... 88 stop condition....................................................... 467 stop mode, operation in ......................................... 80 subclock mode, operation in .................................. 74 subclock output, pin for ........................................ 494 subclock, oscillation stabilization wait time of ........ 76 system clock control register (SYCC), structure of 69 T timebase timer control register (TBTC)................ 148 timebase timer interrupt, oscillation stabilization wait time and ..................................................... 150 timebase timer, block diagram of ......................... 146 timebase timer, note on using.............................. 153 timebase timer, program example of ................... 154 time-based timer, operation of ............................. 152 timer control register (TMCR) .............................. 294 timer count register (TCR) ................................... 296 transfer clock selection ........................................ 391 transfer data format.............................................. 380 transfer instruction ............................................... 553 transmission interrupt................................... 377, 410 transmitting operation in CLK asynchronous mode ................................................................... 383 U UART/SIO operation mode, explanation of.......... 384 UART/SIO, block diagram of................................ 363 UART/SIO, function of ......................................... 362 UART/SIO, operation of ....................................... 378 UART/SIO, pin related to ..................................... 365 upper address setting register (WRARH1 to WRARH6) .................................................. 481 usable EPROM .................................................... 563 V vector table area .................................................... 36 W watch mode, operation in .......................................82 watch prescaler control register (WPCR) .............172 watch prescaler, block diagram of ........................170 watch prescaler, note on using.............................177 watch prescaler, operation of ...............................176 watch prescaler, program example of ..................178 watchdog timer control register (WDTC) ..............159 watchdog timer function........................................156 watchdog timer, block diagram of.........................157 watchdog timer, note on using..............................163 watchdog timer, operation of ................................161 watchdog timer, program example of ...................164 wild register data test register (WROR) and its relationship to the wild register ...................487 Wild register enable register (WREN) ..................485 wild register function.............................................476 wild register function, block diagram of ................477 wild register function, register related to...............478 wild register operation ..........................................488 write ......................................................................509 writing data ...........................................................516 writing data, note on .............................................516 writing to EPROM, method of ...............................563 writing to flash memory.........................................502 575 576 CM25-10135-5E FUJITSU SEMICONDUCTOR * CONTROLLER MANUAL F2MC-8L 8-BIT MICROCONTROLLER MB89530/530H/530A Series HARDWARE MANUAL October 2002 the fifth edition Published Edited FUJITSU LIMITED Electronic Devices Standardization Promoting Dept. |
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